mtd: rawnand: Ensure the nand chip supports cached reads
authorRouven Czerwinski <r.czerwinski@pengutronix.de>
Fri, 22 Sep 2023 14:17:16 +0000 (16:17 +0200)
committerMiquel Raynal <miquel.raynal@bootlin.com>
Mon, 16 Oct 2023 08:47:22 +0000 (10:47 +0200)
Both the JEDEC and ONFI specification say that read cache sequential
support is an optional command. This means that we not only need to
check whether the individual controller supports the command, we also
need to check the parameter pages for both ONFI and JEDEC NAND flashes
before enabling sequential cache reads.

This fixes support for NAND flashes which don't support enabling cache
reads, i.e. Samsung K9F4G08U0F or Toshiba TC58NVG0S3HTA00.

Sequential cache reads are now only available for ONFI and JEDEC
devices, if individual vendors implement this, it needs to be enabled
per vendor.

Tested on i.MX6Q with a Samsung NAND flash chip that doesn't support
sequential reads.

Fixes: 003fe4b9545b ("mtd: rawnand: Support for sequential cache reads")
Cc: stable@vger.kernel.org
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230922141717.35977-1-r.czerwinski@pengutronix.de
drivers/mtd/nand/raw/nand_base.c
drivers/mtd/nand/raw/nand_jedec.c
drivers/mtd/nand/raw/nand_onfi.c
include/linux/mtd/jedec.h
include/linux/mtd/onfi.h
include/linux/mtd/rawnand.h

index d4b5515..1fcac40 100644 (file)
@@ -5110,6 +5110,9 @@ static void rawnand_check_cont_read_support(struct nand_chip *chip)
 {
        struct mtd_info *mtd = nand_to_mtd(chip);
 
+       if (!chip->parameters.supports_read_cache)
+               return;
+
        if (chip->read_retries)
                return;
 
index 8367577..b3cc8f3 100644 (file)
@@ -94,6 +94,9 @@ int nand_jedec_detect(struct nand_chip *chip)
                goto free_jedec_param_page;
        }
 
+       if (p->opt_cmd[0] & JEDEC_OPT_CMD_READ_CACHE)
+               chip->parameters.supports_read_cache = true;
+
        memorg->pagesize = le32_to_cpu(p->byte_per_page);
        mtd->writesize = memorg->pagesize;
 
index f15ef90..861975e 100644 (file)
@@ -303,6 +303,9 @@ int nand_onfi_detect(struct nand_chip *chip)
                           ONFI_FEATURE_ADDR_TIMING_MODE, 1);
        }
 
+       if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_READ_CACHE)
+               chip->parameters.supports_read_cache = true;
+
        onfi = kzalloc(sizeof(*onfi), GFP_KERNEL);
        if (!onfi) {
                ret = -ENOMEM;
index 0b6b59f..56047a4 100644 (file)
@@ -21,6 +21,9 @@ struct jedec_ecc_info {
 /* JEDEC features */
 #define JEDEC_FEATURE_16_BIT_BUS       (1 << 0)
 
+/* JEDEC Optional Commands */
+#define JEDEC_OPT_CMD_READ_CACHE       BIT(1)
+
 struct nand_jedec_params {
        /* rev info and features block */
        /* 'J' 'E' 'S' 'D'  */
index a7376f9..55ab2e4 100644 (file)
@@ -55,6 +55,7 @@
 #define ONFI_SUBFEATURE_PARAM_LEN      4
 
 /* ONFI optional commands SET/GET FEATURES supported? */
+#define ONFI_OPT_CMD_READ_CACHE                BIT(1)
 #define ONFI_OPT_CMD_SET_GET_FEATURES  BIT(2)
 
 struct nand_onfi_params {
index 90a141b..c29ace1 100644 (file)
@@ -225,6 +225,7 @@ struct gpio_desc;
  * struct nand_parameters - NAND generic parameters from the parameter page
  * @model: Model name
  * @supports_set_get_features: The NAND chip supports setting/getting features
+ * @supports_read_cache: The NAND chip supports read cache operations
  * @set_feature_list: Bitmap of features that can be set
  * @get_feature_list: Bitmap of features that can be get
  * @onfi: ONFI specific parameters
@@ -233,6 +234,7 @@ struct nand_parameters {
        /* Generic parameters */
        const char *model;
        bool supports_set_get_features;
+       bool supports_read_cache;
        DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
        DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);