Compiling the kernel
--------------------
- - Make sure you have at least gcc 4.9 available.
+ - Make sure you have at least gcc 5.1 available.
For more information, refer to :ref:`Documentation/process/changes.rst <changes>`.
Please note that you can still run a.out user programs with this kernel.
case the Linux IRQ numbers cannot be dynamically assigned and the legacy
mapping should be used.
-As the name implies, the *_legacy() functions are deprecated and only
+As the name implies, the \*_legacy() functions are deprecated and only
exist to ease the support of ancient platforms. No new users should be
-added.
+added. Same goes for the \*_simple() functions when their use results
+in the legacy behaviour.
The legacy map assumes a contiguous range of IRQ numbers has already
been allocated for the controller and that the IRQ number can be
- enum:
- amlogic,p281
- oranth,tx3-mini
+ - jethome,jethub-j80
- const: amlogic,s905w
- const: amlogic,meson-gxl
items:
- enum:
- amlogic,s400
+ - jethome,jethub-j100
- const: amlogic,a113d
- const: amlogic,meson-axg
- enum:
- amediatech,x96-max
- amlogic,u200
+ - radxa,zero
- seirobotics,sei510
- const: amlogic,g12a
- const: atmel,sama5d3
- const: atmel,sama5
+ - description: CalAmp LMU5000 board
+ items:
+ - const: calamp,lmu5000
+ - const: atmel,at91sam9g20
+ - const: atmel,at91sam9
+
+ - description: Exegin Q5xR5 board
+ items:
+ - const: exegin,q5xr5
+ - const: atmel,at91sam9g20
+ - const: atmel,at91sam9
+
- items:
- enum:
- atmel,sama5d31
items:
- enum:
- raspberrypi,400
+ - raspberrypi,4-compute-module
- raspberrypi,4-model-b
- const: brcm,bcm2711
$nodename:
const: '/'
compatible:
- items:
- - enum:
- - brcm,bcm58522
- - brcm,bcm58525
- - brcm,bcm58535
- - brcm,bcm58622
- - brcm,bcm58623
- - brcm,bcm58625
- - brcm,bcm88312
- - const: brcm,nsp
+ oneOf:
+ - description: BCM58522 based boards
+ items:
+ - enum:
+ - brcm,bcm958522er
+ - const: brcm,bcm58522
+ - const: brcm,nsp
+
+ - description: BCM58525 based boards
+ items:
+ - enum:
+ - brcm,bcm958525er
+ - brcm,bcm958525xmc
+ - const: brcm,bcm58525
+ - const: brcm,nsp
+
+ - description: BCM58535 based boards
+ items:
+ - const: brcm,bcm58535
+ - const: brcm,nsp
+
+ - description: BCM58622 based boards
+ items:
+ - enum:
+ - brcm,bcm958622hr
+ - const: brcm,bcm58622
+ - const: brcm,nsp
+
+ - description: BCM58623 based boards
+ items:
+ - enum:
+ - brcm,bcm958623hr
+ - const: brcm,bcm58623
+ - const: brcm,nsp
+
+ - description: BCM58625 based boards
+ items:
+ - enum:
+ - brcm,bcm958625hr
+ - brcm,bcm958625k
+ - meraki,mx64
+ - meraki,mx64-a0
+ - meraki,mx64w
+ - meraki,mx64w-a0
+ - meraki,mx65
+ - meraki,mx65w
+ - const: brcm,bcm58625
+ - const: brcm,nsp
+
+ - description: BCM88312 based boards
+ items:
+ - enum:
+ - brcm,bcm988312hr
+ - const: brcm,bcm88312
+ - const: brcm,nsp
additionalProperties: true
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
+ - qcom,kryo560
- qcom,kryo685
- qcom,scorpion
- const: mediatek,mt6580
- items:
- enum:
+ - fairphone,fp1
- mundoreader,bq-aquaris5
- const: mediatek,mt6589
- items:
"#clock-cells":
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
The 'SoC' element must be one of the following strings:
apq8016
+ apq8026
apq8074
apq8084
apq8096
sdm660
sdm845
sdx55
+ sdx65
sm8150
sm8250
sm8350
- items:
- enum:
+ - lge,lenok
+ - const: qcom,apq8026
+
+ - items:
+ - enum:
+ - asus,nexus4-mako
+ - asus,nexus7-flo
+ - sony,xperia-yuga
- qcom,apq8064-cm-qs600
- qcom,apq8064-ifc6410
- const: qcom,apq8064
- enum:
- fairphone,fp2
- lge,hammerhead
+ - samsung,klte
- sony,xperia-amami
- sony,xperia-castor
- sony,xperia-honami
- items:
- enum:
+ - qcom,sdx65-mtp
+ - const: qcom,sdx65
+
+ - items:
+ - enum:
- qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
+ - renesas,m3nulcb
- enum:
+ - renesas,r8a779m0
- renesas,r8a779m1
+ - renesas,r8a779m2
- renesas,r8a779m3
+ - renesas,r8a779m4
+ - renesas,r8a779m5
+ - renesas,r8a779m8
- enum:
- renesas,r8a7795
- renesas,r8a77961
+ - renesas,r8a77965
- description: R-Car M3-N (R8A77965)
items:
- const: renesas,falcon-cpu
- const: renesas,r8a779a0
+ - description: R-Car H3e (R8A779M0)
+ items:
+ - enum:
+ - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
+ - const: renesas,r8a779m0
+ - const: renesas,r8a7795
+
- description: R-Car H3e-2G (R8A779M1)
items:
- enum:
- const: renesas,r8a779m1
- const: renesas,r8a7795
+ - description: R-Car M3e (R8A779M2)
+ items:
+ - enum:
+ - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
+ - const: renesas,r8a779m2
+ - const: renesas,r8a77961
+
- description: R-Car M3e-2G (R8A779M3)
items:
- enum:
- const: renesas,r8a779m3
- const: renesas,r8a77961
+ - description: R-Car M3Ne (R8A779M4)
+ items:
+ - enum:
+ - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
+ - const: renesas,r8a779m4
+ - const: renesas,r8a77965
+
+ - description: R-Car M3Ne-2G (R8A779M5)
+ items:
+ - enum:
+ - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
+ - const: renesas,r8a779m5
+ - const: renesas,r8a77965
+
+ - description: R-Car E3e (R8A779M6)
+ items:
+ - enum:
+ - renesas,ebisu # Ebisu
+ - const: renesas,r8a779m6
+ - const: renesas,r8a77990
+
+ - description: R-Car D3e (R8A779M7)
+ items:
+ - enum:
+ - renesas,draak # Draak
+ - const: renesas,r8a779m7
+ - const: renesas,r8a77995
+
+ - description: R-Car H3Ne (R8A779M8)
+ items:
+ - enum:
+ - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
+ - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
+ - const: renesas,r8a779m8
+ - const: renesas,r8a7795
+
- description: RZ/N1D (R9A06G032)
items:
- enum:
- const: firefly,roc-rk3328-cc
- const: rockchip,rk3328
+ - description: Firefly ROC-RK3328-PC
+ items:
+ - const: firefly,roc-rk3328-pc
+ - const: rockchip,rk3328
+
- description: Firefly ROC-RK3399-PC
items:
- enum:
- firefly,roc-rk3399-pc-mezzanine
- const: rockchip,rk3399
+ - description: Firefly ROC-RK3399-PC-PLUS
+ items:
+ - enum:
+ - firefly,roc-rk3399-pc-plus
+ - const: rockchip,rk3399
+
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
- const: google,veyron
- const: rockchip,rk3288
+ - description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100)
+ items:
+ - const: google,scarlet-rev15-sku0
+ - const: google,scarlet-rev15
+ - const: google,scarlet-rev14-sku0
+ - const: google,scarlet-rev14
+ - const: google,scarlet-rev13-sku0
+ - const: google,scarlet-rev13
+ - const: google,scarlet-rev12-sku0
+ - const: google,scarlet-rev12
+ - const: google,scarlet-rev11-sku0
+ - const: google,scarlet-rev11
+ - const: google,scarlet-rev10-sku0
+ - const: google,scarlet-rev10
+ - const: google,scarlet-rev9-sku0
+ - const: google,scarlet-rev9
+ - const: google,scarlet-rev8-sku0
+ - const: google,scarlet-rev8
+ - const: google,scarlet-rev7-sku0
+ - const: google,scarlet-rev7
+ - const: google,scarlet-rev6-sku0
+ - const: google,scarlet-rev6
+ - const: google,scarlet-rev5-sku0
+ - const: google,scarlet-rev5
+ - const: google,scarlet
+ - const: google,gru
+ - const: rockchip,rk3399
+
- description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10)
items:
- const: google,scarlet-rev15-sku7
- const: pine64,rockpro64
- const: rockchip,rk3399
+ - description: Pine64 Quartz64 Model A
+ items:
+ - const: pine64,quartz64-a
+ - const: rockchip,rk3566
+
- description: Radxa Rock
items:
- const: radxa,rock
- const: rockchip,rk3188
- - description: Radxa ROCK Pi 4A/B/C
+ - description: Radxa ROCK Pi 4A/A+/B/B+/C
items:
- enum:
- radxa,rockpi4a
+ - radxa,rockpi4a-plus
- radxa,rockpi4b
+ - radxa,rockpi4b-plus
- radxa,rockpi4c
- const: radxa,rockpi4
- const: rockchip,rk3399
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3399-pmu
+ - rockchip,rk3568-pmu
required:
- compatible
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3399-pmu
+ - rockchip,rk3568-pmu
- const: syscon
- const: simple-mfd
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
- const: samsung,exynos7
+ - description: Exynos Auto v9 based boards
+ items:
+ - enum:
+ - samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
+ - const: samsung,exynosautov9
+
required:
- compatible
- sprd,sp9863a-1h10
- const: sprd,sc9863a
+ - items:
+ - enum:
+ - sprd,ums512-1h10
+ - const: sprd,ums512
+
additionalProperties: true
...
- const: toradex,apalis_t30
- const: nvidia,tegra30
- items:
- - const: toradex,apalis_t30-eval-v1.1
+ - const: toradex,apalis_t30-v1.1-eval
- const: toradex,apalis_t30-eval
- const: toradex,apalis_t30-v1.1
- const: toradex,apalis_t30
- enum:
- ti,am654-evm
- siemens,iot2050-basic
+ - siemens,iot2050-basic-pg2
- siemens,iot2050-advanced
+ - siemens,iot2050-advanced-pg2
- const: ti,am654
- description: K3 J721E SoC
- items:
+ oneOf:
- const: ti,j721e
+ - items:
+ - enum:
+ - ti,j721e-evm
+ - ti,j721e-sk
+ - const: ti,j721e
- description: K3 J7200 SoC
- items:
+ oneOf:
- const: ti,j7200
+ - items:
+ - enum:
+ - ti,j7200-evm
+ - const: ti,j7200
- description: K3 AM642 SoC
items:
- xlnx,zynqmp-zcu102-revA
- xlnx,zynqmp-zcu102-revB
- xlnx,zynqmp-zcu102-rev1.0
+ - xlnx,zynqmp-zcu102-rev1.1
- const: xlnx,zynqmp-zcu102
- const: xlnx,zynqmp
- const: xlnx,zynqmp-zcu111
- const: xlnx,zynqmp
+ - description: Xilinx Kria SOMs
+ items:
+ - const: xlnx,zynqmp-sm-k26-rev1
+ - const: xlnx,zynqmp-sm-k26-revB
+ - const: xlnx,zynqmp-sm-k26-revA
+ - const: xlnx,zynqmp-sm-k26
+ - const: xlnx,zynqmp
+
+ - description: Xilinx Kria SOMs (starter)
+ items:
+ - const: xlnx,zynqmp-smk-k26-rev1
+ - const: xlnx,zynqmp-smk-k26-revB
+ - const: xlnx,zynqmp-smk-k26-revA
+ - const: xlnx,zynqmp-smk-k26
+ - const: xlnx,zynqmp
+
additionalProperties: true
...
interrupts:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- "#clock-cells"
- compatible
dma-names:
const: audio-rx
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
interrupts:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
interrupts:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
DISP function blocks
====================
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
+Optional properties:
+- resets: list of phandle + reset specifier pair, as described in [1].
+
+[1] Documentation/devicetree/bindings/reset/reset.txt
+
MIPI TX Configuration Module
============================
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Device tree binding for NVIDIA Tegra NVDEC
+
+description: |
+ NVDEC is the hardware video decoder present on NVIDIA Tegra210
+ and newer chips. It is located on the Host1x bus and typically
+ programmed through Host1x channels.
+
+maintainers:
+ - Thierry Reding <treding@gmail.com>
+ - Mikko Perttunen <mperttunen@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^nvdec@[0-9a-f]*$"
+
+ compatible:
+ enum:
+ - nvidia,tegra210-nvdec
+ - nvidia,tegra186-nvdec
+ - nvidia,tegra194-nvdec
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: nvdec
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: nvdec
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+ interconnects:
+ items:
+ - description: DMA read memory client
+ - description: DMA read 2 memory client
+ - description: DMA write memory client
+
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: read-1
+ - const: write
+
+ nvidia,host1x-class:
+ description: |
+ Host1x class of the engine, used to specify the targeted engine
+ when programming the engine through Host1x channels or when
+ configuring engine-specific behavior in Host1x.
+ default: 0xf0
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra186-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+ #include <dt-bindings/power/tegra186-powergate.h>
+ #include <dt-bindings/reset/tegra186-reset.h>
+
+ nvdec@15480000 {
+ compatible = "nvidia,tegra186-nvdec";
+ reg = <0x15480000 0x40000>;
+ clocks = <&bpmp TEGRA186_CLK_NVDEC>;
+ clock-names = "nvdec";
+ resets = <&bpmp TEGRA186_RESET_NVDEC>;
+ reset-names = "nvdec";
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA186_SID_NVDEC>;
+ };
- const: allwinner,sun8i-v3s-emac
- const: allwinner,sun50i-a64-emac
- items:
- - const: allwinner,sun50i-h6-emac
+ - enum:
+ - allwinner,sun20i-d1-emac
+ - allwinner,sun50i-h6-emac
- const: allwinner,sun50i-a64-emac
reg:
Tegra194 EP mode:
-----------------
- pcie_ep@141a0000 {
+ pcie-ep@141a0000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS host controller Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+
+description: |
+ Each Samsung UFS host controller instance should have its own node.
+ This binding define Samsung specific binding other then what is used
+ in the common ufshcd bindings
+ [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+
+properties:
+
+ compatible:
+ enum:
+ - samsung,exynos7-ufs
+
+ reg:
+ items:
+ - description: HCI register
+ - description: vendor specific register
+ - description: unipro register
+ - description: UFS protector register
+
+ reg-names:
+ items:
+ - const: hci
+ - const: vs_hci
+ - const: unipro
+ - const: ufsp
+
+ clocks:
+ items:
+ - description: ufs link core clock
+ - description: unipro main clock
+
+ clock-names:
+ items:
+ - const: core_clk
+ - const: sclk_unipro_main
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: ufs-phy
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - phys
+ - phy-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ ufs: ufs@15570000 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x15570000 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
+ <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_phy>;
+ phy-names = "ufs-phy";
+ };
+...
description: B&R Industrial Automation GmbH
"^bticino,.*":
description: Bticino International
+ "^calamp,.*":
+ description: CalAmp Corp.
"^calaosystems,.*":
description: CALAO Systems SAS
"^calxeda,.*":
description: Exar Corporation
"^excito,.*":
description: Excito
+ "^exegin,.*":
+ description: Exegin Technologies Limited
"^ezchip,.*":
description: EZchip Semiconductor
"^facebook,.*":
description: JEDEC Solid State Technology Association
"^jesurun,.*":
description: Shenzhen Jesurun Electronics Business Dept.
+ "^jethome,.*":
+ description: JetHome (IP Sokolov P.A.)
"^jianda,.*":
description: Jiandangjing Technology Co., Ltd.
"^kam,.*":
- 0x88A8 traffic will not be received unless VLAN stripping is disabled with
the following command::
- # ethool -K <ethX> rxvlan off
+ # ethtool -K <ethX> rxvlan off
- 0x88A8/0x8100 double VLANs cannot be used with 0x8100 or 0x8100/0x8100 VLANS
configured on the same port. 0x88a8/0x8100 traffic will not be received if
Device Tree bindings and board design
=====================================
-This section references ``Documentation/devicetree/bindings/net/dsa/sja1105.txt``
+This section references ``Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml``
and aims to showcase some potential switch caveats.
RMII PHY role and out-of-band signaling
====================== =============== ========================================
Program Minimal version Command to check the version
====================== =============== ========================================
-GNU C 4.9 gcc --version
+GNU C 5.1 gcc --version
Clang/LLVM (optional) 10.0.1 clang --version
GNU make 3.81 make --version
binutils 2.23 ld -v
编译内核
---------
- - 确保您至少有gcc 4.9可用。
+ - 确保您至少有gcc 5.1可用。
有关更多信息，请参阅 :ref:`Documentation/process/changes.rst <changes>` 。
请注意，您仍然可以使用此内核运行a.out用户程序。
編譯內核
---------
- - 確保您至少有gcc 4.9可用。
+ - 確保您至少有gcc 5.1可用。
有關更多信息，請參閱 :ref:`Documentation/process/changes.rst <changes>` 。
請注意，您仍然可以使用此內核運行a.out用戶程序。
S: Maintained
F: drivers/platform/x86/amd-pmc.*
-AMD POWERPLAY
+AMD POWERPLAY AND SWSMU
M: Evan Quan <evan.quan@amd.com>
L: amd-gfx@lists.freedesktop.org
S: Supported
T: git https://gitlab.freedesktop.org/agd5f/linux.git
-F: drivers/gpu/drm/amd/pm/powerplay/
+F: drivers/gpu/drm/amd/pm/
AMD PTDMA DRIVER
M: Sanjay R Mehta <sanju.mehta@amd.com>
F: arch/arm/mach-pxa/vpac270.c
ARM/VT8500 ARM ARCHITECTURE
-M: Tony Prisk <linux@prisktech.co.nz>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
+S: Orphan
F: Documentation/devicetree/bindings/i2c/i2c-wmt.txt
F: arch/arm/mach-vt8500/
F: drivers/clocksource/timer-vt8500.c
S: Supported
T: git git://anongit.freedesktop.org/tegra/linux.git
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+F: Documentation/devicetree/bindings/gpu/host1x/
F: drivers/gpu/drm/tegra/
F: drivers/gpu/host1x/
F: include/linux/host1x.h
F: drivers/scsi/nsp32*
NIOS2 ARCHITECTURE
-M: Ley Foon Tan <ley.foon.tan@intel.com>
+M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
F: arch/nios2/
NITRO ENCLAVES (NE)
F: drivers/pci/controller/pci-ixp4xx.c
PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
-M: Jonathan Derrick <jonathan.derrick@intel.com>
+M: Nirmal Patel <nirmal.patel@linux.intel.com>
+R: Jonathan Derrick <jonathan.derrick@linux.dev>
L: linux-pci@vger.kernel.org
S: Supported
F: drivers/pci/controller/vmd.c
S: Supported
F: drivers/char/pcmcia/scr24x_cs.c
-SCSI CDROM DRIVER
-M: Jens Axboe <axboe@kernel.dk>
-L: linux-scsi@vger.kernel.org
-S: Maintained
-W: http://www.kernel.dk
-F: drivers/scsi/sr*
-
SCSI RDMA PROTOCOL (SRP) INITIATOR
M: Bart Van Assche <bvanassche@acm.org>
L: linux-rdma@vger.kernel.org
SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
M: Karsten Graul <kgraul@linux.ibm.com>
-M: Guvenc Gulce <guvenc@linux.ibm.com>
L: linux-s390@vger.kernel.org
S: Supported
W: http://www.ibm.com/developerworks/linux/linux390/
F: arch/x86/boot/video*
SWIOTLB SUBSYSTEM
-M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+M: Christoph Hellwig <hch@infradead.org>
L: iommu@lists.linux-foundation.org
S: Supported
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/konrad/swiotlb.git
+W: http://git.infradead.org/users/hch/dma-mapping.git
+T: git git://git.infradead.org/users/hch/dma-mapping.git
F: arch/*/kernel/pci-swiotlb.c
F: include/linux/swiotlb.h
F: kernel/dma/swiotlb.c
F: drivers/usb/misc/chaoskey.c
USB CYPRESS C67X00 DRIVER
-M: Peter Korsgaard <jacmet@sunsite.dk>
L: linux-usb@vger.kernel.org
-S: Maintained
+S: Orphan
F: drivers/usb/c67x00/
USB DAVICOM DM9601 DRIVER
-M: Peter Korsgaard <jacmet@sunsite.dk>
+M: Peter Korsgaard <peter@korsgaard.com>
L: netdev@vger.kernel.org
S: Maintained
W: http://www.linux-usb.org/usbnet
F: tools/lib/bpf/xsk*
XEN BLOCK SUBSYSTEM
-M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
M: Roger Pau Monné <roger.pau@citrix.com>
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
S: Supported
F: drivers/net/xen-netback/*
XEN PCI SUBSYSTEM
-M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+M: Juergen Gross <jgross@suse.com>
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
S: Supported
F: arch/x86/pci/*xen*
F: sound/xen/*
XEN SWIOTLB SUBSYSTEM
-M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+M: Juergen Gross <jgross@suse.com>
+M: Stefano Stabellini <sstabellini@kernel.org>
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
L: iommu@lists.linux-foundation.org
S: Supported
VERSION = 5
PATCHLEVEL = 15
SUBLEVEL = 0
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
NAME = Opossums on Parade
# *DOCUMENTATION*
DEBUG_CFLAGS :=
-# Workaround for GCC versions < 5.0
-# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801
-ifdef CONFIG_CC_IS_GCC
-DEBUG_CFLAGS += $(call cc-ifversion, -lt, 0500, $(call cc-option, -fno-var-tracking-assignments))
-endif
-
ifdef CONFIG_DEBUG_INFO
ifdef CONFIG_DEBUG_INFO_SPLIT
select NEED_SG_DMA_LENGTH
select VIRT_TO_BUS
select GENERIC_IRQ_PROBE
- select GENERIC_PCI_IOMAP if PCI
+ select GENERIC_PCI_IOMAP
select AUTO_IRQ_AFFINITY if SMP
select GENERIC_IRQ_SHOW
select ARCH_WANT_IPC_PARSE_VERSION
config ALPHA_JENSEN
bool "Jensen"
- depends on BROKEN
select HAVE_EISA
help
DEC PC 150 AXP (aka Jensen): This is a very old Digital system - one
extern void __remlu(void);
extern void __divqu(void);
extern void __remqu(void);
+extern unsigned long __udiv_qrnnd(unsigned long *, unsigned long, unsigned long , unsigned long);
* Change virtual addresses to physical addresses and vv.
*/
#ifdef USE_48_BIT_KSEG
-static inline unsigned long virt_to_phys(void *address)
+static inline unsigned long virt_to_phys(volatile void *address)
{
return (unsigned long)address - IDENT_ADDR;
}
return (void *) (address + IDENT_ADDR);
}
#else
-static inline unsigned long virt_to_phys(void *address)
+static inline unsigned long virt_to_phys(volatile void *address)
{
unsigned long phys = (unsigned long)address;
extern unsigned long __direct_map_base;
extern unsigned long __direct_map_size;
-static inline unsigned long __deprecated virt_to_bus(void *address)
+static inline unsigned long __deprecated virt_to_bus(volatile void *address)
{
unsigned long phys = virt_to_phys(address);
unsigned long bus = phys + __direct_map_base;
* convinced that I need one of the newer machines.
*/
-static inline unsigned int jensen_local_inb(unsigned long addr)
+__EXTERN_INLINE unsigned int jensen_local_inb(unsigned long addr)
{
return 0xff & *(vuip)((addr << 9) + EISA_VL82C106);
}
-static inline void jensen_local_outb(u8 b, unsigned long addr)
+__EXTERN_INLINE void jensen_local_outb(u8 b, unsigned long addr)
{
*(vuip)((addr << 9) + EISA_VL82C106) = b;
mb();
}
-static inline unsigned int jensen_bus_inb(unsigned long addr)
+__EXTERN_INLINE unsigned int jensen_bus_inb(unsigned long addr)
{
long result;
return __kernel_extbl(result, addr & 3);
}
-static inline void jensen_bus_outb(u8 b, unsigned long addr)
+__EXTERN_INLINE void jensen_bus_outb(u8 b, unsigned long addr)
{
jensen_set_hae(0);
*(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ALPHA_SETUP_H
+#define __ALPHA_SETUP_H
+
+#include <uapi/asm/setup.h>
+
+/*
+ * We leave one page for the initial stack page, and one page for
+ * the initial process structure. Also, the console eats 3 MB for
+ * the initial bootloader (one of which we can reclaim later).
+ */
+#define BOOT_PCB 0x20000000
+#define BOOT_ADDR 0x20000000
+/* Remove when official MILO sources have ELF support: */
+#define BOOT_SIZE (16*1024)
+
+#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
+#define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
+#else
+#define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
+#endif
+
+#define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS)
+#define SWAPPER_PGD KERNEL_START
+#define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
+#define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
+#define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
+#define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
+
+#define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
+
+/*
+ * This is setup by the secondary bootstrap loader. Because
+ * the zero page is zeroed out as soon as the vm system is
+ * initialized, we need to copy things out into a more permanent
+ * place.
+ */
+#define PARAM ZERO_PGE
+#define COMMAND_LINE ((char *)(absolute_pointer(PARAM + 0x0000)))
+#define INITRD_START (*(unsigned long *) (PARAM+0x100))
+#define INITRD_SIZE (*(unsigned long *) (PARAM+0x108))
+
+#endif
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ALPHA_SETUP_H
-#define __ALPHA_SETUP_H
+#ifndef _UAPI__ALPHA_SETUP_H
+#define _UAPI__ALPHA_SETUP_H
#define COMMAND_LINE_SIZE 256
-/*
- * We leave one page for the initial stack page, and one page for
- * the initial process structure. Also, the console eats 3 MB for
- * the initial bootloader (one of which we can reclaim later).
- */
-#define BOOT_PCB 0x20000000
-#define BOOT_ADDR 0x20000000
-/* Remove when official MILO sources have ELF support: */
-#define BOOT_SIZE (16*1024)
-
-#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
-#define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
-#else
-#define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
-#endif
-
-#define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS)
-#define SWAPPER_PGD KERNEL_START
-#define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
-#define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
-#define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
-#define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
-
-#define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
-
-/*
- * This is setup by the secondary bootstrap loader. Because
- * the zero page is zeroed out as soon as the vm system is
- * initialized, we need to copy things out into a more permanent
- * place.
- */
-#define PARAM ZERO_PGE
-#define COMMAND_LINE ((char*)(PARAM + 0x0000))
-#define INITRD_START (*(unsigned long *) (PARAM+0x100))
-#define INITRD_SIZE (*(unsigned long *) (PARAM+0x108))
-
-#endif
+#endif /* _UAPI__ALPHA_SETUP_H */
*
* Code supporting the Jensen.
*/
+#define __EXTERN_INLINE
+#include <asm/io.h>
+#include <asm/jensen.h>
+#undef __EXTERN_INLINE
+
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/ptrace.h>
-#define __EXTERN_INLINE inline
-#include <asm/io.h>
-#include <asm/jensen.h>
-#undef __EXTERN_INLINE
-
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
ev67-$(CONFIG_ALPHA_EV67) := ev67-
lib-y = __divqu.o __remqu.o __divlu.o __remlu.o \
+ udiv-qrnnd.o \
udelay.o \
$(ev6-y)memset.o \
$(ev6-y)memcpy.o \
# along with GCC; see the file COPYING. If not, write to the
# Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
# MA 02111-1307, USA.
+#include <asm/export.h>
.set noreorder
.set noat
ret $31,($26),1
.end __udiv_qrnnd
+EXPORT_SYMBOL(__udiv_qrnnd)
obj-$(CONFIG_MATHEMU) += math-emu.o
-math-emu-objs := math.o qrnnd.o
+math-emu-objs := math.o
egress:
return si_code;
}
-
-EXPORT_SYMBOL(__udiv_qrnnd);
usb_a9263.dtb \
at91-foxg20.dtb \
at91-kizbox.dtb \
+ at91-lmu5000.dtb \
at91sam9g20ek.dtb \
at91sam9g20ek_2mmc.dtb \
tny_a9g20.dtb \
at91-kizboxmini-base.dtb \
at91-kizboxmini-mb.dtb \
at91-kizboxmini-rd.dtb \
+ at91-q5xr5.dtb \
at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
+ bcm2711-rpi-cm4-io.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm4709-tplink-archer-c9-v1.dtb \
+ bcm47094-asus-rt-ac88u.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-linksys-panamera.dtb \
bcm47094-luxul-abr-4500.dtb \
bcm958525xmc.dtb \
bcm958622hr.dtb \
bcm958623hr.dtb \
+ bcm958625-meraki-mx64.dtb \
+ bcm958625-meraki-mx64-a0.dtb \
+ bcm958625-meraki-mx64w.dtb \
+ bcm958625-meraki-mx64w-a0.dtb \
+ bcm958625-meraki-mx65.dtb \
+ bcm958625-meraki-mx65w.dtb \
bcm958625hr.dtb \
bcm988312hr.dtb \
bcm958625k.dtb
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8026-lge-lenok.dtb \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
&am33xx_pinmux {
+ compatible = "pinconf-single";
pinctrl-names = "default";
pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree file for CalAmp LMU5000 board
+ *
+ * Copyright (C) 2013 Adam Porter <porter.adam@gmail.com>
+ */
+
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+ model = "CalAmp LMU5000";
+ compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9";
+
+ chosen {
+ bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2";
+ };
+
+ memory {
+ reg = <0x20000000 0x4000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock@0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <18432000>;
+ };
+ };
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&ebi {
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ kernel@0 {
+ label = "kernel";
+ reg = <0x0 0x400000>;
+ };
+
+ rootfs@400000 {
+ label = "rootfs";
+ reg = <0x400000 0x3C00000>;
+ };
+
+ user1@4000000 {
+ label = "user1";
+ reg = <0x4000000 0x2000000>;
+ };
+
+ user2@6000000 {
+ label = "user2";
+ reg = <0x6000000 0x2000000>;
+ };
+ };
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&pinctrl {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usb0 {
+ pinctrl_usb1_vbus_gpio: usb0_vbus_gpio {
+ atmel,pins = <AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&ssc0 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ssc0_tx>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usart0 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+};
+
+&usart2 {
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <2>;
+ status = "okay";
+};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree file for Exegin Q5xR5 board
+ *
+ * Copyright (C) 2014 Owen Kirby <osk@exegin.com>
+ */
+
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+ model = "Exegin Q5x (rev5)";
+ compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
+ };
+
+ memory {
+ reg = <0x20000000 0x0>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock@0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <18432000>;
+ };
+
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <18432000>;
+ };
+ };
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&ebi {
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x1000000 0x800000>;
+ bank-width = <2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ kernel@0 {
+ label = "kernel";
+ reg = <0x0 0x200000>;
+ };
+
+ rootfs@200000 {
+ label = "rootfs";
+ reg = <0x200000 0x600000>;
+ };
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&pinctrl {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi0_npcs0: spi0_npcs0 {
+ atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi0_npcs1: spi0_npcs1 {
+ atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi1_npcs0: spi1_npcs0 {
+ atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi1_npcs1: spi1_npcs1 {
+ atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
+ cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91boot@0 {
+ label = "at91boot";
+ reg = <0x0 0x4000>;
+ };
+
+ uenv@4000 {
+ label = "uboot-env";
+ reg = <0x4000 0x4000>;
+ };
+
+ uboot@8000 {
+ label = "uboot";
+ reg = <0x8000 0x3E000>;
+ };
+ };
+
+ spidev@1 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <1>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
+ cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <0>;
+ };
+
+ spidev@1 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <1>;
+ };
+};
+
+&usart0 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <2>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Atmel SAMA5D27 SoM1";
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
at24@50 {
bias-disable;
};
+ pinctrl_i2c0_gpio: i2c0_gpio {
+ pinmux = <PIN_PD21__GPIO>,
+ <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+
pinctrl_qspi1_default: qspi1_default {
sck_cs {
pinmux = <PIN_PB5__QSPI1_SCK>,
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&pioA PIN_PA24 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PA23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
};
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
bias-disable;
};
+ pinctrl_i2c1_gpio: i2c1_gpio {
+ pinmux = <PIN_PD4__GPIO>,
+ <PIN_PD5__GPIO>;
+ bias-disable;
+ };
+
+
pinctrl_isc_base: isc_base {
pinmux = <PIN_PC21__ISC_PCK>,
<PIN_PC22__ISC_VSYNC>,
bias-disable;
};
+ pinctrl_i2c3_gpio: i2c3_gpio {
+ pinmux = <PIN_PA24__GPIO>,
+ <PIN_PA23__GPIO>;
+ bias-disable;
+ };
+
pinctrl_flx4_default: flx4_uart_default {
pinmux = <PIN_PC28__FLEXCOM4_IO0>,
<PIN_PC29__FLEXCOM4_IO1>,
clock-frequency = <24000000>;
};
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-wilc1000";
+ reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pinctrl_wilc_pwrseq>;
+ pinctrl-names = "default";
+ };
};
&flx1 {
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
+
+ pinctrl_sdmmc1_default: sdmmc1_default {
+ cmd-data {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-disable;
+ };
+
+ conf-ck {
+ pinmux = <PIN_PA22__SDMMC1_CK>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_wilc_default: wilc_default {
+ conf-irq {
+ pinmux = <PIN_PB25__GPIO>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_wilc_pwrseq: wilc_pwrseq {
+ conf-ce-nrst {
+ pinmux = <PIN_PA27__GPIO>,
+ <PIN_PA29__GPIO>;
+ bias-disable;
+ };
+
+ conf-rtcclk {
+ pinmux = <PIN_PB13__PCK1>;
+ bias-disable;
+ };
+ };
+};
+
+&sdmmc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ no-1-8-v;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+
+ wilc: wifi@0 {
+ reg = <0>;
+ compatible = "microchip,wilc1000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wilc_default>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 9>;
+ clock-names = "rtc";
+ interrupts = <PIN_PB25 IRQ_TYPE_NONE>;
+ interrupt-parent = <&pioA>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
+ assigned-clock-rates = <32768>;
+ };
};
};
&i2c0 { /* mikrobus i2c */
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
&i2c1 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
bias-disable;
};
+ pinctrl_i2c1_gpio: i2c1_gpio {
+ pinmux = <PIN_PD19__GPIO>,
+ <PIN_PD20__GPIO>;
+ bias-disable;
+ };
+
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PD0__GPIO>;
bias-pull-up;
bias-disable;
};
+ pinctrl_i2c0_gpio: i2c0_gpio {
+ pinmux = <PIN_PD21__GPIO>,
+ <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+
pinctrl_mikrobus1_an: mikrobus1_an {
pinmux = <PIN_PD26__GPIO>;
bias-disable;
};
};
+&adc {
+ vddana-supply = <&vddout25>;
+ vref-supply = <&vddout25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vddcpu>;
};
&macb1 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
- pinctrl@fffff400 {
+ pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom Northstar Plus Ax stepping-specific bindings.
+ * Notable differences from B0+ are the secondary-boot-reg and
+ * lack of DMA coherency.
+ */
+
+&cpu1 {
+ secondary-boot-reg = <0xffff042c>;
+};
+
+&dma {
+ /delete-property/ dma-coherent;
+};
+
+&sdio {
+ /delete-property/ dma-coherent;
+};
+
+&amac0 {
+ /delete-property/ dma-coherent;
+};
+
+&amac1 {
+ /delete-property/ dma-coherent;
+};
+
+&amac2 {
+ /delete-property/ dma-coherent;
+};
+
+&ehci0 {
+ /delete-property/ dma-coherent;
+};
+
+&mailbox {
+ /delete-property/ dma-coherent;
+};
+
+&xhci {
+ /delete-property/ dma-coherent;
+};
+
+&ehci0 {
+ /delete-property/ dma-coherent;
+};
+
+&ohci0 {
+ /delete-property/ dma-coherent;
+};
+
+&i2c0 {
+ /delete-property/ dma-coherent;
+};
+
+&sata {
+ /delete-property/ dma-coherent;
+};
+
+&pcie0 {
+ /delete-property/ dma-coherent;
+};
+
+&pcie1 {
+ /delete-property/ dma-coherent;
+};
+
+&pcie2 {
+ /delete-property/ dma-coherent;
+};
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- mpcore@19000000 {
+ mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
};
};
- axi@18000000 {
+ axi: axi@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011c40c>;
#address-cells = <1>;
status = "disabled";
};
- sdio: sdhci@21000 {
+ sdio: mmc@21000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x21000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
xhci: usb@29000 {
status = "disabled";
};
+ mdio: mdio@32000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x32000 0x8>;
+ #size-cells = <0>;
+ #address-cells = <1>;
+ };
+
+ mdio-mux@32000 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ reg = <0x32000 0x4>;
+ mux-mask = <0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio>;
+
+ mdio_int: mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,ns-bx-usb3-phy";
+ reg = <0x10>;
+ usb3-dmp-syscon = <&usb3_dmp>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ mdio_ext: mdio@200 {
+ reg = <0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
};
};
- usb3_phy: usb3-phy@104000 {
- compatible = "brcm,ns-bx-usb3-phy";
- reg = <0x104000 0x1000>,
- <0x032000 0x1000>;
- reg-names = "dmp", "ccb-mii";
- #phy-cells = <0>;
- status = "disabled";
+ usb3_dmp: syscon@104000 {
+ reg = <0x104000 0x1000>;
};
};
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
};
};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
- };
-
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
};
};
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+};
+
&ddc0 {
status = "okay";
};
status = "okay";
};
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- bus-width = <4>;
- non-removable;
- mmc-pwrseq = <&wifi_pwrseq>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* EMMC2 is used to drive the SD card */
&emmc2 {
vqmmc-supply = <&sd_io_1v8_reg>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
- };
};
/* uart1 is mapped to the pin header */
&vec {
status = "disabled";
};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711-rpi-cm4.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ model = "Raspberry Pi Compute Module 4 IO Board";
+
+ leds {
+ led-act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&ddc0 {
+ status = "okay";
+};
+
+&ddc1 {
+ status = "okay";
+};
+
+&gpio {
+ /*
+ * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "RGMII_MDIO",
+ "RGMIO_MDC",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ /* Shared with SPI flash */
+ "PWM0_MISO",
+ "PWM1_MOSI",
+ "STATUS_LED_G_CLK",
+ "SPIFLASH_CE_N",
+ "SDA0",
+ "SCL0",
+ "RGMII_RXCLK",
+ "RGMII_RXCTL",
+ "RGMII_RXD0",
+ "RGMII_RXD1",
+ "RGMII_RXD2",
+ "RGMII_RXD3",
+ "RGMII_TXCLK",
+ "RGMII_TXCTL",
+ "RGMII_TXD0",
+ "RGMII_TXD1",
+ "RGMII_TXD2",
+ "RGMII_TXD3";
+};
+
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi1 {
+ status = "okay";
+};
+
+&genet {
+ status = "okay";
+};
+
+&pixelvalve0 {
+ status = "okay";
+};
+
+&pixelvalve1 {
+ status = "okay";
+};
+
+&pixelvalve2 {
+ status = "okay";
+};
+
+&pixelvalve4 {
+ status = "okay";
+};
+
+&vc4 {
+ status = "okay";
+};
+
+&vec {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711.dtsi"
+#include "bcm2711-rpi.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
+
+/ {
+ compatible = "raspberrypi,4-compute-module", "brcm,bcm2711";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ sd_io_1v8_reg: sd_io_1v8_reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-sd-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-settling-time-us = <5000>;
+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ status = "okay";
+ };
+
+ sd_vcc_reg: sd_vcc_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+};
+
+/* EMMC2 is used to drive the eMMC */
+&emmc2 {
+ bus-width = <8>;
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ vmmc-supply = <&sd_vcc_reg>;
+ broken-cd;
+ /* Even the IP block is limited to 100 MHz
+ * this provides a throughput gain
+ */
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "ANT1",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "ANT2";
+
+ ant1: ant1-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ /* internal antenna enabled */
+ output-high;
+ line-name = "ant1";
+ };
+
+ ant2: ant2-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ /* external antenna disabled */
+ output-low;
+ line-name = "ant2";
+ };
+};
+
+&genet {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+};
+
+&genet_mdio {
+ phy1: ethernet-phy@0 {
+ /* No PHY interrupt */
+ reg = <0x0>;
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
+ uart-has-rtscts;
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
+};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
- };
+&bt {
+ shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
};
&gpio {
};
&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
- bus-width = <4>;
- mmc-pwrseq = <&wifi_pwrseq>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
};
&sdhost {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
- };
};
&uart1 {
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
+
+&wifi_pwrseq {
+ reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+};
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
status = "okay";
};
-/*
- * SDHCI is used to control the SDIO for wireless
- *
- * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
- * by a single GPIO. We can't give GPIO control to one of the drivers,
- * otherwise the other part would get unexpectedly disturbed.
- */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
bus-width = <4>;
};
-/* uart0 communicates with the BT module */
+/* uart0 communicates with the BT module
+ *
+ * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
+ * by a single GPIO. We can't give GPIO control to one of the drivers,
+ * otherwise the other part would get unexpectedly disturbed.
+ */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- };
};
/* uart1 is mapped to the pin header */
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
linux,default-trigger = "default-on";
};
};
+};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
- };
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
status = "okay";
};
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
- mmc-pwrseq = <&wifi_pwrseq>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
- };
};
/* uart1 is mapped to the pin header */
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
+};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
- };
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
- };
};
/* uart1 is mapped to the pin header */
status = "okay";
};
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
- mmc-pwrseq = <&wifi_pwrseq>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
status = "okay";
bus-width = <4>;
};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ };
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ status = "okay";
+
+ bt: bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ };
+};
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
};
};
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <&gmac2>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Asus RT-AC88U";
+
+ chosen {
+ bootargs = "earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
+ };
+
+ nvram@1c080000 {
+ compatible = "brcm,nvram";
+ reg = <0x1c080000 0x00180000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "white:power";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ wan-red {
+ label = "red:wan";
+ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ lan {
+ label = "white:lan";
+ gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2 {
+ label = "white:usb2";
+ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ehci_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ usb3 {
+ label = "white:usb3";
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ehci_port1>, <&xhci_port1>;
+ linux,default-trigger = "usbport";
+ };
+
+ wps {
+ label = "white:wps";
+ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
+ };
+
+ reset {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi {
+ label = "Wi-Fi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led {
+ label = "Backlight";
+ linux,code = <KEY_BRIGHTNESS_ZERO>;
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab";
+ status = "okay";
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ sw0_p5: port@5 {
+ reg = <5>;
+ label = "extsw";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ ethernet = <&gmac1>;
+ label = "cpu";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ ethernet = <&gmac2>;
+ label = "cpu";
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&nandcs {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "nvram";
+ reg = <0x00080000 0x00180000>;
+ };
+
+ partition@200000 {
+ label = "firmware";
+ reg = <0x00200000 0x07e00000>;
+ compatible = "brcm,trx";
+ };
+ };
+};
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <&gmac2>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
};
};
- mdio-bus-mux@18003000 {
+ mdio-mux@18003000 {
/* BIT(9) = 1 => external mdio */
mdio@200 {
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;
};
};
};
+
+&switch {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
bootargs = " console=ttyS0,115200n8 earlycon";
};
- memory {
+ memory@0 {
reg = <0x00000000 0x08000000>;
device_type = "memory";
};
reg = <0x50>;
pagesize = <32>;
read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac_address: mac-address@66 {
+ reg = <0x66 0x6>;
+ };
};
};
};
*/
};
+&gmac0 {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&mac_address>;
+};
+
&gmac1 {
status = "disabled";
};
};
};
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "poe";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ };
+ };
+};
#size-cells = <1>;
interrupt-parent = <&gic>;
- chipcommonA@18000000 {
+ chipcommon-a-bus@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x00001000>;
#address-cells = <1>;
};
};
- mpcore@19000000 {
+ mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
#address-cells = <1>;
};
- mdio-bus-mux@18003000 {
- compatible = "mdio-mux-mmioreg";
+ mdio-mux@18003000 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- dmu@1800c000 {
+ dmu-bus@1800c000 {
compatible = "simple-bus";
ranges = <0 0x1800c000 0x1000>;
#address-cells = <1>;
gmac0: ethernet@5000 {
reg = <0x5000 0x1000>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch: switch@1e {
+ compatible = "brcm,bcm53125";
+ reg = <0x1e>;
+
+ status = "disabled";
+
+ /* ports are defined in board DTS */
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
};
gmac1: ethernet@b000 {
model = "NorthStar SVK (BCM94708)";
compatible = "brcm,bcm94708", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
model = "NorthStar SVK (BCM94709)";
compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
/ {
model = "NorthStar Plus SVK (BCM958522ER)";
- compatible = "brcm,bcm58522", "brcm,nsp";
+ compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
/ {
model = "NorthStar Plus SVK (BCM958525ER)";
- compatible = "brcm,bcm58525", "brcm,nsp";
+ compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
/ {
model = "NorthStar Plus XMC (BCM958525xmc)";
- compatible = "brcm,bcm58525", "brcm,nsp";
+ compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
/ {
model = "NorthStar Plus SVK (BCM958622HR)";
- compatible = "brcm,bcm58622", "brcm,nsp";
+ compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
/ {
model = "NorthStar Plus SVK (BCM958623HR)";
- compatible = "brcm,bcm58623", "brcm,nsp";
+ compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm958625-meraki-mx6x-common.dtsi"
+
+/ {
+ keys {
+ compatible = "gpio-keys-polled";
+ autorepeat;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ /* green:wan1-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ /* green:wan1-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ /* green:wan2-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ /* green:wan2-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ /* amber:power */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led-5 {
+ /* white:status */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&axi {
+ mdio-mux@3f1c0 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ reg = <0x3f1c0 0x4>;
+ mux-mask = <0x2000>;
+ mdio-parent-bus = <&mdio_ext>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port6: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port7: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port8: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port9: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port10: phy@4 {
+ reg = <4>;
+ };
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ reg = <0x10>;
+ dsa,member = <1 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ethernet = <&sgmii1>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ phy-handle = <&phy_port6>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan9";
+ phy-handle = <&phy_port7>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan10";
+ phy-handle = <&phy_port8>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan11";
+ phy-handle = <&phy_port9>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan12";
+ phy-handle = <&phy_port10>;
+ };
+ };
+ };
+ };
+
+ mdio-mii@2000 {
+ reg = <0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port1: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port2: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port3: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port4: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port5: phy@4 {
+ reg = <4>;
+ };
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ reg = <0x10>;
+ dsa,member = <2 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ethernet = <&sgmii0>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ phy-handle = <&phy_port1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan4";
+ phy-handle = <&phy_port2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan5";
+ phy-handle = <&phy_port3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan6";
+ phy-handle = <&phy_port4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan7";
+ phy-handle = <&phy_port5>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+ dsa,member = <0 0>;
+
+ ports {
+ port@0 {
+ label = "wan1";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "wan2";
+ reg = <1>;
+ };
+
+ sgmii0: port@4 {
+ label = "sw0";
+ reg = <4>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ sgmii1: port@5 {
+ label = "sw1";
+ reg = <5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm958625-meraki-mx6x-common.dtsi"
+
+/ {
+
+ keys {
+ compatible = "gpio-keys-polled";
+ autorepeat;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ /* green:lan1-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 19 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ /* green:lan1-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ /* green:lan2-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ /* green:lan2-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 20 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ /* green:lan3-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <4>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
+ };
+
+ led-5 {
+ /* green:lan3-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <5>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
+ };
+
+ led-6 {
+ /* green:lan4-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+ };
+
+ led-7 {
+ /* green:lan4-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <7>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
+ };
+
+ led-8 {
+ /* green:wan-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <8>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 30 GPIO_ACTIVE_LOW>;
+ };
+
+ led-9 {
+ /* green:wan-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <9>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 29 GPIO_ACTIVE_LOW>;
+ };
+
+ led-a {
+ /* amber:power */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-b {
+ /* white:status */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+
+ ports {
+ port@0 {
+ label = "lan1";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "lan2";
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "lan3";
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "lan4";
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "wan";
+ reg = <4>;
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+#include "bcm-nsp-ax.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64(A0)";
+ compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64";
+ compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+#include "bcm-nsp-ax.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64W(A0)";
+ compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64W";
+ compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-alamo.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65";
+ compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65W.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-alamo.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65W";
+ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm-nsp.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm 1 50000>;
+ max-brightness = <255>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm 2 50000>;
+ max-brightness = <255>;
+ };
+
+ led-3 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm 3 50000>;
+ max-brightness = <255>;
+ };
+ };
+};
+
+&amac2 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
+ };
+};
+
+&nand_controller {
+ nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "shmoo";
+ reg = <0x80000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "bootkernel1";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@400000 {
+ label = "nvram";
+ reg = <0x400000 0x100000>;
+ };
+
+ partition@500000 {
+ label = "bootkernel2";
+ reg = <0x500000 0x300000>;
+ };
+
+ partition@800000 {
+ label = "ubi";
+ reg = <0x800000 0x3f700000>;
+ };
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_leds>;
+
+ pwm_leds: pwm_leds {
+ function = "pwm";
+ groups = "pwm1_grp", "pwm2_grp", "pwm3_grp";
+ };
+};
+
+&pwm {
+ status = "okay";
+ #pwm-cells = <2>;
+};
+
+&uart0 {
+ clock-frequency = <62500000>;
+ status = "okay";
+};
/ {
model = "NorthStar Plus SVK (BCM958625HR)";
- compatible = "brcm,bcm58625", "brcm,nsp";
+ compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
/ {
model = "NorthStar Plus SVK (BCM958625K)";
- compatible = "brcm,bcm58625", "brcm,nsp";
+ compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
/ {
model = "NorthStar Plus SVK (BCM988312HR)";
- compatible = "brcm,bcm88312", "brcm,nsp";
+ compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
/* USB 3 support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
};
};
+ target-module@59000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x59000020 0x4>;
+ reg-names = "rev";
+ clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000000 0x1000>;
+
+ bb2d: gpu@0 {
+ compatible = "vivante,gc";
+ reg = <0x0 0x700>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>;
+ clock-names = "core";
+ };
+ };
+
aes1_target: target-module@4b500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b500080 0x4>,
};
ethernet@20000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan9221", "smsc,lan9115";
reg = <0x20000000 0x10000>;
phy-mode = "mii";
interrupt-parent = <&gpio0>;
ldo4_reg: LDO4 {
regulator-name = "VDD_RTC_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "VMIPI_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo7_reg: LDO7 {
regulator-name = "VDD_AUD_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
ldo8_reg: LDO8 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
ldo9_reg: LDO9 {
regulator-name = "DVDD_SWB_2.8V";
regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo10_reg: LDO10 {
regulator-name = "VDD_PLL_1.1V";
regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo11_reg: LDO11 {
regulator-name = "VDD_AUD_3V";
regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
};
ldo14_reg: LDO14 {
regulator-name = "AVDD18_SWB_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo17_reg: LDO17 {
regulator-name = "VDD_SWB_3.3V";
regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo21_reg: LDO21 {
regulator-name = "VDD_MIF_1.2V";
regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "VDD_ARM_1.2V";
regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
buck2_reg: BUCK2 {
regulator-name = "VDD_INT_1.1V";
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
buck1_reg: BUCK1 {
regulator-name = "VDD_MIF";
regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
buck2_reg: BUCK2 {
regulator-name = "VDD_ARM";
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
buck3_reg: BUCK3 {
regulator-name = "VDD_INT";
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
buck4_reg: BUCK4 {
regulator-name = "VDD_G3D";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
buck5_reg: BUCK5 {
regulator-name = "VDD_M12";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
buck6_reg: BUCK6 {
regulator-name = "VDD12_5M";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
buck9_reg: BUCK9 {
regulator-name = "VDDF28_EMMC";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
vinl8-supply = <&buck8_reg>;
vinl9-supply = <&buck8_reg>;
- s5m8767,pmic-buck2-dvs-voltage = <1300000>;
- s5m8767,pmic-buck3-dvs-voltage = <1100000>;
- s5m8767,pmic-buck4-dvs-voltage = <1200000>;
s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
<&gpd1 1 GPIO_ACTIVE_HIGH>,
<&gpd1 2 GPIO_ACTIVE_HIGH>;
sata: sata@122f0000 {
compatible = "snps,dwc-ahci";
- samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
status = "okay";
phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
micrel,led-mode = <1>;
};
status = "disabled";
};
+ usb0: usb@11200000 {
+ compatible = "mediatek,mt7623-musb",
+ "mediatek,mtk-musb";
+ reg = <0 0x11200000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ status = "disabled";
+ };
+
+ u2phy1: t-phy@11210000 {
+ compatible = "mediatek,mt7623-tphy",
+ "mediatek,generic-tphy-v1";
+ reg = <0 0x11210000 0 0x0800>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port2: usb-phy@11210800 {
+ reg = <0 0x11210800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7623-audsys",
"mediatek,mt2701-audsys",
clock-names = "ethif";
};
+&usb0 {
+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
+};
+
&usb1 {
power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
};
status = "okay";
};
+&pio {
+ musb_pins: musb {
+ pins-musb {
+ pinmux = <MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS>;
+ };
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins_a>;
status = "okay";
};
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&musb_pins>;
+ status = "okay";
+ usb-role-switch;
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&usb1 {
vusb33-supply = <®_3p3v>;
vbus-supply = <®_5v>;
status = "okay";
};
+&u2phy1 {
+ status = "okay";
+};
+
&u3phy1 {
status = "okay";
};
};
};
-&pcie {
+&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
+ status = "okay";
};
&pciephy1 {
#reset-cells = <1>;
};
- pcie: pcie@1a140000 {
+ pciecfg: pciecfg@1a140000 {
+ compatible = "mediatek,generic-pciecfg", "syscon";
+ reg = <0x1a140000 0x1000>;
+ };
+
+ pcie1: pcie@1a145000 {
compatible = "mediatek,mt7629-pcie";
device_type = "pci";
- reg = <0x1a140000 0x1000>,
- <0x1a145000 0x1000>;
- reg-names = "subsys","port1";
+ reg = <0x1a145000 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "pcie_irq";
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P1_AUX_EN>,
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+ status = "disabled";
- pcie1: pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- ranges;
- num-lanes = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
-
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
};
#include <dt-bindings/thermal/thermal.h>
-cpu_thermal: cpu_thermal {
+cpu_thermal: cpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
coefficients = <0 20000>;
#sound-dai-cells = <0>;
};
- spi_lcd: spi_lcd {
+ spi_lcd: spi {
compatible = "spi-gpio";
#address-cells = <0x1>;
#size-cells = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_gpio_pins>;
- gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
pinctrl-0 = <&bmp085_pins>;
interrupt-parent = <&gpio4>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */
+ vdda-supply = <&vio>;
+ vddd-supply = <&vio>;
};
/* accelerometer */
compatible = "bosch,bma180";
reg = <0x41>;
pinctrl-names = "default";
- pintcrl-0 = <&bma180_pins>;
+ pinctrl-0 = <&bma180_pins>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
};
gpio-controller;
#gpio-cells = <2>;
- gta04_led0: red_aux@0 {
+ gta04_led0: led@0 {
label = "gta04:red:aux";
reg = <0x0>;
};
- gta04_led1: green_aux@1 {
+ gta04_led1: led@1 {
label = "gta04:green:aux";
reg = <0x1>;
};
- gta04_led3: red_power@3 {
+ gta04_led3: led@3 {
label = "gta04:red:power";
reg = <0x3>;
linux,default-trigger = "default-on";
};
- gta04_led4: green_power@4 {
+ gta04_led4: led@4 {
label = "gta04:green:power";
reg = <0x4>;
};
- wifi_reset: wifi_reset@6 { /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */
+ wifi_reset: led@6 {
+ /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */
reg = <0x6>;
compatible = "gpio";
};
bme280@76 {
compatible = "bosch,bme280";
reg = <0x76>;
+ vdda-supply = <&vio>;
+ vddd-supply = <&vio>;
};
};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Luca Weiss <luca@z3ntu.xyz>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "qcom-pm8226.dtsi"
+
+/ {
+ model = "LG G Watch R";
+ compatible = "lge,lenok", "qcom,apq8026";
+ qcom,board-id = <132 0x0a>;
+ qcom,msm-id = <199 0x20000>;
+
+ aliases {
+ serial0 = &blsp1_uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+ clock-frequency = <384000>;
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l15>;
+ vio-supply = <&pm8226_l22>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&rpm_requests {
+ pm8226-regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s1: s1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1275000>;
+ };
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhc1_pin_a>;
+};
+
+&tlmm {
+ sdhc1_pin_a: sdhc1-pin-active {
+ clk {
+ pins = "sdc1_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-data {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ touch_pins: touch {
+ irq {
+ pins = "gpio17";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ reset {
+ pins = "gpio16";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
&gfx3d1 30
&gfx3d1 31>;
- qcom,gpu-pwrlevels {
- compatible = "qcom,gpu-pwrlevels";
- qcom,gpu-pwrlevel@0 {
- qcom,gpu-freq = <450000000>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <450000000>;
};
- qcom,gpu-pwrlevel@1 {
- qcom,gpu-freq = <27000000>;
+
+ opp-27000000 {
+ opp-hz = /bits/ 64 <27000000>;
};
};
};
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
- compatible = "qcom,ipq4019-dk04.1-c1";
+ compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019";
soc {
dma@7984000 {
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
- compatible = "qcom,ipq4019-ap-dk04.1-c3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3", "qcom,ipq4019";
};
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
- compatible = "qcom,ipq4019-ap-dk07.1-c1";
+ compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
soc {
pci@40000000 {
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
- compatible = "qcom,ipq4019-ap-dk07.1-c2";
+ compatible = "qcom,ipq4019-ap-dk07.1-c2", "qcom,ipq4019";
soc {
pinctrl@1000000 {
/ {
model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
- compatible = "qcom,ipq8064-ap148";
+ compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
soc {
pinmux@800000 {
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
reg = <0x0 0x0>;
};
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8226", "qcom,scm";
+ clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
+ clock-names = "core", "bus", "iface";
+ };
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x80>;
+
+ #hwlock-cells = <1>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem_region: smem@3000000 {
+ reg = <0x3000000 0x100000>;
+ no-map;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8226";
+ qcom,smd-channels = "rpm_requests";
+ };
+ };
+ };
+
+ smem {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem_region>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#interrupt-cells = <3>;
};
+ apcs: syscon@f9011000 {
+ compatible = "syscon";
+ reg = <0xf9011000 0x1000>;
+ };
+
+ sdhc_1: sdhci@f9824900 {
+ compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@f98a4900 {
+ compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
+ sdhc_3: sdhci@f9864900 {
+ compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC3_APPS_CLK>,
+ <&gcc GCC_SDCC3_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
+ blsp1_uart3: serial@f991f000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991f000 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart4: serial@f9920000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf9920000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_i2c1: i2c@f9923000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9923000 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c2: i2c@f9924000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9924000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c2_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c3: i2c@f9925000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9925000 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c3_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c4: i2c@f9926000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9926000 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c4_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c5: i2c@f9927000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9927000 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c5_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8226";
reg = <0xfc400000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- };
- blsp1_uart3: serial@f991f000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf991f000 0x1000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
+ blsp1_i2c1_pins: blsp1-i2c1 {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c2_pins: blsp1-i2c2 {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c3_pins: blsp1-i2c3 {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c4_pins: blsp1-i2c4 {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c5_pins: blsp1-i2c5 {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
restart@fc4ab000 {
reg = <0xfc4ab000 0x4>;
};
+ spmi_bus: spmi@fc4cf000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg-names = "core", "intr", "cnfg";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
status = "disabled";
};
};
+
+ rpm_msg_ram: memory@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+
+ tcsr_mutex_block: syscon@fd484000 {
+ compatible = "syscon";
+ reg = <0xfd484000 0x2000>;
+ };
};
timer {
#phy-cells = <0>;
qcom,dsi-phy-index = <0>;
- clocks = <&mmcc MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
};
};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm8226_0: pm8226@0 {
+ compatible = "qcom,pm8226", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@800 {
+ compatible = "qcom,pm8941-pwrkey";
+ reg = <0x800>;
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ };
+ };
+
+ pm8226_1: pm8226@1 {
+ compatible = "qcom,pm8226", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-idb824.2814",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f0",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-idb824.2814",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
renesas,no-ether-link;
phy-handle = <&phy1>;
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c816",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
clock-frequency = <24000000>; /* 24MHz */
};
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ eeprom@50 {
+ compatible = "renesas,r1ex24128", "atmel,24c128";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+};
+
/* High resolution System tick timers */
&ostm0 {
status = "okay";
<RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
};
+ i2c3_pins: i2c3 {
+ pinmux = <RZA2_PINMUX(PORTD, 6, 1)>, /* RIIC3SCL */
+ <RZA2_PINMUX(PORTD, 7, 1)>; /* RIIC3SDA */
+ };
+
keyboard_pins: keyboard {
pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>; /* IRQ0 */
};
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
+ reset-gpios = <&pfc 270 GPIO_ACTIVE_LOW>;
vdd33a-supply = <&ape6evm_fixed_3v3>;
vddvario-supply = <&ape6evm_fixed_1v8>;
};
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f1",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ reset-gpios = <&pfc 18 GPIO_ACTIVE_LOW>;
};
};
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1560",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
micrel,led-mode = <1>;
};
status = "okay";
phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
micrel,led-mode = <1>;
};
/dts-v1/;
#include "r8a7743.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "SK-RZG1M";
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
* On some older versions of the platform (before R4.0) the phy address
* may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
*/
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
micrel,led-mode = <1>;
};
/dts-v1/;
#include "r8a7745.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "SK-RZG1E";
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
};
status = "okay";
phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
&bsc {
ethernet@18300000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0x18300000 0x1000>;
phy-mode = "mii";
};
ethernet@18000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0x18000000 0x100>;
pinctrl-0 = <ðernet_pins>;
pinctrl-names = "default";
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
pwm0: pwm@20050000 {
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "rk3066a.dtsi"
/ {
device_type = "memory";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <2500000>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
gpio-leds {
compatible = "gpio-leds";
};
};
+ vcc_2v5: vcc-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
};
};
+&saradc {
+ vref-supply = <&vcc_2v5>;
+ status = "okay";
+};
+
&uart2 {
status = "okay";
};
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 1416000 1300000
- 1200000 1175000
- 1008000 1125000
- 816000 1125000
- 600000 1100000
- 504000 1100000
- 312000 1075000
- >;
+ <1416000 1300000>,
+ <1200000 1175000>,
+ <1008000 1125000>,
+ <816000 1125000>,
+ <600000 1100000>,
+ <504000 1100000>,
+ <312000 1075000>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
/delete-node/ opp-table0;
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
cru: clock-controller@110e0000 {
};
};
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
status = "disabled";
};
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-100000000 {
};
};
- cpu_opp_table: opp_table {
+ cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-408000000 {
compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
reg = <0x10350000 0x20>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
watchdog: watchdog@10360000 {
status = "disabled";
};
- gmac: eth@30200000 {
+ gmac: ethernet@30200000 {
compatible = "rockchip,rv1108-gmac";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama5d29.dtsi - Device Tree Include file for SAMA5D29 SoC of the SAMA5D2
+ * family.
+ *
+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
+ *
+ * Author: Hari Prasath <Hari.PrasathGE@microchip.com>
+ *
+ */
+
+#include "sama5d2.dtsi"
+
+&macb0 {
+ compatible = "atmel,sama5d29-gem";
+};
clocks = <&clk32k 0>;
};
+ adc: adc@e1000000 {
+ compatible = "microchip,sama7g5-adc";
+ reg = <0xe1000000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clock-rates = <100000000>;
+ clock-names = "adc_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
+ dma-names = "rx";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ status = "disabled";
+ };
+
sdmmc0: mmc@e1204000 {
compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
reg = <0xe1204000 0x4000>;
&bsc {
ethernet@10000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan9221", "smsc,lan9115";
reg = <0x10000000 0x100>;
phy-mode = "mii";
interrupt-parent = <&irqpin0>;
io-channel-names = "aux1", "aux2";
};
- ab8500_battery: ab8500_battery {
- stericsson,battery-type = "LIPO";
- thermistor-on-batctrl;
- };
-
ab8500_fg {
compatible = "stericsson,ab8500-fg";
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
"LOW_BAT_F",
"CC_INT_CALIB",
"CCEOC";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x08>;
io-channel-names = "main_bat_v";
};
"BTEMP_HIGH",
"BTEMP_LOW_MEDIUM",
"BTEMP_MEDIUM_HIGH";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x02>,
<&gpadc 0x01>;
io-channel-names = "btemp_ball",
"VBUS_OVV",
"CH_WD_EXP",
"VBUS_CH_DROP_END";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
vddadc-supply = <&ab8500_ldo_tvout_reg>;
io-channels = <&gpadc 0x03>,
<&gpadc 0x0a>,
ab8500_chargalg {
compatible = "stericsson,ab8500-chargalg";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
};
ab8500_usb: ab8500_usb {
};
};
- ab8500_battery: ab8500_battery {
- stericsson,battery-type = "LIPO";
- thermistor-on-batctrl;
- };
-
ab8500_fg {
status = "disabled";
compatible = "stericsson,ab8500-fg";
"LOW_BAT_F",
"CC_INT_CALIB",
"CCEOC";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x08>;
io-channel-names = "main_bat_v";
};
"BTEMP_HIGH",
"BTEMP_LOW_MEDIUM",
"BTEMP_MEDIUM_HIGH";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x02>,
<&gpadc 0x01>;
io-channel-names = "btemp_ball",
"VBUS_OVV",
"CH_WD_EXP",
"VBUS_CH_DROP_END";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
vddadc-supply = <&ab8500_ldo_adc_reg>;
io-channels = <&gpadc 0x09>,
<&gpadc 0x0b>;
ab8500_chargalg {
status = "disabled";
compatible = "stericsson,ab8500-chargalg";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
};
ab8500_usb: ab8500_usb {
reg = <0x00000000 0x20000000>;
};
+ battery: battery {
+ compatible = "simple-battery";
+ battery-type = "lithium-ion-polymer";
+ thermistor-on-batctrl;
+ };
+
soc {
uart@80120000 {
pinctrl-names = "default", "sleep";
reg = <0x00000000 0x20000000>;
};
+ battery: battery {
+ compatible = "simple-battery";
+ battery-type = "lithium-ion-polymer";
+ thermistor-on-batctrl;
+ };
+
en_3v3_reg: en_3v3 {
compatible = "regulator-fixed";
regulator-name = "en-3v3-fixed-supply";
stdout-path = &serial2;
};
+ battery: battery {
+ compatible = "samsung,eb425161lu";
+ };
+
/* TI TXS0206 level translator for 2.9 V */
sd_level_translator: regulator-gpio {
compatible = "regulator-fixed";
stdout-path = &serial2;
};
+ battery: battery {
+ compatible = "samsung,eb585157lu";
+ };
+
/* TI TXS0206 level translator for 2.9 V */
sd_level_translator: regulator-gpio {
compatible = "regulator-fixed";
stdout-path = &serial2;
};
+ battery: battery {
+ compatible = "samsung,eb-l1m7flu";
+ };
+
i2c-gpio-0 {
compatible = "i2c-gpio";
sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
stdout-path = &serial2;
};
+ battery: battery {
+ compatible = "samsung,eb535151vu";
+ };
+
/* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */
ldo_3v3_reg: regulator-gpio-ldo-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&panel_default_mode>;
spi-3wire;
+ /* TYPE 3: inverse clock polarity and phase */
+ spi-cpha;
+ spi-cpol;
port {
panel_in: endpoint {
stdout-path = &serial2;
};
+ battery: battery {
+ compatible = "samsung,eb425161la";
+ };
+
/* TI TXS0206 level translator for 2.9 V */
sd_level_translator: regulator-gpio {
compatible = "regulator-fixed";
stdout-path = &serial2;
};
+ battery: battery {
+ compatible = "samsung,eb485159lu";
+ };
+
/* TI TXS0206 level translator for 2.9 V */
sd_level_translator: regulator-gpio {
compatible = "regulator-fixed";
};
};
- // eMMC
+ /*
+ * eMMC seems to be mostly Samsung KLM4G1YE4C "4YMD1R"
+ */
mmc@80005000 {
arm,primecell-periphid = <0x10480180>;
max-frequency = <100000000>;
mmc-ddr-1_8v;
no-sdio;
no-sd;
+ /* From datasheet page 26 figure 9: 300 ms set-up time for 4GB */
+ post-power-on-delay-ms = <300>;
vmmc-supply = <&ldo_3v3_reg>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mc2_a_1_default>;
};
ab8500_ldo_aux2 {
- /* Supplies the Cypress TMA140 touchscreen only with 3.3V */
+ /* Supplies the Cypress TMA140 touchscreen only with 3.0V */
regulator-name = "AUX2";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
};
ab8500_ldo_aux3 {
ab8500_ldo_aux5 {
regulator-name = "AUX5";
+ /* Intended for 1V8 for touchscreen but actually left unused */
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <2790000>;
- regulator-always-on;
};
ab8500_ldo_aux6 {
};
&pinctrl {
- /*
- * This extends the MC0 default config to include DAT32DIR
- * which is used by this machine. If we don't do this the
- * SD card does not work.
- */
sdi0 {
mc0_a_1_default {
- default_mux {
- function = "mc0";
- /* This machine uses the DAT31 pin */
- groups = "mc0_a_1", "mc0dat31dir_a_1";
- };
- default_cfg5 {
- pins = "GPIO21_AB3"; /* DAT31DIR */
- ste,config = <&out_hi>;
+ default_cfg1 {
+ /* GPIO18, 19 & 20 unused so pull down */
+ ste,config = <&gpio_in_pd>;
};
};
};
- /* The unused FBCLK needs to be pulled down on this machine */
+ /* This is a reset line for the eMMC */
sdi2 {
mc2_a_1_default {
default_cfg2 {
pins = "GPIO130_C8"; /* FBCLK */
- ste,config = <&in_pd>;
+ ste,config = <&gpio_in_pd>;
};
};
};
};
usb@7d000000 {
- compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
reg = <0x7d000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d000000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USBD>,
<&tegra_car TEGRA114_CLK_PLL_U>,
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};
usb@7d008000 {
- compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
reg = <0x7d008000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USB3>,
<&tegra_car TEGRA114_CLK_PLL_U>,
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};
};
usb@7d000000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USBD>,
<&tegra_car TEGRA124_CLK_PLL_U>,
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};
usb@7d004000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>,
<&tegra_car TEGRA124_CLK_PLL_U>,
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};
usb@7d008000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d008000 0x0 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d008000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB3>,
<&tegra_car TEGRA124_CLK_PLL_U>,
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};
bluetooth {
compatible = "brcm,bcm4329-bt";
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
/* PLLP 216MHz / 16 / 4 */
max-speed = <3375000>;
vddio-supply = <&vdd_1v8_sys>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
};
};
status = "okay";
magnetometer@c {
- compatible = "ak,ak8975";
+ compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
interrupt-parent = <&gpio>;
brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
default-brightness-level = <10>;
-
- backlight-boot-off;
};
clk32k_in: clock@0 {
};
usb@c5000000 {
- compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ compatible = "nvidia,tegra20-ehci";
reg = <0xc5000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
- nvidia,has-legacy-mode;
clocks = <&tegra_car TEGRA20_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5000000 0x4000>,
<0xc5000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USBD>,
<&tegra_car TEGRA20_CLK_PLL_U>,
nvidia,xcvr-lsfslew = <1>;
nvidia,xcvr-lsrslew = <1>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};
usb@c5004000 {
- compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ compatible = "nvidia,tegra20-ehci";
reg = <0xc5004000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
phy2: usb-phy@c5004000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
#phy-cells = <0>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};
usb@c5008000 {
- compatible = "nvidia,tegra20-ehci", "usb-ehci";
+ compatible = "nvidia,tegra20-ehci";
reg = <0xc5008000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008000 0x4000>,
<0xc5000000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USB3>,
<&tegra_car TEGRA20_CLK_PLL_U>,
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};
bluetooth {
compatible = "brcm,bcm4330-bt";
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
max-speed = <4000000>;
clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
vddio-supply = <&vdd_1v8>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
};
};
interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>;
summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>;
+ summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
summit,enable-usb-charging;
monitored-battery = <&battery_cell>;
+
+ usb_vbus: usb-vbus {
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microamp = <750000>;
+ regulator-max-microamp = <750000>;
+
+ /*
+ * SMB347 INOK input pin is connected to PMIC's
+ * ACOK output, which is fixed to ACTIVE_LOW as
+ * long as battery voltage is in a good range.
+ *
+ * Active INOK disables SMB347 output, so polarity
+ * needs to be toggled when we want to get the
+ * output.
+ */
+ summit,needs-inok-toggle;
+ };
};
};
usb@7d000000 {
compatible = "nvidia,tegra30-udc";
status = "okay";
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ vbus-supply = <&usb_vbus>;
};
usb-phy@7d000000 {
status = "okay";
- dr_mode = "peripheral";
+ dr_mode = "otg";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
bluetooth {
compatible = "brcm,bcm4330-bt";
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
max-speed = <4000000>;
clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
};
};
};
usb@7d000000 {
- compatible = "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra30-ehci";
reg = <0x7d000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra30-usb-phy";
reg = <0x7d000000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USBD>,
<&tegra_car TEGRA30_CLK_PLL_U>,
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};
usb@7d004000 {
- compatible = "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra30-ehci";
reg = <0x7d004000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra30-usb-phy";
reg = <0x7d004000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USB2>,
<&tegra_car TEGRA30_CLK_PLL_U>,
nvidia,xcvr-hsslew = <32>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};
usb@7d008000 {
- compatible = "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra30-ehci";
reg = <0x7d008000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USB3>,
<&tegra_car TEGRA30_CLK_PLL_U>,
nvidia,xcvr-hsslew = <32>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};
uprobe_notify_resume(regs);
} else {
tracehook_notify_resume(regs);
- rseq_handle_notify_resume(NULL, regs);
}
}
local_irq_disable();
select ARCH_SUPPORTS_LTO_CLANG_THIN
select ARCH_SUPPORTS_CFI_CLANG
select ARCH_SUPPORTS_ATOMIC_RMW
- select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
+ select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
select ARCH_SUPPORTS_NUMA_BALANCING
select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
select ARCH_WANT_DEFAULT_BPF_JIT
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
+ * Copyright (c) 2020 JetHome
+ * Author: Aleksandr Kazantsev <ak@tvip.ru>
+ * Author: Alexey Shevelkin <ash@tvip.ru>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-axg.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";
+ model = "JetHome JetHub J100";
+ aliases {
+ serial0 = &uart_AO; /* Console */
+ serial1 = &uart_AO_B; /* External UART (Wireless Module) */
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* 1024MB RAM */
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0x0 0x400000>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
+ regulator-always-on;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&scpi_sensors 0>;
+ trips {
+ cpu_passive: cpu-passive {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+
+ cpu_hot: cpu-hot {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "hot";
+ };
+
+ cpu_critical: cpu-critical {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&cpu_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>;
+ #gpio-cells = <1>;
+ };
+};
+
+&efuse {
+ sn: sn@32 {
+ reg = <0x32 0x20>;
+ };
+
+ eth_mac: eth_mac@0 {
+ reg = <0x0 0x6>;
+ };
+
+ bt_mac: bt_mac@6 {
+ reg = <0x6 0x6>;
+ };
+
+ wifi_mac: wifi_mac@c {
+ reg = <0xc 0x6>;
+ };
+
+ bid: bid@12 {
+ reg = <0x12 0x20>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rmii_x_pins>;
+ pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+ phy-mode = "rmii";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */
+ eth_phy0: ethernet-phy@0 {
+ /* compatible = "ethernet-phy-id0243.0c54";*/
+ max-speed = <100>;
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* Internal I2C bus (on CPU module) */
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_z_pins>;
+ pinctrl-names = "default";
+
+ /* RTC */
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "okay";
+ };
+};
+
+/* Peripheral I2C bus (on motherboard) */
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_a_x20_pins>;
+ pinctrl-names = "default";
+};
+
+/* wifi module */
+&sd_emmc_b {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr104;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* emmc storage */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* UART Bluetooth */
+&uart_B {
+ status = "okay";
+ pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* UART Console */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* UART Wireless module */
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&spicc1 {
+ status = "okay";
+ pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>;
+ pinctrl-names = "default";
+};
+
+&gpio {
+ gpio-line-names =
+ "", "", "", "", "", // 0 - 4
+ "", "", "", "", "", // 5 - 9
+ "UserButton", "", "", "", "", // 10 - 14
+ "", "", "", "", "", // 15 - 19
+ "", "", "", "", "", // 20 - 24
+ "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29
+ "Output1", "", "", "", "", // 30 - 34
+ "", "ZigBeeBOOT", "", "", "", // 35 - 39
+ "1Wire", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44
+ "Input2", "Input1", "", "", "", // 45 - 49
+ "", "", "", "", "", // 50 - 54
+ "", "", "", "", "", // 55 - 59
+ "", "", "", "", "", // 60 - 64
+ "", "", "", "", "", // 65 - 69
+ "", "", "", "", "", // 70 - 74
+ "", "", "", "", "", // 75 - 79
+ "", "", "", "", "", // 80 - 84
+ "", ""; // 85-86
+};
+
+&cpu0 {
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ #cooling-cells = <2>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "radxa,zero", "amlogic,g12a";
+ model = "Radxa Zero";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ cvbs-connector {
+ status = "disabled";
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ hdmi_pw: regulator-hdmi_pw {
+ compatible = "regulator-fixed";
+ regulator-name = "HDMI_PW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&ao_5v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "RADXA-ZERO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_pw>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "disabled";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&dc_in>;
+ pwm-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&main_12v>;
+ pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&dc_in>;
+ pwm-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
- vin-supply = <&dc_in>;
+ pwm-supply = <&dc_in>;
pwms = <&pwm_ab 0 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
- vin-supply = <&vsys_3v3>;
+ pwm-supply = <&vsys_3v3>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
};
vcc_1v8: regulator-vcc_1v8 {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&main_12v>;
+ pwm-supply = <&main_12v>;
pwms = <&pwm_ab 0 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&main_12v>;
+ pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&main_12v>;
+ pwm-supply = <&main_12v>;
pwms = <&pwm_ab 0 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&main_12v>;
+ pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
+ * Copyright (c) 2020 JetHome
+ * Author: Aleksandr Kazantsev <ak@tvip.ru>
+ * Author: Alexey Shevelkin <ash@tvip.ru>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl.dtsi"
+
+/ {
+ compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
+ model = "JetHome JetHub J80";
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO; /* Console */
+ serial1 = &uart_A; /* Bluetooth */
+ serial2 = &uart_AO_B; /* Wireless module 1 */
+ serial3 = &uart_C; /* Wireless module 2 */
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+&efuse {
+ bt_mac: bt_mac@6 {
+ reg = <0x6 0x6>;
+ };
+
+ wifi_mac: wifi_mac@C {
+ reg = <0xc 0x6>;
+ };
+};
+
+&sn {
+ reg = <0x32 0x20>;
+};
+
+ð_mac {
+ reg = <0x0 0x6>;
+};
+
+&bid {
+ reg = <0x12 0x20>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* Console UART */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* S905W only has access to its internal PHY */
+ðmac {
+ status = "okay";
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&internal_phy {
+ status = "okay";
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&uart_C {
+ status = "okay";
+ pinctrl-0 = <&uart_c_pins>;
+ pinctrl-names = "default";
+};
+
+&uart_AO_B {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&i2c_B {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_b_pins>;
+
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "okay";
+ };
+};
/dts-v1/;
#include "meson-gxm.dtsi"
+#include <dt-bindings/sound/meson-aiu.h>
/ {
compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";
reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
};
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
leds {
compatible = "gpio-leds";
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "RBOX-PRO";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
};
ðmac {
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
- vin-supply = <&dc_in>;
+ pwm-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
- vin-supply = <&vsys_3v3>;
+ pwm-supply = <&vsys_3v3>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
- vin-supply = <&main_12v>;
+ pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
reg = <0>;
max-speed = <1000>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
- vin-supply = <&dc_in>;
+ pwm-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1500 0>;
pwm-dutycycle-range = <100 0>;
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
+ bcm2711-rpi-cm4-io.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+#include "arm/bcm2711-rpi-cm4-io.dts"
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
- clock-names = "periph";
+ clock-names = "refclk";
status = "okay";
};
- nand@1800 {
+ nand-controller@1800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
#reset-cells = <1>;
};
};
+ };
- reboot {
- compatible = "syscon-reboot";
- regmap = <&timer>;
- offset = <0x34>;
- mask = <1>;
- };
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&timer>;
+ offset = <0x34>;
+ mask = <1>;
};
};
dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos5433-tm2.dtb \
exynos5433-tm2e.dtb \
- exynos7-espresso.dtb
+ exynos7-espresso.dtb \
+ exynosautov9-sadk.dtb
status = "disabled";
};
- bus_g2d_400_opp_table: opp-table2 {
+ bus_g2d_400_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp-shared;
};
};
- bus_g2d_266_opp_table: opp-table3 {
+ bus_g2d_266_opp_table: opp-table-3 {
compatible = "operating-points-v2";
opp-267000000 {
};
};
- bus_gscl_opp_table: opp-table4 {
+ bus_gscl_opp_table: opp-table-4 {
compatible = "operating-points-v2";
opp-333000000 {
};
};
- bus_hevc_opp_table: opp-table5 {
+ bus_hevc_opp_table: opp-table-5 {
compatible = "operating-points-v2";
opp-shared;
};
};
- bus_noc2_opp_table: opp-table6 {
+ bus_noc2_opp_table: opp-table-6 {
compatible = "operating-points-v2";
opp-400000000 {
};
};
- cluster_a53_opp_table: opp-table0 {
+ cluster_a53_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
};
- cluster_a57_opp_table: opp-table1 {
+ cluster_a57_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
};
syscon_fsys: syscon@156f0000 {
- compatible = "syscon";
+ compatible = "samsung,exynos5433-sysreg", "syscon";
reg = <0x156f0000 0x1044>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ *
+ * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ */
+
+#include <dt-bindings/pinctrl/samsung.h>
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dp0_hpd: dp0-hpd-pins {
+ samsung,pins = "gpa1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ };
+
+ dp1_hpd: dp1-hpd-pins {
+ samsung,pins = "gpa1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ };
+
+ gpq0: gpq0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ speedy0_bus: speedy0-bus-pins {
+ samsung,pins = "gpq0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ speedy1_bus: speedy1-bus-pins {
+ samsung,pins = "gpa0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ };
+};
+
+&pinctrl_aud {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ aud_codec_mclk: aud-codec-mclk-pins {
+ samsung,pins = "gpb0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
+ samsung,pins = "gpb0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s0_bus: aud-i2s0-pins {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s0_idle: aud-i2s0-idle-pins {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s1_bus: aud-i2s1-pins {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s1_idle: aud-i2s1-idle-pins {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s2_bus: aud-i2s2-pins {
+ samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s2_idle: aud-i2s2-idle-pins {
+ samsung,pins = "gpb1-4", "gpb1-5", "gpb1-6", "gpb1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s3_bus: aud-i2s3-pins {
+ samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s3_idle: aud-i2s3-idle-pins {
+ samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s4_bus: aud-i2s4-pins {
+ samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s4_idle: aud-i2s4-idle-pins {
+ samsung,pins = "gpb2-4", "gpb2-5", "gpb2-6", "gpb2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s5_bus: aud-i2s5-pins {
+ samsung,pins = "gpb3-0", "gpb3-1", "gpb3-2", "gpb3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s5_idle: aaud-i2s5-idle-pins {
+ samsung,pins = "gpb3-0", "gpb3-1", "gpb3-2", "gpb3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s6_bus: aud-i2s6-pins {
+ samsung,pins = "gpb3-4", "gpb3-5", "gpb3-6", "gpb3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s6_idle: aaud-i2s6-idle-pins {
+ samsung,pins = "gpb3-4", "gpb3-5", "gpb3-6", "gpb3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+};
+
+&pinctrl_fsys0 {
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcie_clkreq0: pcie-clkreq0-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ pcie_perst0_out: pcie-perst0-out-pins {
+ samsung,pins = "gpf0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_perst0_in: pcie-perst0-in-pins {
+ samsung,pins = "gpf0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_clkreq1: pcie-clkreq1-pins {
+ samsung,pins = "gpf0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ pcie_perst1_out: pcie-perst1-out-pins {
+ samsung,pins = "gpf0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_perst1_in: pcie-perst1-in-pins {
+ samsung,pins = "gpf0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_clkreq2: pcie-clkreq2-pins {
+ samsung,pins = "gpf0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ pcie_perst2_out: pcie-perst2-out-pins {
+ samsung,pins = "gpf0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_perst2_in: pcie-perst2-in-pins {
+ samsung,pins = "gpf0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_clkreq3: pcie-clkreq3-pins {
+ samsung,pins = "gpf1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ pcie_perst3_out: pcie-perst3-out-pins {
+ samsung,pins = "gpf1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_perst3_in: pcie-perst3-in-pins {
+ samsung,pins = "gpf1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_clkreq4: pcie-clkreq4-pins {
+ samsung,pins = "gpf1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ pcie_perst4_out: pcie-perst4-out-pins {
+ samsung,pins = "gpf1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_perst4_in: pcie-perst4-in-pins {
+ samsung,pins = "gpf1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_clkreq5: pcie-clkreq5-pins {
+ samsung,pins = "gpf1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ pcie_perst5_out: pcie-perst5-out-pins {
+ samsung,pins = "gpf1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ pcie_perst5_in: pcie-perst5-in-pins {
+ samsung,pins = "gpf1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+};
+
+&pinctrl_fsys1 {
+ gpf8: gpf8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd2_clk: sd2-clk-pins {
+ samsung,pins = "gpf8-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <2>; /* 2x drive strength */
+ };
+
+ sd2_cmd: sd2-cmd-pins {
+ samsung,pins = "gpf8-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>; /* 2x drive strength */
+ };
+
+ sd2_bus1: sd2-bus-width1-pins {
+ samsung,pins = "gpf8-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>; /* 2x drive strength */
+ };
+
+ sd2_bus4: sd2-bus-width4-pins {
+ samsung,pins = "gpf8-3", "gpf8-4", "gpf8-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>; /* 2x drive strength */
+ };
+};
+
+&pinctrl_fsys2 {
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf5: gpf5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf6: gpf6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ufs_rst_n: ufs-rst-n-pins {
+ samsung,pins = "gpf2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out-pins {
+ samsung,pins = "gpf2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ ufs_rst_n_1: ufs-rst-n-1-pins {
+ samsung,pins = "gpf2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ ufs_refclk_out_1: ufs-refclk-out-1-pins {
+ samsung,pins = "gpf2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ };
+
+ eth0_mdc_mdio: eth0-mdc-mdio-pins {
+ samsung,pins = "gpf4-5", "gpf4-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ };
+
+ eth0_rgmii: eth0-rgmii-pins {
+ samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3", "gpf3-4",
+ "gpf3-5", "gpf3-6", "gpf3-7", "gpf4-0",
+ "gpf4-1", "gpf4-2", "gpf4-3", "gpf4-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ };
+
+ eth0_pps_out: eth0-pps-out-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ eth1_mdc_mdio: eth1-mdc-mdio-pins {
+ samsung,pins = "gpf6-5", "gpf6-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ };
+
+ eth1_rgmii: eth1-rgmii-pins {
+ samsung,pins = "gpf5-1", "gpf5-2", "gpf5-3", "gpf5-4",
+ "gpf5-5", "gpf5-6", "gpf5-7", "gpf6-0",
+ "gpf6-1", "gpf6-2", "gpf6-3", "gpf6-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ };
+
+ eth1_pps_out: eth1-pps-out-pins {
+ samsung,pins = "gpf5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
+
+&pinctrl_peric0 {
+ gpp0: gpp0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp1: gpp1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm_tout0: pwm-tout0-pins {
+ samsung,pins = "gpg0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ pwm_tout1: pwm-tout1-pins {
+ samsung,pins = "gpg0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ pwm_tout2: pwm-tout2-pins {
+ samsung,pins = "gpg0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ pwm_tout3: pwm-tout3-pins {
+ samsung,pins = "gpg0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI00 */
+ hsi2c0_bus: hsi2c0-bus-pins {
+ samsung,pins = "gpp0-0", "gpp0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI00_I2C */
+ hsi2c1_bus: hsi2c1-bus-pins {
+ samsung,pins = "gpp0-2", "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI01 */
+ hsi2c2_bus: hsi2c2-bus-pins {
+ samsung,pins = "gpp0-4", "gpp0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI01_I2C */
+ hsi2c3_bus: hsi2c3-bus-pins {
+ samsung,pins = "gpp0-6", "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI02 */
+ hsi2c4_bus: hsi2c4-bus-pins {
+ samsung,pins = "gpp1-0", "gpp1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI02_I2C */
+ hsi2c5_bus: hsi2c5-bus-pins {
+ samsung,pins = "gpp1-2", "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI03 */
+ hsi2c6_bus: hsi2c6-bus-pins {
+ samsung,pins = "gpp1-4", "gpp1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI03_I2C */
+ hsi2c7_bus: hsi2c7-bus-pins {
+ samsung,pins = "gpp1-6", "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI04 */
+ hsi2c8_bus: hsi2c8-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI04_I2C */
+ hsi2c9_bus: hsi2c9-bus-pins {
+ samsung,pins = "gpp2-2", "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI05 */
+ hsi2c10_bus: hsi2c10-bus-pins {
+ samsung,pins = "gpp2-4", "gpp2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI05_I2C */
+ hsi2c11_bus: hsi2c11-bus-pins {
+ samsung,pins = "gpp2-6", "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI USI_PERIC0_USI00_SPI */
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpp0-2", "gpp0-1", "gpp0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi0_cs: spi0-cs-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi0_cs_func: spi0-cs-func-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI01_SPI */
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpp0-6", "gpp0-5", "gpp0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi1_cs: spi1-cs-pins {
+ samsung,pins = "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi1_cs_func: spi1-cs-func-pins {
+ samsung,pins = "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI02_SPI */
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpp1-2", "gpp1-1", "gpp1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi2_cs: spi2-cs-pins {
+ samsung,pins = "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi2_cs_func: spi2-cs-func-pins {
+ samsung,pins = "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI03_SPI */
+ spi3_bus: spi3-bus-pins {
+ samsung,pins = "gpp1-6", "gpp1-5", "gpp1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi3_cs: spi3-cs-pins {
+ samsung,pins = "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi3_cs_func: spi3-cs-func-pins {
+ samsung,pins = "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI04_SPI */
+ spi4_bus: spi4-bus-pins {
+ samsung,pins = "gpp2-2", "gpp2-1", "gpp2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi4_cs: spi4-cs-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi4_cs_func: spi4-cs-func-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* PERIC0 USI05_SPI */
+ spi5_bus: spi5-bus-pins {
+ samsung,pins = "gpp2-6", "gpp2-5", "gpp2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi5_cs: spi5-cs-pins {
+ samsung,pins = "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi5_cs_func: spi5-cs-func-pins {
+ samsung,pins = "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC0_USI00_UART */
+ uart0_bus: uart0-bus-pins {
+ samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart0_bus_dual: uart0-bus-dual-pins {
+ samsung,pins = "gpp0-0", "gpp0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC0_USI01_UART */
+ uart1_bus: uart1-bus-pins {
+ samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart1_bus_dual: uart1-bus-dual-pins {
+ samsung,pins = "gpp0-4", "gpp0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC0_USI02_UART */
+ uart2_bus: uart2-bus-pins {
+ samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart2_bus_dual: uart2-bus-dual-pins {
+ samsung,pins = "gpp1-0", "gpp1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC0_USI03_UART */
+ uart3_bus: uart3-bus-pins {
+ samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart3_bus_dual: uart3-bus-dual-pins {
+ samsung,pins = "gpp1-4", "gpp1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC0_USI04_UART */
+ uart4_bus: uart4-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart4_bus_dual: uart4-bus-dual-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC0_USI05_UART */
+ uart5_bus: uart5-bus-pins {
+ samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart5_bus_dual: uart5-bus-dual-pins {
+ samsung,pins = "gpp2-4", "gpp2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
+
+&pinctrl_peric1 {
+ gpp3: gpp3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp4: gpp4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp5: gpp5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* PERIC1 USI06 */
+ hsi2c12_bus: hsi2c12-bus-pins {
+ samsung,pins = "gpp3-0", "gpp3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI06_I2C */
+ hsi2c13_bus: hsi2c13-bus-pins {
+ samsung,pins = "gpp3-2", "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI07 */
+ hsi2c14_bus: hsi2c14-bus-pins {
+ samsung,pins = "gpp3-4", "gpp3-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI07_I2C */
+ hsi2c15_bus: hsi2c15-bus-pins {
+ samsung,pins = "gpp3-6", "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI08 */
+ hsi2c16_bus: hsi2c16-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI08_I2C */
+ hsi2c17_bus: hsi2c17-bus-pins {
+ samsung,pins = "gpp4-2", "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI09 */
+ hsi2c18_bus: hsi2c18-bus-pins {
+ samsung,pins = "gpp4-4", "gpp4-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI09_I2C */
+ hsi2c19_bus: hsi2c19-bus-pins {
+ samsung,pins = "gpp4-6", "gpp4-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI10 */
+ hsi2c20_bus: hsi2c20-bus-pins {
+ samsung,pins = "gpp5-0", "gpp5-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI10_I2C */
+ hsi2c21_bus: hsi2c21-bus-pins {
+ samsung,pins = "gpp5-2", "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI11 */
+ hsi2c22_bus: hsi2c22-bus-pins {
+ samsung,pins = "gpp5-4", "gpp5-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI11_I2C */
+ hsi2c23_bus: hsi2c23-bus-pins {
+ samsung,pins = "gpp5-6", "gpp5-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI06_SPI */
+ spi6_bus: spi6-bus-pins {
+ samsung,pins = "gpp3-2", "gpp3-1", "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi6_cs: spi6-cs-pins {
+ samsung,pins = "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi6_cs_func: spi6-cs-func-pins {
+ samsung,pins = "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI07_SPI */
+ spi7_bus: spi7-bus-pins {
+ samsung,pins = "gpp3-6", "gpp3-5", "gpp3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi7_cs: spi7-cs-pins {
+ samsung,pins = "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi7_cs_func: spi7-cs-func-pins {
+ samsung,pins = "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI08_SPI */
+ spi8_bus: spi8-bus-pins {
+ samsung,pins = "gpp4-2", "gpp4-1", "gpp4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi8_cs: spi8-cs-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi8_cs_func: spi8-cs-func-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI09_SPI */
+ spi9_bus: spi9-bus-pins {
+ samsung,pins = "gpp4-6", "gpp4-5", "gpp4-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi9_cs: spi9-cs-pins {
+ samsung,pins = "gpp4-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi9_cs_func: spi9-cs-func-pins {
+ samsung,pins = "gpp4-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI10_SPI */
+ spi10_bus: spi10-pins {
+ samsung,pins = "gpp5-2", "gpp5-1", "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi10_cs: spi10-cs-pins {
+ samsung,pins = "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi10_cs_func: spi10-cs-func-pins {
+ samsung,pins = "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* PERIC1 USI11_SPI */
+ spi11_bus: spi11-pins {
+ samsung,pins = "gpp3-6", "gpp3-5", "gpp3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi11_cs: spi11-cs-pins {
+ samsung,pins = "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ spi11_cs_func: spi11-cs-func-pins {
+ samsung,pins = "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI_PERIC1_USI06_UART */
+ uart6_bus: uart6-bus-pins {
+ samsung,pins = "gpp3-3", "gpp3-2", "gpp3-1", "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart6_bus_dual: uart6-bus-dual-pins {
+ samsung,pins = "gpp3-0", "gpp3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC1_USI07_UART */
+ uart7_bus: uart7-bus-pins {
+ samsung,pins = "gpp3-7", "gpp3-6", "gpp3-5", "gpp3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart7_bus_dual: uart7-bus-dual-pins {
+ samsung,pins = "gpp3-4", "gpp3-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC1_USI08_UART */
+ uart8_bus: uart8-bus-pins {
+ samsung,pins = "gpp4-3", "gpp4-2", "gpp4-1", "gpp4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart8_bus_dual: uart8-bus-dual-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC1_USI09_UART */
+ uart9_bus: uart9-bus-pins {
+ samsung,pins = "gpp4-7", "gpp4-6", "gpp4-5", "gpp4-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart9_bus_dual: uart9-bus-dual-pins {
+ samsung,pins = "gpp4-4", "gpp4-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC1_USI10_UART */
+ uart10_bus: uart10-bus-pins {
+ samsung,pins = "gpp5-3", "gpp5-2", "gpp5-1", "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart10_bus_dual: uart10-bus-dual-pins {
+ samsung,pins = "gpp5-0", "gpp5-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_PERIC1_USI11_UART */
+ uart11_bus: uart11-bus-pins {
+ samsung,pins = "gpp5-7", "gpp5-6", "gpp5-5", "gpp5-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart11_bus_dual: uart11-bus-dual-pins {
+ samsung,pins = "gpp5-4", "gpp5-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung ExynosAutov9 SADK board device tree source
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include "exynosautov9.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Samsung ExynosAuto v9 SADK board";
+ compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &serial_0;
+ };
+
+ chosen {
+ stdout-path = &serial_0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x77000000>,
+ <0x8 0x80000000 0x1 0x7ba00000>,
+ <0xa 0x00000000 0x2 0x00000000>;
+ };
+
+ ufs_0_fixed_vcc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ufs-vcc";
+ gpio = <&gpq0 1 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
+};
+
+&serial_0 {
+ status = "okay";
+};
+
+&ufs_0_phy {
+ status = "okay";
+};
+
+&ufs_0 {
+ status = "okay";
+ vcc-supply = <&ufs_0_fixed_vcc_reg>;
+ vcc-fixed-regulator;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's ExynosAuto v9 SoC device tree source
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynosautov9";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_aud;
+ pinctrl2 = &pinctrl_fsys0;
+ pinctrl3 = &pinctrl_fsys1;
+ pinctrl4 = &pinctrl_fsys2;
+ pinctrl5 = &pinctrl_peric0;
+ pinctrl6 = &pinctrl_peric1;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x10000>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x10100>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@10200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x10200>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@10300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x10300>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ fixed-rate-clocks {
+ xtcxo: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "oscclk";
+ };
+
+ /*
+ * Keep the stub clock for serial driver, until proper clock
+ * driver is implemented.
+ */
+ uart_clock: uart-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133250000>;
+ clock-output-names = "uart";
+ };
+
+ /*
+ * Keep the stub clock for ufs driver, until proper clock
+ * driver is implemented.
+ */
+ ufs_core_clock: ufs-core-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <166562500>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ gic: interrupt-controller@10101000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x10101000 0x1000>,
+ <0x10102000 0x2000>,
+ <0x10104000 0x2000>,
+ <0x10106000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl_alive: pinctrl@10450000 {
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x10450000 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ pinctrl_aud: pinctrl@19c60000{
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x19c60000 0x1000>;
+ };
+
+ pinctrl_fsys0: pinctrl@17740000 {
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x17740000 0x1000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_fsys1: pinctrl@17060000 {
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x17060000 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_fsys2: pinctrl@17c30000 {
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x17c30000 0x1000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_peric0: pinctrl@10230000 {
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x10230000 0x1000>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_peric1: pinctrl@10830000 {
+ compatible = "samsung,exynosautov9-pinctrl";
+ reg = <0x10830000 0x1000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu_system_controller: system-controller@10460000 {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x10460000 0x10000>;
+ };
+
+ syscon_fsys2: syscon@17c20000 {
+ compatible = "samsung,exynosautov9-sysreg", "syscon";
+ reg = <0x17c20000 0x1000>;
+ };
+
+ /* USI: UART */
+ serial_0: uart@10300000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x10300000 0x100>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus_dual>;
+ clocks = <&uart_clock>, <&uart_clock>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ ufs_0_phy: ufs0-phy@17e04000 {
+ compatible = "samsung,exynosautov9-ufs-phy";
+ reg = <0x17e04000 0xc00>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&xtcxo>;
+ clock-names = "ref_clk";
+ status = "disabled";
+ };
+
+ ufs_0: ufs0@17e00000 {
+ compatible ="samsung,exynosautov9-ufs";
+
+ reg = <0x17e00000 0x100>, /* 0: HCI standard */
+ <0x17e01100 0x410>, /* 1: Vendor-specific */
+ <0x17e80000 0x8000>, /* 2: UNIPRO */
+ <0x17dc0000 0x2200>; /* 3: UFS protector */
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ufs_core_clock>,
+ <&ufs_core_clock>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_0_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&syscon_fsys2>;
+ samsung,ufs-shareability-reg-offset = <0x710>;
+ status = "disabled";
+ };
+ };
+};
+
+#include "exynosautov9-pinctrl.dtsi"
};
};
- cluster0_opp: opp_table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
};
- cluster1_opp: opp_table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
};
watchdog0: watchdog@e8a06000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xe8a06000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>,
};
watchdog1: watchdog@e8a07000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xe8a07000 0x0 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>,
#include "hi3670.dtsi"
#include "hikey970-pinctrl.dtsi"
+#include "hikey970-pmic.dtsi"
/ {
model = "HiKey970";
reg = <0x0 0x0 0x0 0x0>;
};
- sd_1v8: regulator-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- sd_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
wlan_en: wlan-en-1-8v {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
pinctrl-0 = <&sd_pmx_func
&sd_clk_cfg_func
&sd_cfg_func>;
- vmmc-supply = <&sd_3v3>;
- vqmmc-supply = <&sd_1v8>;
+ vmmc-supply = <&ldo16>;
+ vqmmc-supply = <&ldo9>;
status = "okay";
};
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
- <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0
0 0>;
};
};
- cpu_opp_table: cpu_opp_table {
+ cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
watchdog0: watchdog@f8005000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xf8005000 0x0 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hi6421v600 SPMI PMIC used at the HiKey970 Development Board
+ *
+ * Copyright (C) 2020, Huawei Tech. Co., Ltd.
+ */
+
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ spmi: spmi@fff24000 {
+ compatible = "hisilicon,kirin970-spmi-controller";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ status = "okay";
+ reg = <0x0 0xfff24000 0x0 0x1000>;
+ hisilicon,spmi-channel = <2>;
+
+ pmic: pmic@0 {
+ compatible = "hisilicon,hi6421-spmi";
+ reg = <0 SPMI_USID>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ gpios = <&gpio28 0 0>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ldo3: ldo3 { /* HDMI */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ };
+
+ ldo4: ldo4 { /* 40 PIN */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1725000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ };
+
+ ldo9: ldo9 { /* SDCARD I/O */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ ldo15: ldo15 { /* UFS */
+ regulator-name = "ldo15";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ ldo16: ldo16 { /* SD */
+ regulator-name = "ldo16";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ };
+
+ ldo17: ldo17 { /* USB HUB */
+ regulator-name = "ldo17";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo33: ldo33 { /* PEX8606 */
+ regulator-name = "ldo33";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo34: ldo34 { /* GPS AUX IN VDD */
+ regulator-name = "ldo34";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+ };
+};
};
};
- pcie: pcie@11700000 {
+ pcie1: pcie@112ff000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
- reg = <0 0x11700000 0 0x1000>,
- <0 0x112ff000 0 0x1000>;
- reg-names = "port0", "port1";
+ reg = <0 0x112ff000 0 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
- <&pericfg CLK_PERI_PCIE0>,
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
<&pericfg CLK_PERI_PCIE1>;
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
- phy-names = "pcie-phy0", "pcie-phy1";
+ clock-names = "sys_ck1", "ahb_ck1";
+ phys = <&u3port1 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy1";
bus-range = <0x00 0xff>;
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
+ status = "disabled";
- pcie0: pcie@0,0 {
- device_type = "pci";
- status = "disabled";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
- <0 0 0 2 &pcie_intc0 1>,
- <0 0 0 3 &pcie_intc0 2>,
- <0 0 0 4 &pcie_intc0 3>;
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
+ };
- pcie1: pcie@1,0 {
- device_type = "pci";
- status = "disabled";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
+ pcie0: pcie@11700000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+ reg = <0 0x11700000 0 0x1000>;
+ reg-names = "port0";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+ <&pericfg CLK_PERI_PCIE0>;
+ clock-names = "sys_ck0", "ahb_ck0";
+ phys = <&u3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
};
mt6358codec: mt6358codec {
compatible = "mediatek,mt6358-sound";
+ mediatek,dmic-mode = <0>; /* two-wires */
};
mt6358regulator: mt6358regulator {
};
};
-&pcie {
+&pcie0 {
pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+ pinctrl-0 = <&pcie0_pins>;
status = "okay";
+};
- pcie@0,0 {
- status = "okay";
- };
-
- pcie@1,0 {
- status = "okay";
- };
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
};
&pio {
};
};
-&pcie {
+&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
-
- pcie@0,0 {
- status = "okay";
- };
};
&pio {
#reset-cells = <1>;
};
- pcie: pcie@1a140000 {
+ pciecfg: pciecfg@1a140000 {
+ compatible = "mediatek,generic-pciecfg", "syscon";
+ reg = <0 0x1a140000 0 0x1000>;
+ };
+
+ pcie0: pcie@1a143000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
- reg = <0 0x1a140000 0 0x1000>,
- <0 0x1a143000 0 0x1000>,
- <0 0x1a145000 0 0x1000>;
- reg-names = "subsys", "port0", "port1";
+ reg = <0 0x1a143000 0 0x1000>;
+ reg-names = "port0";
+ linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "pcie_irq";
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
- <&pciesys CLK_PCIE_P1_MAC_EN>,
- <&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AUX_EN>,
- <&pciesys CLK_PCIE_P1_AUX_EN>,
<&pciesys CLK_PCIE_P0_AXI_EN>,
- <&pciesys CLK_PCIE_P1_AXI_EN>,
<&pciesys CLK_PCIE_P0_OBFF_EN>,
- <&pciesys CLK_PCIE_P1_OBFF_EN>,
- <&pciesys CLK_PCIE_P0_PIPE_EN>,
- <&pciesys CLK_PCIE_P1_PIPE_EN>;
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+ "axi_ck0", "obff_ck0", "pipe_ck0";
+
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
status = "disabled";
- pcie0: pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- ranges;
- status = "disabled";
-
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
- <0 0 0 2 &pcie_intc0 1>,
- <0 0 0 3 &pcie_intc0 2>,
- <0 0 0 4 &pcie_intc0 3>;
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
+ };
- pcie1: pcie@1,0 {
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
+ pcie1: pcie@1a145000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0 0x1a145000 0 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "pcie_irq";
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
+ /* designer has connect RC1 with p0_ahb clock */
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
+ "axi_ck1", "obff_ck1", "pipe_ck1";
+
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- ranges;
- status = "disabled";
-
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
};
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) da7219-max98357a sound card.
+ *
+ * Copyright 2019 Google LLC.
+ */
+
+#include "mt8183-kukui-audio-da7219.dtsi"
+#include "mt8183-kukui-audio-max98357a.dtsi"
+
+&sound {
+ compatible = "mediatek,mt8183_da7219_max98357";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) da7219-rt1015p sound card.
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+#include "mt8183-kukui-audio-da7219.dtsi"
+#include "mt8183-kukui-audio-rt1015p.dtsi"
+
+&sound {
+ compatible = "mediatek,mt8183_da7219_rt1015p";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) audio fragment for da7219.
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+&i2c5 {
+ da7219: da7219@1a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&da7219_pins>;
+ compatible = "dlg,da7219";
+ reg = <0x1a>;
+ interrupt-parent = <&pio>;
+ interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>;
+
+ dlg,micbias-lvl = <2600>;
+ dlg,mic-amp-in-sel = "diff";
+ VDD-supply = <&pp1800_alw>;
+ VDDMIC-supply = <&pp3300_alw>;
+ VDDIO-supply = <&pp1800_alw>;
+
+ status = "okay";
+
+ da7219_aad {
+ dlg,adc-1bit-rpt = <1>;
+ dlg,btn-avg = <4>;
+ dlg,btn-cfg = <50>;
+ dlg,mic-det-thr = <500>;
+ dlg,jack-ins-deb = <20>;
+ dlg,jack-det-rate = "32ms_64ms";
+ dlg,jack-rem-deb = <1>;
+
+ dlg,a-d-btn-thr = <0xa>;
+ dlg,d-b-btn-thr = <0x16>;
+ dlg,b-c-btn-thr = <0x21>;
+ dlg,c-mic-btn-thr = <0x3E>;
+ };
+ };
+};
+
+&pio {
+ da7219_pins: da7219_pins {
+ pins1 {
+ pinmux = <PINMUX_GPIO165__FUNC_GPIO165>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+};
+
+&sound {
+ mediatek,headset-codec = <&da7219>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) audio fragment for max98357a.
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+/ {
+ max98357a: max98357a {
+ compatible = "maxim,max98357a";
+ sdmode-gpios = <&pio 175 0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) audio fragment for rt1015p.
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+/ {
+ rt1015p: rt1015p {
+ compatible = "realtek,rt1015p";
+ sdb-gpios = <&pio 175 0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) ts3a227e-max98357a sound card.
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+#include "mt8183-kukui-audio-max98357a.dtsi"
+#include "mt8183-kukui-audio-ts3a227e.dtsi"
+
+&sound {
+ compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card.
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+#include "mt8183-kukui-audio-ts3a227e.dtsi"
+#include "mt8183-kukui-audio-rt1015p.dtsi"
+
+&sound {
+ compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Google Kukui (and derivatives) audio fragment for ts3a227e.
+ *
+ * Copyright 2019 Google LLC.
+ */
+
+&i2c5 {
+ ts3a227e: ts3a227e@3b {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts3a227e_pins>;
+ compatible = "ti,ts3a227e";
+ reg = <0x3b>;
+ interrupt-parent = <&pio>;
+ interrupts = <157 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+};
+
+&pio {
+ ts3a227e_pins: ts3a227e_pins {
+ pins1 {
+ pinmux = <PINMUX_GPIO157__FUNC_GPIO157>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+};
+
+&sound {
+ mediatek,headset-codec = <&ts3a227e>;
+};
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google burnet board";
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
+#include "mt8183-kukui-audio-da7219-max98357a.dtsi"
/ {
model = "Google damu board";
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google juniper sku16 board";
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google kappa board";
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google kenzo sku17 board";
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
+#include "mt8183-kukui-audio-da7219-max98357a.dtsi"
/ {
model = "Google willow board sku0";
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google willow board sku1";
/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "MediaTek kakadu board";
/dts-v1/;
#include "mt8183-kukui.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
ppvarn_lcd: ppvarn-lcd {
*/
#include "mt8183-kukui.dtsi"
+#include "mt8183-kukui-audio-max98357a.dtsi"
/ {
ppvarn_lcd: ppvarn-lcd {
&qca_wifi {
qcom,ath10k-calibration-variant = "LE_Krane";
};
+
+&sound {
+ compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
+};
};
};
- max98357a: codec0 {
- compatible = "maxim,max98357a";
- sdmode-gpios = <&pio 175 0>;
+ sound: mt8183-sound {
+ mediatek,platform = <&afe>;
+ pinctrl-names = "default",
+ "aud_tdm_out_on",
+ "aud_tdm_out_off";
+ pinctrl-0 = <&aud_pins_default>;
+ pinctrl-1 = <&aud_pins_tdm_out_on>;
+ pinctrl-2 = <&aud_pins_tdm_out_off>;
+ status = "okay";
};
- btsco: codec1 {
+ btsco: bt-sco {
compatible = "linux,bt-sco";
};
};
};
+&afe {
+ i2s3-share = "I2S2";
+ i2s0-share = "I2S5";
+};
+
&auxadc {
status = "okay";
};
};
&pio {
+ aud_pins_default: audiopins {
+ pins_bus {
+ pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
+ <PINMUX_GPIO98__FUNC_I2S2_BCK>,
+ <PINMUX_GPIO101__FUNC_I2S2_LRCK>,
+ <PINMUX_GPIO102__FUNC_I2S2_DI>,
+ <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
+ <PINMUX_GPIO89__FUNC_I2S5_BCK>,
+ <PINMUX_GPIO90__FUNC_I2S5_LRCK>,
+ <PINMUX_GPIO91__FUNC_I2S5_DO>,
+ <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
+ <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
+ <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
+ <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
+ <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
+ <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
+ <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
+ <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
+ <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
+ };
+ };
+
+ aud_pins_tdm_out_on: audiotdmouton {
+ pins_bus {
+ pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
+ <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
+ <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
+ <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
+ <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
+ <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+ };
+
+ aud_pins_tdm_out_off: audiotdmoutoff {
+ pins_bus {
+ pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
+ <PINMUX_GPIO170__FUNC_GPIO170>,
+ <PINMUX_GPIO171__FUNC_GPIO171>,
+ <PINMUX_GPIO172__FUNC_GPIO172>,
+ <PINMUX_GPIO173__FUNC_GPIO173>,
+ <PINMUX_GPIO10__FUNC_GPIO10>;
+ input-enable;
+ bias-pull-down;
+ drive-strength = <MTK_DRIVE_2mA>;
+ };
+ };
+
bt_pins: bt-pins {
pins_bt_en {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
-#include <dt-bindings/reset-controller/mt8183-resets.h>
+#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
};
};
- audiosys: syscon@11220000 {
+ audiosys: audio-controller@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
#clock-cells = <1>;
+ afe: mt8183-afe-pcm {
+ compatible = "mediatek,mt8183-audio";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ power-domains =
+ <&spm MT8183_POWER_DOMAIN_AUDIO>;
+ clocks = <&audiosys CLK_AUDIO_AFE>,
+ <&audiosys CLK_AUDIO_DAC>,
+ <&audiosys CLK_AUDIO_DAC_PREDIS>,
+ <&audiosys CLK_AUDIO_ADC>,
+ <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
+ <&audiosys CLK_AUDIO_22M>,
+ <&audiosys CLK_AUDIO_24M>,
+ <&audiosys CLK_AUDIO_APLL_TUNER>,
+ <&audiosys CLK_AUDIO_APLL2_TUNER>,
+ <&audiosys CLK_AUDIO_I2S1>,
+ <&audiosys CLK_AUDIO_I2S2>,
+ <&audiosys CLK_AUDIO_I2S3>,
+ <&audiosys CLK_AUDIO_I2S4>,
+ <&audiosys CLK_AUDIO_TDM>,
+ <&audiosys CLK_AUDIO_TML>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_AUDIO>,
+ <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&topckgen CLK_TOP_SYSPLL_D2_D4>,
+ <&topckgen CLK_TOP_MUX_AUD_1>,
+ <&topckgen CLK_TOP_APLL1_CK>,
+ <&topckgen CLK_TOP_MUX_AUD_2>,
+ <&topckgen CLK_TOP_APLL2_CK>,
+ <&topckgen CLK_TOP_MUX_AUD_ENG1>,
+ <&topckgen CLK_TOP_APLL1_D8>,
+ <&topckgen CLK_TOP_MUX_AUD_ENG2>,
+ <&topckgen CLK_TOP_APLL2_D8>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S0>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S1>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S2>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S3>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S4>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S5>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adc_adda6_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_i2s1_bclk_sw",
+ "aud_i2s2_bclk_sw",
+ "aud_i2s3_bclk_sw",
+ "aud_i2s4_bclk_sw",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_syspll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ /*"top_apll12_div5",*/
+ "top_clk26m_clk";
+ };
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- mediatek,syscon-dsi = <&mmsys 0x140>;
clocks = <&mmsys CLK_MM_DSI0_MM>,
<&mmsys CLK_MM_DSI0_IF>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
};
*/
/dts-v1/;
+#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
};
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8192-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8192-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
#interrupt-cells = <2>;
};
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8192-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
clock-names = "clk13m";
};
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8192-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
status = "disabled";
};
+ imp_iic_wrap_c: clock-controller@11007000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_c";
+ reg = <0 0x11007000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
status = "disable";
};
+ audsys: clock-controller@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
status = "disabled";
};
+ imp_iic_wrap_e: clock-controller@11cb1000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_e";
+ reg = <0 0x11cb1000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c7: i2c7@11d00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
status = "disabled";
};
+ imp_iic_wrap_s: clock-controller@11d03000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c1: i2c1@11d20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
status = "disabled";
};
+ imp_iic_wrap_ws: clock-controller@11d23000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_ws";
+ reg = <0 0x11d23000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c5: i2c5@11e00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
status = "disabled";
};
+ imp_iic_wrap_w: clock-controller@11e01000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_w";
+ reg = <0 0x11e01000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c0: i2c0@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
#size-cells = <0>;
status = "disabled";
};
+
+ imp_iic_wrap_n: clock-controller@11f02000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_n";
+ reg = <0 0x11f02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc_top: clock-controller@11f10000 {
+ compatible = "mediatek,mt8192-msdc_top";
+ reg = <0 0x11f10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc: clock-controller@11f60000 {
+ compatible = "mediatek,mt8192-msdc";
+ reg = <0 0x11f60000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8192-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8192-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15020000 {
+ compatible = "mediatek,mt8192-imgsys";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys2: clock-controller@15820000 {
+ compatible = "mediatek,mt8192-imgsys2";
+ reg = <0 0x15820000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1600f000 {
+ compatible = "mediatek,mt8192-vdecsys_soc";
+ reg = <0 0x1600f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1602f000 {
+ compatible = "mediatek,mt8192-vdecsys";
+ reg = <0 0x1602f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@17000000 {
+ compatible = "mediatek,mt8192-vencsys";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8192-camsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1a04f000 {
+ compatible = "mediatek,mt8192-camsys_rawa";
+ reg = <0 0x1a04f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1a06f000 {
+ compatible = "mediatek,mt8192-camsys_rawb";
+ reg = <0 0x1a06f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawc: clock-controller@1a08f000 {
+ compatible = "mediatek,mt8192-camsys_rawc";
+ reg = <0 0x1a08f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@1b000000 {
+ compatible = "mediatek,mt8192-ipesys";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mdpsys: clock-controller@1f000000 {
+ compatible = "mediatek,mt8192-mdpsys";
+ reg = <0 0x1f000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
-
- backlight-boot-off;
};
clk32k_in: clock@0 {
};
usb@7d000000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USBD>,
<&tegra_car TEGRA124_CLK_PLL_U>,
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};
usb@7d004000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>,
<&tegra_car TEGRA124_CLK_PLL_U>,
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};
usb@7d008000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d008000 0x0 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d008000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB3>,
<&tegra_car TEGRA124_CLK_PLL_U>,
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};
remote-endpoint = <&dspk2_cif_ep>;
};
};
+
+ xbar_sfc1_in_port: port@20 {
+ reg = <0x20>;
+
+ xbar_sfc1_in_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_in_ep>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ xbar_sfc1_out_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@22 {
+ reg = <0x22>;
+
+ xbar_sfc2_in_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_in_ep>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ xbar_sfc2_out_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@24 {
+ reg = <0x24>;
+
+ xbar_sfc3_in_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_in_ep>;
+ };
+ };
+
+ port@25 {
+ reg = <0x25>;
+
+ xbar_sfc3_out_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@26 {
+ reg = <0x26>;
+
+ xbar_sfc4_in_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_in_ep>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_sfc4_out_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_mvc1_in_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_in_ep>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_mvc1_out_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@2a {
+ reg = <0x2a>;
+
+ xbar_mvc2_in_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_in_ep>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_mvc2_out_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_out_ep>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@2c {
+ reg = <0x2c>;
+
+ xbar_amx1_in1_ep: endpoint {
+ remote-endpoint = <&amx1_in1_ep>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_amx1_in2_ep: endpoint {
+ remote-endpoint = <&amx1_in2_ep>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@2e {
+ reg = <0x2e>;
+
+ xbar_amx1_in3_ep: endpoint {
+ remote-endpoint = <&amx1_in3_ep>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@2f {
+ reg = <0x2f>;
+
+ xbar_amx1_in4_ep: endpoint {
+ remote-endpoint = <&amx1_in4_ep>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_amx1_out_ep: endpoint {
+ remote-endpoint = <&amx1_out_ep>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@31 {
+ reg = <0x31>;
+
+ xbar_amx2_in1_ep: endpoint {
+ remote-endpoint = <&amx2_in1_ep>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@32 {
+ reg = <0x32>;
+
+ xbar_amx2_in2_ep: endpoint {
+ remote-endpoint = <&amx2_in2_ep>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@33 {
+ reg = <0x33>;
+
+ xbar_amx2_in3_ep: endpoint {
+ remote-endpoint = <&amx2_in3_ep>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@34 {
+ reg = <0x34>;
+
+ xbar_amx2_in4_ep: endpoint {
+ remote-endpoint = <&amx2_in4_ep>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ xbar_amx2_out_ep: endpoint {
+ remote-endpoint = <&amx2_out_ep>;
+ };
+ };
+
+ xbar_amx3_in1_port: port@36 {
+ reg = <0x36>;
+
+ xbar_amx3_in1_ep: endpoint {
+ remote-endpoint = <&amx3_in1_ep>;
+ };
+ };
+
+ xbar_amx3_in2_port: port@37 {
+ reg = <0x37>;
+
+ xbar_amx3_in2_ep: endpoint {
+ remote-endpoint = <&amx3_in2_ep>;
+ };
+ };
+
+ xbar_amx3_in3_port: port@38 {
+ reg = <0x38>;
+
+ xbar_amx3_in3_ep: endpoint {
+ remote-endpoint = <&amx3_in3_ep>;
+ };
+ };
+
+ xbar_amx3_in4_port: port@39 {
+ reg = <0x39>;
+
+ xbar_amx3_in4_ep: endpoint {
+ remote-endpoint = <&amx3_in4_ep>;
+ };
+ };
+
+ port@3a {
+ reg = <0x3a>;
+
+ xbar_amx3_out_ep: endpoint {
+ remote-endpoint = <&amx3_out_ep>;
+ };
+ };
+
+ xbar_amx4_in1_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_amx4_in1_ep: endpoint {
+ remote-endpoint = <&amx4_in1_ep>;
+ };
+ };
+
+ xbar_amx4_in2_port: port@3c {
+ reg = <0x3c>;
+
+ xbar_amx4_in2_ep: endpoint {
+ remote-endpoint = <&amx4_in2_ep>;
+ };
+ };
+
+ xbar_amx4_in3_port: port@3d {
+ reg = <0x3d>;
+
+ xbar_amx4_in3_ep: endpoint {
+ remote-endpoint = <&amx4_in3_ep>;
+ };
+ };
+
+ xbar_amx4_in4_port: port@3e {
+ reg = <0x3e>;
+
+ xbar_amx4_in4_ep: endpoint {
+ remote-endpoint = <&amx4_in4_ep>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_amx4_out_ep: endpoint {
+ remote-endpoint = <&amx4_out_ep>;
+ };
+ };
+
+ xbar_adx1_in_port: port@40 {
+ reg = <0x40>;
+
+ xbar_adx1_in_ep: endpoint {
+ remote-endpoint = <&adx1_in_ep>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ xbar_adx1_out1_ep: endpoint {
+ remote-endpoint = <&adx1_out1_ep>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_adx1_out2_ep: endpoint {
+ remote-endpoint = <&adx1_out2_ep>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ xbar_adx1_out3_ep: endpoint {
+ remote-endpoint = <&adx1_out3_ep>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_adx1_out4_ep: endpoint {
+ remote-endpoint = <&adx1_out4_ep>;
+ };
+ };
+
+ xbar_adx2_in_port: port@45 {
+ reg = <0x45>;
+
+ xbar_adx2_in_ep: endpoint {
+ remote-endpoint = <&adx2_in_ep>;
+ };
+ };
+
+ port@46 {
+ reg = <0x46>;
+
+ xbar_adx2_out1_ep: endpoint {
+ remote-endpoint = <&adx2_out1_ep>;
+ };
+ };
+
+ port@47 {
+ reg = <0x47>;
+
+ xbar_adx2_out2_ep: endpoint {
+ remote-endpoint = <&adx2_out2_ep>;
+ };
+ };
+
+ port@48 {
+ reg = <0x48>;
+
+ xbar_adx2_out3_ep: endpoint {
+ remote-endpoint = <&adx2_out3_ep>;
+ };
+ };
+
+ port@49 {
+ reg = <0x49>;
+
+ xbar_adx2_out4_ep: endpoint {
+ remote-endpoint = <&adx2_out4_ep>;
+ };
+ };
+
+ xbar_adx3_in_port: port@4a {
+ reg = <0x4a>;
+
+ xbar_adx3_in_ep: endpoint {
+ remote-endpoint = <&adx3_in_ep>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ xbar_adx3_out1_ep: endpoint {
+ remote-endpoint = <&adx3_out1_ep>;
+ };
+ };
+
+ port@4c {
+ reg = <0x4c>;
+
+ xbar_adx3_out2_ep: endpoint {
+ remote-endpoint = <&adx3_out2_ep>;
+ };
+ };
+
+ port@4d {
+ reg = <0x4d>;
+
+ xbar_adx3_out3_ep: endpoint {
+ remote-endpoint = <&adx3_out3_ep>;
+ };
+ };
+
+ port@4e {
+ reg = <0x4e>;
+
+ xbar_adx3_out4_ep: endpoint {
+ remote-endpoint = <&adx3_out4_ep>;
+ };
+ };
+
+ xbar_adx4_in_port: port@4f {
+ reg = <0x4f>;
+
+ xbar_adx4_in_ep: endpoint {
+ remote-endpoint = <&adx4_in_ep>;
+ };
+ };
+
+ port@50 {
+ reg = <0x50>;
+
+ xbar_adx4_out1_ep: endpoint {
+ remote-endpoint = <&adx4_out1_ep>;
+ };
+ };
+
+ port@51 {
+ reg = <0x51>;
+
+ xbar_adx4_out2_ep: endpoint {
+ remote-endpoint = <&adx4_out2_ep>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ xbar_adx4_out3_ep: endpoint {
+ remote-endpoint = <&adx4_out3_ep>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ xbar_adx4_out4_ep: endpoint {
+ remote-endpoint = <&adx4_out4_ep>;
+ };
+ };
+
+ xbar_mixer_in1_port: port@54 {
+ reg = <0x54>;
+
+ xbar_mixer_in1_ep: endpoint {
+ remote-endpoint = <&mixer_in1_ep>;
+ };
+ };
+
+ xbar_mixer_in2_port: port@55 {
+ reg = <0x55>;
+
+ xbar_mixer_in2_ep: endpoint {
+ remote-endpoint = <&mixer_in2_ep>;
+ };
+ };
+
+ xbar_mixer_in3_port: port@56 {
+ reg = <0x56>;
+
+ xbar_mixer_in3_ep: endpoint {
+ remote-endpoint = <&mixer_in3_ep>;
+ };
+ };
+
+ xbar_mixer_in4_port: port@57 {
+ reg = <0x57>;
+
+ xbar_mixer_in4_ep: endpoint {
+ remote-endpoint = <&mixer_in4_ep>;
+ };
+ };
+
+ xbar_mixer_in5_port: port@58 {
+ reg = <0x58>;
+
+ xbar_mixer_in5_ep: endpoint {
+ remote-endpoint = <&mixer_in5_ep>;
+ };
+ };
+
+ xbar_mixer_in6_port: port@59 {
+ reg = <0x59>;
+
+ xbar_mixer_in6_ep: endpoint {
+ remote-endpoint = <&mixer_in6_ep>;
+ };
+ };
+
+ xbar_mixer_in7_port: port@5a {
+ reg = <0x5a>;
+
+ xbar_mixer_in7_ep: endpoint {
+ remote-endpoint = <&mixer_in7_ep>;
+ };
+ };
+
+ xbar_mixer_in8_port: port@5b {
+ reg = <0x5b>;
+
+ xbar_mixer_in8_ep: endpoint {
+ remote-endpoint = <&mixer_in8_ep>;
+ };
+ };
+
+ xbar_mixer_in9_port: port@5c {
+ reg = <0x5c>;
+
+ xbar_mixer_in9_ep: endpoint {
+ remote-endpoint = <&mixer_in9_ep>;
+ };
+ };
+
+ xbar_mixer_in10_port: port@5d {
+ reg = <0x5d>;
+
+ xbar_mixer_in10_ep: endpoint {
+ remote-endpoint = <&mixer_in10_ep>;
+ };
+ };
+
+ port@5e {
+ reg = <0x5e>;
+
+ xbar_mixer_out1_ep: endpoint {
+ remote-endpoint = <&mixer_out1_ep>;
+ };
+ };
+
+ port@5f {
+ reg = <0x5f>;
+
+ xbar_mixer_out2_ep: endpoint {
+ remote-endpoint = <&mixer_out2_ep>;
+ };
+ };
+
+ port@60 {
+ reg = <0x60>;
+
+ xbar_mixer_out3_ep: endpoint {
+ remote-endpoint = <&mixer_out3_ep>;
+ };
+ };
+
+ port@61 {
+ reg = <0x61>;
+
+ xbar_mixer_out4_ep: endpoint {
+ remote-endpoint = <&mixer_out4_ep>;
+ };
+ };
+
+ port@62 {
+ reg = <0x62>;
+
+ xbar_mixer_out5_ep: endpoint {
+ remote-endpoint = <&mixer_out5_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s1_ep>;
+ };
+ };
+
+ i2s1_port: port@1 {
+ reg = <1>;
+
+ i2s1_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s2_ep>;
+ };
+ };
+
+ i2s2_port: port@1 {
+ reg = <1>;
+
+ i2s2_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
};
- admaif@290f000 {
+ i2s@2901300 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
- admaif0_port: port@0 {
- reg = <0x0>;
+ port@0 {
+ reg = <0>;
- admaif0_ep: endpoint {
- remote-endpoint = <&xbar_admaif0_ep>;
+ i2s4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s4_ep>;
};
};
- admaif1_port: port@1 {
- reg = <0x1>;
+ i2s4_port: port@1 {
+ reg = <1>;
- admaif1_ep: endpoint {
- remote-endpoint = <&xbar_admaif1_ep>;
+ i2s4_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
};
};
+ };
+ };
- admaif2_port: port@2 {
- reg = <0x2>;
+ i2s@2901400 {
+ status = "okay";
- admaif2_ep: endpoint {
- remote-endpoint = <&xbar_admaif2_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s5_ep>;
};
};
- admaif3_port: port@3 {
- reg = <0x3>;
+ i2s5_port: port@1 {
+ reg = <1>;
- admaif3_ep: endpoint {
- remote-endpoint = <&xbar_admaif3_ep>;
+ i2s5_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
};
};
+ };
+ };
- admaif4_port: port@4 {
- reg = <0x4>;
+ i2s@2901500 {
+ status = "okay";
- admaif4_ep: endpoint {
- remote-endpoint = <&xbar_admaif4_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s6_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s6_ep>;
};
};
- admaif5_port: port@5 {
- reg = <0x5>;
+ i2s6_port: port@1 {
+ reg = <1>;
- admaif5_ep: endpoint {
- remote-endpoint = <&xbar_admaif5_ep>;
+ i2s6_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
};
};
+ };
+ };
- admaif6_port: port@6 {
- reg = <0x6>;
+ dmic@2904000 {
+ status = "okay";
- admaif6_ep: endpoint {
- remote-endpoint = <&xbar_admaif6_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
};
};
- admaif7_port: port@7 {
- reg = <0x7>;
+ dmic1_port: port@1 {
+ reg = <1>;
- admaif7_ep: endpoint {
- remote-endpoint = <&xbar_admaif7_ep>;
+ dmic1_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif8_port: port@8 {
- reg = <0x8>;
+ dmic@2904100 {
+ status = "okay";
- admaif8_ep: endpoint {
- remote-endpoint = <&xbar_admaif8_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
};
};
- admaif9_port: port@9 {
- reg = <0x9>;
+ dmic2_port: port@1 {
+ reg = <1>;
- admaif9_ep: endpoint {
- remote-endpoint = <&xbar_admaif9_ep>;
+ dmic2_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif10_port: port@a {
- reg = <0xa>;
+ dmic@2904200 {
+ status = "okay";
- admaif10_ep: endpoint {
- remote-endpoint = <&xbar_admaif10_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic3_ep>;
};
};
- admaif11_port: port@b {
- reg = <0xb>;
+ dmic3_port: port@1 {
+ reg = <1>;
- admaif11_ep: endpoint {
- remote-endpoint = <&xbar_admaif11_ep>;
+ dmic3_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif12_port: port@c {
- reg = <0xc>;
+ dspk@2905000 {
+ status = "okay";
- admaif12_ep: endpoint {
- remote-endpoint = <&xbar_admaif12_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk1_ep>;
};
};
- admaif13_port: port@d {
- reg = <0xd>;
+ dspk1_port: port@1 {
+ reg = <1>;
- admaif13_ep: endpoint {
- remote-endpoint = <&xbar_admaif13_ep>;
+ dspk1_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif14_port: port@e {
- reg = <0xe>;
+ dspk@2905100 {
+ status = "okay";
- admaif14_ep: endpoint {
- remote-endpoint = <&xbar_admaif14_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk2_ep>;
};
};
- admaif15_port: port@f {
- reg = <0xf>;
+ dspk2_port: port@1 {
+ reg = <1>;
- admaif15_ep: endpoint {
- remote-endpoint = <&xbar_admaif15_ep>;
+ dspk2_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif16_port: port@10 {
- reg = <0x10>;
+ sfc@2902000 {
+ status = "okay";
- admaif16_ep: endpoint {
- remote-endpoint = <&xbar_admaif16_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_in_ep>;
+ convert-rate = <44100>;
};
};
- admaif17_port: port@11 {
- reg = <0x11>;
+ sfc1_out_port: port@1 {
+ reg = <1>;
- admaif17_ep: endpoint {
- remote-endpoint = <&xbar_admaif17_ep>;
+ sfc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_out_ep>;
+ convert-rate = <48000>;
+ };
+ };
+ };
+ };
+
+ sfc@2902200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_in_ep>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_in_ep>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_out_ep>;
};
};
+ };
+ };
- admaif18_port: port@12 {
- reg = <0x12>;
+ sfc@2902600 {
+ status = "okay";
- admaif18_ep: endpoint {
- remote-endpoint = <&xbar_admaif18_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_in_ep>;
};
};
- admaif19_port: port@13 {
- reg = <0x13>;
+ sfc4_out_port: port@1 {
+ reg = <1>;
- admaif19_ep: endpoint {
- remote-endpoint = <&xbar_admaif19_ep>;
+ sfc4_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_out_ep>;
};
};
};
};
- i2s@2901000 {
+ mvc@290a000 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s1_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s1_ep>;
+ mvc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_in_ep>;
};
};
- i2s1_port: port@1 {
+ mvc1_out_port: port@1 {
reg = <1>;
- i2s1_dap_ep: endpoint {
- dai-format = "i2s";
- /* Placeholder for external Codec */
+ mvc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_out_ep>;
};
};
};
};
- i2s@2901100 {
+ mvc@290a200 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s2_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s2_ep>;
+ mvc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_in_ep>;
};
};
- i2s2_port: port@1 {
+ mvc2_out_port: port@1 {
reg = <1>;
- i2s2_dap_ep: endpoint {
- dai-format = "i2s";
- /* Placeholder for external Codec */
+ mvc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_out_ep>;
};
};
};
};
- i2s@2901200 {
+ amx@2903000 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s3_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s3_ep>;
+ amx1_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in1_ep>;
};
};
- i2s3_port: port@1 {
+ port@1 {
reg = <1>;
- i2s3_dap_ep: endpoint {
- dai-format = "i2s";
- /* Placeholder for external Codec */
+ amx1_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in4_ep>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_out_ep>;
};
};
};
};
- i2s@2901300 {
+ amx@2903100 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s4_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s4_ep>;
+ amx2_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in1_ep>;
};
};
- i2s4_port: port@1 {
+ port@1 {
reg = <1>;
- i2s4_dap_ep: endpoint {
- dai-format = "i2s";
- /* Placeholder for external Codec */
+ amx2_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in2_ep>;
+ };
+ };
+
+ amx2_in3_port: port@2 {
+ reg = <2>;
+
+ amx2_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in3_ep>;
+ };
+ };
+
+ amx2_in4_port: port@3 {
+ reg = <3>;
+
+ amx2_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in4_ep>;
+ };
+ };
+
+ amx2_out_port: port@4 {
+ reg = <4>;
+
+ amx2_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_out_ep>;
};
};
};
};
- i2s@2901400 {
+ amx@2903200 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s5_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s5_ep>;
+ amx3_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in1_ep>;
};
};
- i2s5_port: port@1 {
+ port@1 {
reg = <1>;
- i2s5_dap_ep: endpoint {
- dai-format = "i2s";
- /* Placeholder for external Codec */
+ amx3_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx3_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx3_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in4_ep>;
+ };
+ };
+
+ amx3_out_port: port@4 {
+ reg = <4>;
+
+ amx3_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_out_ep>;
};
};
};
};
- i2s@2901500 {
+ amx@2903300 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s6_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s6_ep>;
+ amx4_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in1_ep>;
};
};
- i2s6_port: port@1 {
+ port@1 {
reg = <1>;
- i2s6_dap_ep: endpoint {
- dai-format = "i2s";
- /* Placeholder for external Codec */
+ amx4_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx4_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx4_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in4_ep>;
+ };
+ };
+
+ amx4_out_port: port@4 {
+ reg = <4>;
+
+ amx4_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_out_ep>;
};
};
};
};
- dmic@2904000 {
+ adx@2903800 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dmic1_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic1_ep>;
+ adx1_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_in_ep>;
};
};
- dmic1_port: port@1 {
+ adx1_out1_port: port@1 {
reg = <1>;
- dmic1_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx1_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out1_ep>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out2_ep>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out3_ep>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out4_ep>;
};
};
};
};
- dmic@2904100 {
+ adx@2903900 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dmic2_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic2_ep>;
+ adx2_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_in_ep>;
};
};
- dmic2_port: port@1 {
+ adx2_out1_port: port@1 {
reg = <1>;
- dmic2_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx2_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out1_ep>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out2_ep>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out3_ep>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out4_ep>;
};
};
};
};
- dmic@2904200 {
+ adx@2903a00 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dmic3_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic3_ep>;
+ adx3_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_in_ep>;
};
};
- dmic3_port: port@1 {
+ adx3_out1_port: port@1 {
reg = <1>;
- dmic3_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx3_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out1_ep>;
+ };
+ };
+
+ adx3_out2_port: port@2 {
+ reg = <2>;
+
+ adx3_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out2_ep>;
+ };
+ };
+
+ adx3_out3_port: port@3 {
+ reg = <3>;
+
+ adx3_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out3_ep>;
+ };
+ };
+
+ adx3_out4_port: port@4 {
+ reg = <4>;
+
+ adx3_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out4_ep>;
};
};
};
};
- dspk@2905000 {
+ adx@2903b00 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dspk1_cif_ep: endpoint {
- remote-endpoint = <&xbar_dspk1_ep>;
+ adx4_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_in_ep>;
};
};
- dspk1_port: port@1 {
+ adx4_out1_port: port@1 {
reg = <1>;
- dspk1_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx4_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out1_ep>;
+ };
+ };
+
+ adx4_out2_port: port@2 {
+ reg = <2>;
+
+ adx4_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out2_ep>;
+ };
+ };
+
+ adx4_out3_port: port@3 {
+ reg = <3>;
+
+ adx4_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out3_ep>;
+ };
+ };
+
+ adx4_out4_port: port@4 {
+ reg = <4>;
+
+ adx4_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out4_ep>;
};
};
};
};
- dspk@2905100 {
+ amixer@290bb00 {
status = "okay";
ports {
#size-cells = <0>;
port@0 {
- reg = <0>;
+ reg = <0x0>;
- dspk2_cif_ep: endpoint {
- remote-endpoint = <&xbar_dspk2_ep>;
+ mixer_in1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in1_ep>;
};
};
- dspk2_port: port@1 {
- reg = <1>;
+ port@1 {
+ reg = <0x1>;
- dspk2_dap_ep: endpoint {
- /* Place holder for external Codec */
+ mixer_in2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mixer_in3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mixer_in4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mixer_in5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mixer_in6_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mixer_in7_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in7_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mixer_in8_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in8_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mixer_in9_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in9_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mixer_in10_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in10_ep>;
+ };
+ };
+
+ mixer_out1_port: port@a {
+ reg = <0xa>;
+
+ mixer_out1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out1_ep>;
+ };
+ };
+
+ mixer_out2_port: port@b {
+ reg = <0xb>;
+
+ mixer_out2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out2_ep>;
+ };
+ };
+
+ mixer_out3_port: port@c {
+ reg = <0xc>;
+
+ mixer_out3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out3_ep>;
+ };
+ };
+
+ mixer_out4_port: port@d {
+ reg = <0xd>;
+
+ mixer_out4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out4_ep>;
+ };
+ };
+
+ mixer_out5_port: port@e {
+ reg = <0xe>;
+
+ mixer_out5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out5_ep>;
};
};
};
<&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
<&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
<&xbar_dspk1_port>, <&xbar_dspk2_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+ <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+ <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+ <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+ <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
+ <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
+ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
+ <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
+ <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&amx3_out_port>, <&amx4_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&adx3_out1_port>, <&adx3_out2_port>,
+ <&adx3_out3_port>, <&adx3_out4_port>,
+ <&adx4_out1_port>, <&adx4_out2_port>,
+ <&adx4_out3_port>, <&adx4_out4_port>,
+ <&mixer_out1_port>, <&mixer_out2_port>,
+ <&mixer_out3_port>, <&mixer_out4_port>,
+ <&mixer_out5_port>,
/* I/O */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
};
hda@3510000 {
- nvidia,model = "jetson-tx2-hda";
+ nvidia,model = "NVIDIA Jetson TX2 NX HDA";
status = "okay";
};
};
};
};
+
+ aconnect@2900000 {
+ status = "okay";
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a40000 {
+ status = "okay";
+ };
+
+ ahub@2900800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0_ep: endpoint {
+ remote-endpoint = <&admaif0_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1_ep: endpoint {
+ remote-endpoint = <&admaif1_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2_ep: endpoint {
+ remote-endpoint = <&admaif2_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3_ep: endpoint {
+ remote-endpoint = <&admaif3_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4_ep: endpoint {
+ remote-endpoint = <&admaif4_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5_ep: endpoint {
+ remote-endpoint = <&admaif5_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6_ep: endpoint {
+ remote-endpoint = <&admaif6_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7_ep: endpoint {
+ remote-endpoint = <&admaif7_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8_ep: endpoint {
+ remote-endpoint = <&admaif8_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9_ep: endpoint {
+ remote-endpoint = <&admaif9_ep>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10_ep: endpoint {
+ remote-endpoint = <&admaif10_ep>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11_ep: endpoint {
+ remote-endpoint = <&admaif11_ep>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12_ep: endpoint {
+ remote-endpoint = <&admaif12_ep>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13_ep: endpoint {
+ remote-endpoint = <&admaif13_ep>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14_ep: endpoint {
+ remote-endpoint = <&admaif14_ep>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15_ep: endpoint {
+ remote-endpoint = <&admaif15_ep>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16_ep: endpoint {
+ remote-endpoint = <&admaif16_ep>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17_ep: endpoint {
+ remote-endpoint = <&admaif17_ep>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18_ep: endpoint {
+ remote-endpoint = <&admaif18_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19_ep: endpoint {
+ remote-endpoint = <&admaif19_ep>;
+ };
+ };
+
+ xbar_i2s1_port: port@14 {
+ reg = <0x14>;
+
+ xbar_i2s1_ep: endpoint {
+ remote-endpoint = <&i2s1_cif_ep>;
+ };
+ };
+
+ xbar_i2s3_port: port@16 {
+ reg = <0x16>;
+
+ xbar_i2s3_ep: endpoint {
+ remote-endpoint = <&i2s3_cif_ep>;
+ };
+ };
+
+ xbar_dmic1_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_dmic1_ep: endpoint {
+ remote-endpoint = <&dmic1_cif_ep>;
+ };
+ };
+
+ xbar_dmic2_port: port@1b {
+ reg = <0x1b>;
+
+ xbar_dmic2_ep: endpoint {
+ remote-endpoint = <&dmic2_cif_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s1_ep>;
+ };
+ };
+
+ i2s1_port: port@1 {
+ reg = <1>;
+
+ i2s1_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Placeholder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
+ };
+ };
+
+ dmic1_port: port@1 {
+ reg = <1>;
+
+ dmic1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
+ };
+ };
+
+ dmic2_port: port@1 {
+ reg = <1>;
+
+ dmic2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra186-audio-graph-card";
+ status = "okay";
+
+ dais = /* FE */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* Router */
+ <&xbar_i2s1_port>, <&xbar_i2s3_port>,
+ <&xbar_dmic1_port>, <&xbar_dmic2_port>,
+ /* I/O */
+ <&i2s1_port>, <&i2s3_port>,
+ <&dmic1_port>, <&dmic2_port>;
+
+ label = "NVIDIA Jetson TX2 NX APE";
+ };
};
sound-name-prefix = "DSPK2";
status = "disabled";
};
+
+ tegra_sfc1: sfc@2902000 {
+ compatible = "nvidia,tegra186-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902000 0x200>;
+ sound-name-prefix = "SFC1";
+ status = "disabled";
+ };
+
+ tegra_sfc2: sfc@2902200 {
+ compatible = "nvidia,tegra186-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902200 0x200>;
+ sound-name-prefix = "SFC2";
+ status = "disabled";
+ };
+
+ tegra_sfc3: sfc@2902400 {
+ compatible = "nvidia,tegra186-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902400 0x200>;
+ sound-name-prefix = "SFC3";
+ status = "disabled";
+ };
+
+ tegra_sfc4: sfc@2902600 {
+ compatible = "nvidia,tegra186-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902600 0x200>;
+ sound-name-prefix = "SFC4";
+ status = "disabled";
+ };
+
+ tegra_mvc1: mvc@290a000 {
+ compatible = "nvidia,tegra186-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x290a000 0x200>;
+ sound-name-prefix = "MVC1";
+ status = "disabled";
+ };
+
+ tegra_mvc2: mvc@290a200 {
+ compatible = "nvidia,tegra186-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x290a200 0x200>;
+ sound-name-prefix = "MVC2";
+ status = "disabled";
+ };
+
+ tegra_amx1: amx@2903000 {
+ compatible = "nvidia,tegra186-amx",
+ "nvidia,tegra210-amx";
+ reg = <0x2903000 0x100>;
+ sound-name-prefix = "AMX1";
+ status = "disabled";
+ };
+
+ tegra_amx2: amx@2903100 {
+ compatible = "nvidia,tegra186-amx",
+ "nvidia,tegra210-amx";
+ reg = <0x2903100 0x100>;
+ sound-name-prefix = "AMX2";
+ status = "disabled";
+ };
+
+ tegra_amx3: amx@2903200 {
+ compatible = "nvidia,tegra186-amx",
+ "nvidia,tegra210-amx";
+ reg = <0x2903200 0x100>;
+ sound-name-prefix = "AMX3";
+ status = "disabled";
+ };
+
+ tegra_amx4: amx@2903300 {
+ compatible = "nvidia,tegra186-amx",
+ "nvidia,tegra210-amx";
+ reg = <0x2903300 0x100>;
+ sound-name-prefix = "AMX4";
+ status = "disabled";
+ };
+
+ tegra_adx1: adx@2903800 {
+ compatible = "nvidia,tegra186-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903800 0x100>;
+ sound-name-prefix = "ADX1";
+ status = "disabled";
+ };
+
+ tegra_adx2: adx@2903900 {
+ compatible = "nvidia,tegra186-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903900 0x100>;
+ sound-name-prefix = "ADX2";
+ status = "disabled";
+ };
+
+ tegra_adx3: adx@2903a00 {
+ compatible = "nvidia,tegra186-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903a00 0x100>;
+ sound-name-prefix = "ADX3";
+ status = "disabled";
+ };
+
+ tegra_adx4: adx@2903b00 {
+ compatible = "nvidia,tegra186-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903b00 0x100>;
+ sound-name-prefix = "ADX4";
+ status = "disabled";
+ };
+
+ tegra_amixer: amixer@290bb00 {
+ compatible = "nvidia,tegra186-amixer",
+ "nvidia,tegra210-amixer";
+ reg = <0x290bb00 0x800>;
+ sound-name-prefix = "MIXER1";
+ status = "disabled";
+ };
};
};
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
+ nvdec@15480000 {
+ compatible = "nvidia,tegra186-nvdec";
+ reg = <0x15480000 0x40000>;
+ clocks = <&bpmp TEGRA186_CLK_NVDEC>;
+ clock-names = "nvdec";
+ resets = <&bpmp TEGRA186_RESET_NVDEC>;
+ reset-names = "nvdec";
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA186_SID_NVDEC>;
+ };
+
sor0: sor@15540000 {
compatible = "nvidia,tegra186-sor";
reg = <0x15540000 0x10000>;
remote-endpoint = <&dmic3_cif_ep>;
};
};
+
+ xbar_sfc1_in_port: port@20 {
+ reg = <0x20>;
+
+ xbar_sfc1_in_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_in_ep>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ xbar_sfc1_out_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@22 {
+ reg = <0x22>;
+
+ xbar_sfc2_in_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_in_ep>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ xbar_sfc2_out_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@24 {
+ reg = <0x24>;
+
+ xbar_sfc3_in_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_in_ep>;
+ };
+ };
+
+ port@25 {
+ reg = <0x25>;
+
+ xbar_sfc3_out_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@26 {
+ reg = <0x26>;
+
+ xbar_sfc4_in_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_in_ep>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_sfc4_out_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_mvc1_in_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_in_ep>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_mvc1_out_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@2a {
+ reg = <0x2a>;
+
+ xbar_mvc2_in_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_in_ep>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_mvc2_out_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_out_ep>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@2c {
+ reg = <0x2c>;
+
+ xbar_amx1_in1_ep: endpoint {
+ remote-endpoint = <&amx1_in1_ep>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_amx1_in2_ep: endpoint {
+ remote-endpoint = <&amx1_in2_ep>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@2e {
+ reg = <0x2e>;
+
+ xbar_amx1_in3_ep: endpoint {
+ remote-endpoint = <&amx1_in3_ep>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@2f {
+ reg = <0x2f>;
+
+ xbar_amx1_in4_ep: endpoint {
+ remote-endpoint = <&amx1_in4_ep>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_amx1_out_ep: endpoint {
+ remote-endpoint = <&amx1_out_ep>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@31 {
+ reg = <0x31>;
+
+ xbar_amx2_in1_ep: endpoint {
+ remote-endpoint = <&amx2_in1_ep>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@32 {
+ reg = <0x32>;
+
+ xbar_amx2_in2_ep: endpoint {
+ remote-endpoint = <&amx2_in2_ep>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@33 {
+ reg = <0x33>;
+
+ xbar_amx2_in3_ep: endpoint {
+ remote-endpoint = <&amx2_in3_ep>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@34 {
+ reg = <0x34>;
+
+ xbar_amx2_in4_ep: endpoint {
+ remote-endpoint = <&amx2_in4_ep>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ xbar_amx2_out_ep: endpoint {
+ remote-endpoint = <&amx2_out_ep>;
+ };
+ };
+
+ xbar_amx3_in1_port: port@36 {
+ reg = <0x36>;
+
+ xbar_amx3_in1_ep: endpoint {
+ remote-endpoint = <&amx3_in1_ep>;
+ };
+ };
+
+ xbar_amx3_in2_port: port@37 {
+ reg = <0x37>;
+
+ xbar_amx3_in2_ep: endpoint {
+ remote-endpoint = <&amx3_in2_ep>;
+ };
+ };
+
+ xbar_amx3_in3_port: port@38 {
+ reg = <0x38>;
+
+ xbar_amx3_in3_ep: endpoint {
+ remote-endpoint = <&amx3_in3_ep>;
+ };
+ };
+
+ xbar_amx3_in4_port: port@39 {
+ reg = <0x39>;
+
+ xbar_amx3_in4_ep: endpoint {
+ remote-endpoint = <&amx3_in4_ep>;
+ };
+ };
+
+ port@3a {
+ reg = <0x3a>;
+
+ xbar_amx3_out_ep: endpoint {
+ remote-endpoint = <&amx3_out_ep>;
+ };
+ };
+
+ xbar_amx4_in1_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_amx4_in1_ep: endpoint {
+ remote-endpoint = <&amx4_in1_ep>;
+ };
+ };
+
+ xbar_amx4_in2_port: port@3c {
+ reg = <0x3c>;
+
+ xbar_amx4_in2_ep: endpoint {
+ remote-endpoint = <&amx4_in2_ep>;
+ };
+ };
+
+ xbar_amx4_in3_port: port@3d {
+ reg = <0x3d>;
+
+ xbar_amx4_in3_ep: endpoint {
+ remote-endpoint = <&amx4_in3_ep>;
+ };
+ };
+
+ xbar_amx4_in4_port: port@3e {
+ reg = <0x3e>;
+
+ xbar_amx4_in4_ep: endpoint {
+ remote-endpoint = <&amx4_in4_ep>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_amx4_out_ep: endpoint {
+ remote-endpoint = <&amx4_out_ep>;
+ };
+ };
+
+ xbar_adx1_in_port: port@40 {
+ reg = <0x40>;
+
+ xbar_adx1_in_ep: endpoint {
+ remote-endpoint = <&adx1_in_ep>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ xbar_adx1_out1_ep: endpoint {
+ remote-endpoint = <&adx1_out1_ep>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_adx1_out2_ep: endpoint {
+ remote-endpoint = <&adx1_out2_ep>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ xbar_adx1_out3_ep: endpoint {
+ remote-endpoint = <&adx1_out3_ep>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_adx1_out4_ep: endpoint {
+ remote-endpoint = <&adx1_out4_ep>;
+ };
+ };
+
+ xbar_adx2_in_port: port@45 {
+ reg = <0x45>;
+
+ xbar_adx2_in_ep: endpoint {
+ remote-endpoint = <&adx2_in_ep>;
+ };
+ };
+
+ port@46 {
+ reg = <0x46>;
+
+ xbar_adx2_out1_ep: endpoint {
+ remote-endpoint = <&adx2_out1_ep>;
+ };
+ };
+
+ port@47 {
+ reg = <0x47>;
+
+ xbar_adx2_out2_ep: endpoint {
+ remote-endpoint = <&adx2_out2_ep>;
+ };
+ };
+
+ port@48 {
+ reg = <0x48>;
+
+ xbar_adx2_out3_ep: endpoint {
+ remote-endpoint = <&adx2_out3_ep>;
+ };
+ };
+
+ port@49 {
+ reg = <0x49>;
+
+ xbar_adx2_out4_ep: endpoint {
+ remote-endpoint = <&adx2_out4_ep>;
+ };
+ };
+
+ xbar_adx3_in_port: port@4a {
+ reg = <0x4a>;
+
+ xbar_adx3_in_ep: endpoint {
+ remote-endpoint = <&adx3_in_ep>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ xbar_adx3_out1_ep: endpoint {
+ remote-endpoint = <&adx3_out1_ep>;
+ };
+ };
+
+ port@4c {
+ reg = <0x4c>;
+
+ xbar_adx3_out2_ep: endpoint {
+ remote-endpoint = <&adx3_out2_ep>;
+ };
+ };
+
+ port@4d {
+ reg = <0x4d>;
+
+ xbar_adx3_out3_ep: endpoint {
+ remote-endpoint = <&adx3_out3_ep>;
+ };
+ };
+
+ port@4e {
+ reg = <0x4e>;
+
+ xbar_adx3_out4_ep: endpoint {
+ remote-endpoint = <&adx3_out4_ep>;
+ };
+ };
+
+ xbar_adx4_in_port: port@4f {
+ reg = <0x4f>;
+
+ xbar_adx4_in_ep: endpoint {
+ remote-endpoint = <&adx4_in_ep>;
+ };
+ };
+
+ port@50 {
+ reg = <0x50>;
+
+ xbar_adx4_out1_ep: endpoint {
+ remote-endpoint = <&adx4_out1_ep>;
+ };
+ };
+
+ port@51 {
+ reg = <0x51>;
+
+ xbar_adx4_out2_ep: endpoint {
+ remote-endpoint = <&adx4_out2_ep>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ xbar_adx4_out3_ep: endpoint {
+ remote-endpoint = <&adx4_out3_ep>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ xbar_adx4_out4_ep: endpoint {
+ remote-endpoint = <&adx4_out4_ep>;
+ };
+ };
+
+ xbar_mixer_in1_port: port@54 {
+ reg = <0x54>;
+
+ xbar_mixer_in1_ep: endpoint {
+ remote-endpoint = <&mixer_in1_ep>;
+ };
+ };
+
+ xbar_mixer_in2_port: port@55 {
+ reg = <0x55>;
+
+ xbar_mixer_in2_ep: endpoint {
+ remote-endpoint = <&mixer_in2_ep>;
+ };
+ };
+
+ xbar_mixer_in3_port: port@56 {
+ reg = <0x56>;
+
+ xbar_mixer_in3_ep: endpoint {
+ remote-endpoint = <&mixer_in3_ep>;
+ };
+ };
+
+ xbar_mixer_in4_port: port@57 {
+ reg = <0x57>;
+
+ xbar_mixer_in4_ep: endpoint {
+ remote-endpoint = <&mixer_in4_ep>;
+ };
+ };
+
+ xbar_mixer_in5_port: port@58 {
+ reg = <0x58>;
+
+ xbar_mixer_in5_ep: endpoint {
+ remote-endpoint = <&mixer_in5_ep>;
+ };
+ };
+
+ xbar_mixer_in6_port: port@59 {
+ reg = <0x59>;
+
+ xbar_mixer_in6_ep: endpoint {
+ remote-endpoint = <&mixer_in6_ep>;
+ };
+ };
+
+ xbar_mixer_in7_port: port@5a {
+ reg = <0x5a>;
+
+ xbar_mixer_in7_ep: endpoint {
+ remote-endpoint = <&mixer_in7_ep>;
+ };
+ };
+
+ xbar_mixer_in8_port: port@5b {
+ reg = <0x5b>;
+
+ xbar_mixer_in8_ep: endpoint {
+ remote-endpoint = <&mixer_in8_ep>;
+ };
+ };
+
+ xbar_mixer_in9_port: port@5c {
+ reg = <0x5c>;
+
+ xbar_mixer_in9_ep: endpoint {
+ remote-endpoint = <&mixer_in9_ep>;
+ };
+ };
+
+ xbar_mixer_in10_port: port@5d {
+ reg = <0x5d>;
+
+ xbar_mixer_in10_ep: endpoint {
+ remote-endpoint = <&mixer_in10_ep>;
+ };
+ };
+
+ port@5e {
+ reg = <0x5e>;
+
+ xbar_mixer_out1_ep: endpoint {
+ remote-endpoint = <&mixer_out1_ep>;
+ };
+ };
+
+ port@5f {
+ reg = <0x5f>;
+
+ xbar_mixer_out2_ep: endpoint {
+ remote-endpoint = <&mixer_out2_ep>;
+ };
+ };
+
+ port@60 {
+ reg = <0x60>;
+
+ xbar_mixer_out3_ep: endpoint {
+ remote-endpoint = <&mixer_out3_ep>;
+ };
+ };
+
+ port@61 {
+ reg = <0x61>;
+
+ xbar_mixer_out4_ep: endpoint {
+ remote-endpoint = <&mixer_out4_ep>;
+ };
+ };
+
+ port@62 {
+ reg = <0x62>;
+
+ xbar_mixer_out5_ep: endpoint {
+ remote-endpoint = <&mixer_out5_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s1_ep>;
+ };
+ };
+
+ i2s1_port: port@1 {
+ reg = <1>;
+
+ i2s1_dap_ep: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&rt5658_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s2_ep>;
+ };
+ };
+
+ i2s2_port: port@1 {
+ reg = <1>;
+
+ i2s2_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901300 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s4_ep>;
+ };
+ };
+
+ i2s4_port: port@1 {
+ reg = <1>;
+
+ i2s4_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901500 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s6_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s6_ep>;
+ };
+ };
+
+ i2s6_port: port@1 {
+ reg = <1>;
+
+ i2s6_dap_ep: endpoint@0 {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic3_ep>;
+ };
+ };
+
+ dmic3_port: port@1 {
+ reg = <1>;
+
+ dmic3_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ sfc@2902000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_in_ep>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_in_ep>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_in_ep>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902600 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_in_ep>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@290a000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_in_ep>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@290a200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_in_ep>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@2903000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx1_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in4_ep>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_out_ep>;
+ };
+ };
+ };
};
- admaif@290f000 {
+ amx@2903100 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
- admaif0_port: port@0 {
- reg = <0x0>;
+ port@0 {
+ reg = <0>;
- admaif0_ep: endpoint {
- remote-endpoint = <&xbar_admaif0_ep>;
+ amx2_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in1_ep>;
};
};
- admaif1_port: port@1 {
- reg = <0x1>;
+ port@1 {
+ reg = <1>;
- admaif1_ep: endpoint {
- remote-endpoint = <&xbar_admaif1_ep>;
+ amx2_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in2_ep>;
};
};
- admaif2_port: port@2 {
- reg = <0x2>;
+ amx2_in3_port: port@2 {
+ reg = <2>;
- admaif2_ep: endpoint {
- remote-endpoint = <&xbar_admaif2_ep>;
+ amx2_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in3_ep>;
};
};
- admaif3_port: port@3 {
- reg = <0x3>;
+ amx2_in4_port: port@3 {
+ reg = <3>;
- admaif3_ep: endpoint {
- remote-endpoint = <&xbar_admaif3_ep>;
+ amx2_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in4_ep>;
};
};
- admaif4_port: port@4 {
- reg = <0x4>;
+ amx2_out_port: port@4 {
+ reg = <4>;
- admaif4_ep: endpoint {
- remote-endpoint = <&xbar_admaif4_ep>;
+ amx2_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_out_ep>;
};
};
+ };
+ };
- admaif5_port: port@5 {
- reg = <0x5>;
+ amx@2903200 {
+ status = "okay";
- admaif5_ep: endpoint {
- remote-endpoint = <&xbar_admaif5_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx3_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in1_ep>;
};
};
- admaif6_port: port@6 {
- reg = <0x6>;
+ port@1 {
+ reg = <1>;
- admaif6_ep: endpoint {
- remote-endpoint = <&xbar_admaif6_ep>;
+ amx3_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in2_ep>;
};
};
- admaif7_port: port@7 {
- reg = <0x7>;
+ port@2 {
+ reg = <2>;
- admaif7_ep: endpoint {
- remote-endpoint = <&xbar_admaif7_ep>;
+ amx3_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in3_ep>;
};
};
- admaif8_port: port@8 {
- reg = <0x8>;
+ port@3 {
+ reg = <3>;
- admaif8_ep: endpoint {
- remote-endpoint = <&xbar_admaif8_ep>;
+ amx3_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in4_ep>;
};
};
- admaif9_port: port@9 {
- reg = <0x9>;
+ amx3_out_port: port@4 {
+ reg = <4>;
- admaif9_ep: endpoint {
- remote-endpoint = <&xbar_admaif9_ep>;
+ amx3_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_out_ep>;
};
};
+ };
+ };
- admaif10_port: port@a {
- reg = <0xa>;
+ amx@2903300 {
+ status = "okay";
- admaif10_ep: endpoint {
- remote-endpoint = <&xbar_admaif10_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx4_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in1_ep>;
};
};
- admaif11_port: port@b {
- reg = <0xb>;
+ port@1 {
+ reg = <1>;
- admaif11_ep: endpoint {
- remote-endpoint = <&xbar_admaif11_ep>;
+ amx4_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in2_ep>;
};
};
- admaif12_port: port@c {
- reg = <0xc>;
+ port@2 {
+ reg = <2>;
- admaif12_ep: endpoint {
- remote-endpoint = <&xbar_admaif12_ep>;
+ amx4_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in3_ep>;
};
};
- admaif13_port: port@d {
- reg = <0xd>;
+ port@3 {
+ reg = <3>;
- admaif13_ep: endpoint {
- remote-endpoint = <&xbar_admaif13_ep>;
+ amx4_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in4_ep>;
};
};
- admaif14_port: port@e {
- reg = <0xe>;
+ amx4_out_port: port@4 {
+ reg = <4>;
- admaif14_ep: endpoint {
- remote-endpoint = <&xbar_admaif14_ep>;
+ amx4_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_out_ep>;
};
};
+ };
+ };
- admaif15_port: port@f {
- reg = <0xf>;
+ adx@2903800 {
+ status = "okay";
- admaif15_ep: endpoint {
- remote-endpoint = <&xbar_admaif15_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx1_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_in_ep>;
};
};
- admaif16_port: port@10 {
- reg = <0x10>;
+ adx1_out1_port: port@1 {
+ reg = <1>;
- admaif16_ep: endpoint {
- remote-endpoint = <&xbar_admaif16_ep>;
+ adx1_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out1_ep>;
};
};
- admaif17_port: port@11 {
- reg = <0x11>;
+ adx1_out2_port: port@2 {
+ reg = <2>;
- admaif17_ep: endpoint {
- remote-endpoint = <&xbar_admaif17_ep>;
+ adx1_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out2_ep>;
};
};
- admaif18_port: port@12 {
- reg = <0x12>;
+ adx1_out3_port: port@3 {
+ reg = <3>;
- admaif18_ep: endpoint {
- remote-endpoint = <&xbar_admaif18_ep>;
+ adx1_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out3_ep>;
};
};
- admaif19_port: port@13 {
- reg = <0x13>;
+ adx1_out4_port: port@4 {
+ reg = <4>;
- admaif19_ep: endpoint {
- remote-endpoint = <&xbar_admaif19_ep>;
+ adx1_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out4_ep>;
};
};
};
};
- i2s@2901000 {
+ adx@2903900 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s1_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s1_ep>;
+ adx2_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_in_ep>;
};
};
- i2s1_port: port@1 {
+ adx2_out1_port: port@1 {
reg = <1>;
- i2s1_dap_ep: endpoint {
- dai-format = "i2s";
- remote-endpoint = <&rt5658_ep>;
+ adx2_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out1_ep>;
};
};
- };
- };
- i2s@2901100 {
- status = "okay";
+ adx2_out2_port: port@2 {
+ reg = <2>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ adx2_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out2_ep>;
+ };
+ };
- port@0 {
- reg = <0>;
+ adx2_out3_port: port@3 {
+ reg = <3>;
- i2s2_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s2_ep>;
+ adx2_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out3_ep>;
};
};
- i2s2_port: port@1 {
- reg = <1>;
+ adx2_out4_port: port@4 {
+ reg = <4>;
- i2s2_dap_ep: endpoint {
- dai-format = "i2s";
- /* Place holder for external Codec */
+ adx2_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out4_ep>;
};
};
};
};
- i2s@2901300 {
+ adx@2903a00 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s4_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s4_ep>;
+ adx3_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_in_ep>;
};
};
- i2s4_port: port@1 {
+ adx3_out1_port: port@1 {
reg = <1>;
- i2s4_dap_ep: endpoint {
- dai-format = "i2s";
- /* Place holder for external Codec */
+ adx3_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out1_ep>;
+ };
+ };
+
+ adx3_out2_port: port@2 {
+ reg = <2>;
+
+ adx3_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out2_ep>;
+ };
+ };
+
+ adx3_out3_port: port@3 {
+ reg = <3>;
+
+ adx3_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out3_ep>;
+ };
+ };
+
+ adx3_out4_port: port@4 {
+ reg = <4>;
+
+ adx3_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out4_ep>;
};
};
};
};
- i2s@2901500 {
+ adx@2903b00 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s6_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s6_ep>;
+ adx4_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_in_ep>;
};
};
- i2s6_port: port@1 {
+ adx4_out1_port: port@1 {
reg = <1>;
- i2s6_dap_ep: endpoint@0 {
- dai-format = "i2s";
- /* Place holder for external Codec */
+ adx4_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out1_ep>;
+ };
+ };
+
+ adx4_out2_port: port@2 {
+ reg = <2>;
+
+ adx4_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out2_ep>;
+ };
+ };
+
+ adx4_out3_port: port@3 {
+ reg = <3>;
+
+ adx4_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out3_ep>;
+ };
+ };
+
+ adx4_out4_port: port@4 {
+ reg = <4>;
+
+ adx4_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out4_ep>;
};
};
};
};
- dmic@2904200 {
+ amixer@290bb00 {
status = "okay";
ports {
#size-cells = <0>;
port@0 {
- reg = <0>;
+ reg = <0x0>;
- dmic3_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic3_ep>;
+ mixer_in1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in1_ep>;
};
};
- dmic3_port: port@1 {
- reg = <1>;
+ port@1 {
+ reg = <0x1>;
- dmic3_dap_ep: endpoint {
- /* Place holder for external Codec */
+ mixer_in2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mixer_in3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mixer_in4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mixer_in5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mixer_in6_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mixer_in7_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in7_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mixer_in8_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in8_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mixer_in9_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in9_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mixer_in10_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in10_ep>;
+ };
+ };
+
+ mixer_out1_port: port@a {
+ reg = <0xa>;
+
+ mixer_out1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out1_ep>;
+ };
+ };
+
+ mixer_out2_port: port@b {
+ reg = <0xb>;
+
+ mixer_out2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out2_ep>;
+ };
+ };
+
+ mixer_out3_port: port@c {
+ reg = <0xc>;
+
+ mixer_out3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out3_ep>;
+ };
+ };
+
+ mixer_out4_port: port@d {
+ reg = <0xd>;
+
+ mixer_out4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out4_ep>;
+ };
+ };
+
+ mixer_out5_port: port@e {
+ reg = <0xe>;
+
+ mixer_out5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out5_ep>;
};
};
};
"p2u-5", "p2u-6", "p2u-7";
};
- pcie_ep@141a0000 {
+ pcie-ep@141a0000 {
status = "disabled";
vddio-pex-ctl-supply = <&vdd_1v8ao>;
/* XBAR Ports */
<&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
<&xbar_i2s6_port>, <&xbar_dmic3_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+ <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+ <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+ <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+ <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
+ <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
+ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
+ <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
+ <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&amx3_out_port>, <&amx4_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&adx3_out1_port>, <&adx3_out2_port>,
+ <&adx3_out3_port>, <&adx3_out4_port>,
+ <&adx4_out1_port>, <&adx4_out2_port>,
+ <&adx4_out3_port>, <&adx4_out4_port>,
+ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>,
+ <&mixer_out4_port>, <&mixer_out5_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
remote-endpoint = <&dspk2_cif_ep>;
};
};
+
+ xbar_sfc1_in_port: port@20 {
+ reg = <0x20>;
+
+ xbar_sfc1_in_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_in_ep>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ xbar_sfc1_out_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@22 {
+ reg = <0x22>;
+
+ xbar_sfc2_in_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_in_ep>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ xbar_sfc2_out_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@24 {
+ reg = <0x24>;
+
+ xbar_sfc3_in_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_in_ep>;
+ };
+ };
+
+ port@25 {
+ reg = <0x25>;
+
+ xbar_sfc3_out_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@26 {
+ reg = <0x26>;
+
+ xbar_sfc4_in_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_in_ep>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_sfc4_out_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_mvc1_in_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_in_ep>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_mvc1_out_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@2a {
+ reg = <0x2a>;
+
+ xbar_mvc2_in_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_in_ep>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_mvc2_out_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_out_ep>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@2c {
+ reg = <0x2c>;
+
+ xbar_amx1_in1_ep: endpoint {
+ remote-endpoint = <&amx1_in1_ep>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_amx1_in2_ep: endpoint {
+ remote-endpoint = <&amx1_in2_ep>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@2e {
+ reg = <0x2e>;
+
+ xbar_amx1_in3_ep: endpoint {
+ remote-endpoint = <&amx1_in3_ep>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@2f {
+ reg = <0x2f>;
+
+ xbar_amx1_in4_ep: endpoint {
+ remote-endpoint = <&amx1_in4_ep>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_amx1_out_ep: endpoint {
+ remote-endpoint = <&amx1_out_ep>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@31 {
+ reg = <0x31>;
+
+ xbar_amx2_in1_ep: endpoint {
+ remote-endpoint = <&amx2_in1_ep>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@32 {
+ reg = <0x32>;
+
+ xbar_amx2_in2_ep: endpoint {
+ remote-endpoint = <&amx2_in2_ep>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@33 {
+ reg = <0x33>;
+
+ xbar_amx2_in3_ep: endpoint {
+ remote-endpoint = <&amx2_in3_ep>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@34 {
+ reg = <0x34>;
+
+ xbar_amx2_in4_ep: endpoint {
+ remote-endpoint = <&amx2_in4_ep>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ xbar_amx2_out_ep: endpoint {
+ remote-endpoint = <&amx2_out_ep>;
+ };
+ };
+
+ xbar_amx3_in1_port: port@36 {
+ reg = <0x36>;
+
+ xbar_amx3_in1_ep: endpoint {
+ remote-endpoint = <&amx3_in1_ep>;
+ };
+ };
+
+ xbar_amx3_in2_port: port@37 {
+ reg = <0x37>;
+
+ xbar_amx3_in2_ep: endpoint {
+ remote-endpoint = <&amx3_in2_ep>;
+ };
+ };
+
+ xbar_amx3_in3_port: port@38 {
+ reg = <0x38>;
+
+ xbar_amx3_in3_ep: endpoint {
+ remote-endpoint = <&amx3_in3_ep>;
+ };
+ };
+
+ xbar_amx3_in4_port: port@39 {
+ reg = <0x39>;
+
+ xbar_amx3_in4_ep: endpoint {
+ remote-endpoint = <&amx3_in4_ep>;
+ };
+ };
+
+ port@3a {
+ reg = <0x3a>;
+
+ xbar_amx3_out_ep: endpoint {
+ remote-endpoint = <&amx3_out_ep>;
+ };
+ };
+
+ xbar_amx4_in1_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_amx4_in1_ep: endpoint {
+ remote-endpoint = <&amx4_in1_ep>;
+ };
+ };
+
+ xbar_amx4_in2_port: port@3c {
+ reg = <0x3c>;
+
+ xbar_amx4_in2_ep: endpoint {
+ remote-endpoint = <&amx4_in2_ep>;
+ };
+ };
+
+ xbar_amx4_in3_port: port@3d {
+ reg = <0x3d>;
+
+ xbar_amx4_in3_ep: endpoint {
+ remote-endpoint = <&amx4_in3_ep>;
+ };
+ };
+
+ xbar_amx4_in4_port: port@3e {
+ reg = <0x3e>;
+
+ xbar_amx4_in4_ep: endpoint {
+ remote-endpoint = <&amx4_in4_ep>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_amx4_out_ep: endpoint {
+ remote-endpoint = <&amx4_out_ep>;
+ };
+ };
+
+ xbar_adx1_in_port: port@40 {
+ reg = <0x40>;
+
+ xbar_adx1_in_ep: endpoint {
+ remote-endpoint = <&adx1_in_ep>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ xbar_adx1_out1_ep: endpoint {
+ remote-endpoint = <&adx1_out1_ep>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_adx1_out2_ep: endpoint {
+ remote-endpoint = <&adx1_out2_ep>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ xbar_adx1_out3_ep: endpoint {
+ remote-endpoint = <&adx1_out3_ep>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_adx1_out4_ep: endpoint {
+ remote-endpoint = <&adx1_out4_ep>;
+ };
+ };
+
+ xbar_adx2_in_port: port@45 {
+ reg = <0x45>;
+
+ xbar_adx2_in_ep: endpoint {
+ remote-endpoint = <&adx2_in_ep>;
+ };
+ };
+
+ port@46 {
+ reg = <0x46>;
+
+ xbar_adx2_out1_ep: endpoint {
+ remote-endpoint = <&adx2_out1_ep>;
+ };
+ };
+
+ port@47 {
+ reg = <0x47>;
+
+ xbar_adx2_out2_ep: endpoint {
+ remote-endpoint = <&adx2_out2_ep>;
+ };
+ };
+
+ port@48 {
+ reg = <0x48>;
+
+ xbar_adx2_out3_ep: endpoint {
+ remote-endpoint = <&adx2_out3_ep>;
+ };
+ };
+
+ port@49 {
+ reg = <0x49>;
+
+ xbar_adx2_out4_ep: endpoint {
+ remote-endpoint = <&adx2_out4_ep>;
+ };
+ };
+
+ xbar_adx3_in_port: port@4a {
+ reg = <0x4a>;
+
+ xbar_adx3_in_ep: endpoint {
+ remote-endpoint = <&adx3_in_ep>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ xbar_adx3_out1_ep: endpoint {
+ remote-endpoint = <&adx3_out1_ep>;
+ };
+ };
+
+ port@4c {
+ reg = <0x4c>;
+
+ xbar_adx3_out2_ep: endpoint {
+ remote-endpoint = <&adx3_out2_ep>;
+ };
+ };
+
+ port@4d {
+ reg = <0x4d>;
+
+ xbar_adx3_out3_ep: endpoint {
+ remote-endpoint = <&adx3_out3_ep>;
+ };
+ };
+
+ port@4e {
+ reg = <0x4e>;
+
+ xbar_adx3_out4_ep: endpoint {
+ remote-endpoint = <&adx3_out4_ep>;
+ };
+ };
+
+ xbar_adx4_in_port: port@4f {
+ reg = <0x4f>;
+
+ xbar_adx4_in_ep: endpoint {
+ remote-endpoint = <&adx4_in_ep>;
+ };
+ };
+
+ port@50 {
+ reg = <0x50>;
+
+ xbar_adx4_out1_ep: endpoint {
+ remote-endpoint = <&adx4_out1_ep>;
+ };
+ };
+
+ port@51 {
+ reg = <0x51>;
+
+ xbar_adx4_out2_ep: endpoint {
+ remote-endpoint = <&adx4_out2_ep>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ xbar_adx4_out3_ep: endpoint {
+ remote-endpoint = <&adx4_out3_ep>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ xbar_adx4_out4_ep: endpoint {
+ remote-endpoint = <&adx4_out4_ep>;
+ };
+ };
+
+ xbar_mixer_in1_port: port@54 {
+ reg = <0x54>;
+
+ xbar_mixer_in1_ep: endpoint {
+ remote-endpoint = <&mixer_in1_ep>;
+ };
+ };
+
+ xbar_mixer_in2_port: port@55 {
+ reg = <0x55>;
+
+ xbar_mixer_in2_ep: endpoint {
+ remote-endpoint = <&mixer_in2_ep>;
+ };
+ };
+
+ xbar_mixer_in3_port: port@56 {
+ reg = <0x56>;
+
+ xbar_mixer_in3_ep: endpoint {
+ remote-endpoint = <&mixer_in3_ep>;
+ };
+ };
+
+ xbar_mixer_in4_port: port@57 {
+ reg = <0x57>;
+
+ xbar_mixer_in4_ep: endpoint {
+ remote-endpoint = <&mixer_in4_ep>;
+ };
+ };
+
+ xbar_mixer_in5_port: port@58 {
+ reg = <0x58>;
+
+ xbar_mixer_in5_ep: endpoint {
+ remote-endpoint = <&mixer_in5_ep>;
+ };
+ };
+
+ xbar_mixer_in6_port: port@59 {
+ reg = <0x59>;
+
+ xbar_mixer_in6_ep: endpoint {
+ remote-endpoint = <&mixer_in6_ep>;
+ };
+ };
+
+ xbar_mixer_in7_port: port@5a {
+ reg = <0x5a>;
+
+ xbar_mixer_in7_ep: endpoint {
+ remote-endpoint = <&mixer_in7_ep>;
+ };
+ };
+
+ xbar_mixer_in8_port: port@5b {
+ reg = <0x5b>;
+
+ xbar_mixer_in8_ep: endpoint {
+ remote-endpoint = <&mixer_in8_ep>;
+ };
+ };
+
+ xbar_mixer_in9_port: port@5c {
+ reg = <0x5c>;
+
+ xbar_mixer_in9_ep: endpoint {
+ remote-endpoint = <&mixer_in9_ep>;
+ };
+ };
+
+ xbar_mixer_in10_port: port@5d {
+ reg = <0x5d>;
+
+ xbar_mixer_in10_ep: endpoint {
+ remote-endpoint = <&mixer_in10_ep>;
+ };
+ };
+
+ port@5e {
+ reg = <0x5e>;
+
+ xbar_mixer_out1_ep: endpoint {
+ remote-endpoint = <&mixer_out1_ep>;
+ };
+ };
+
+ port@5f {
+ reg = <0x5f>;
+
+ xbar_mixer_out2_ep: endpoint {
+ remote-endpoint = <&mixer_out2_ep>;
+ };
+ };
+
+ port@60 {
+ reg = <0x60>;
+
+ xbar_mixer_out3_ep: endpoint {
+ remote-endpoint = <&mixer_out3_ep>;
+ };
+ };
+
+ port@61 {
+ reg = <0x61>;
+
+ xbar_mixer_out4_ep: endpoint {
+ remote-endpoint = <&mixer_out4_ep>;
+ };
+ };
+
+ port@62 {
+ reg = <0x62>;
+
+ xbar_mixer_out5_ep: endpoint {
+ remote-endpoint = <&mixer_out5_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s5_ep>;
+ };
+ };
+
+ i2s5_port: port@1 {
+ reg = <1>;
+
+ i2s5_dap_ep: endpoint@0 {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
};
- admaif@290f000 {
+ dmic@2904000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
- admaif0_port: port@0 {
- reg = <0x0>;
+ port@0 {
+ reg = <0>;
- admaif0_ep: endpoint {
- remote-endpoint = <&xbar_admaif0_ep>;
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
};
};
- admaif1_port: port@1 {
- reg = <0x1>;
+ dmic1_port: port@1 {
+ reg = <1>;
- admaif1_ep: endpoint {
- remote-endpoint = <&xbar_admaif1_ep>;
+ dmic1_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif2_port: port@2 {
- reg = <0x2>;
+ dmic@2904100 {
+ status = "okay";
- admaif2_ep: endpoint {
- remote-endpoint = <&xbar_admaif2_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
};
};
- admaif3_port: port@3 {
- reg = <0x3>;
+ dmic2_port: port@1 {
+ reg = <1>;
- admaif3_ep: endpoint {
- remote-endpoint = <&xbar_admaif3_ep>;
+ dmic2_dap_ep: endpoint {
+ /* Place holder for external Codec */
};
};
+ };
+ };
- admaif4_port: port@4 {
- reg = <0x4>;
+ dmic@2904300 {
+ status = "okay";
- admaif4_ep: endpoint {
- remote-endpoint = <&xbar_admaif4_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic4_ep>;
+ };
+ };
+
+ dmic4_port: port@1 {
+ reg = <1>;
+
+ dmic4_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk1_ep>;
+ };
+ };
+
+ dspk1_port: port@1 {
+ reg = <1>;
+
+ dspk1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk2_ep>;
+ };
+ };
+
+ dspk2_port: port@1 {
+ reg = <1>;
+
+ dspk2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ sfc@2902000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_in_ep>;
+ convert-rate = <44100>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_out_ep>;
+ convert-rate = <48000>;
+ };
+ };
+ };
+ };
+
+ sfc@2902200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_in_ep>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_in_ep>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902600 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_in_ep>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@290a000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_in_ep>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@290a200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_in_ep>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@2903000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in1_ep>;
};
};
- admaif5_port: port@5 {
- reg = <0x5>;
+ port@1 {
+ reg = <1>;
- admaif5_ep: endpoint {
- remote-endpoint = <&xbar_admaif5_ep>;
+ amx1_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in2_ep>;
};
};
- admaif6_port: port@6 {
- reg = <0x6>;
+ port@2 {
+ reg = <2>;
- admaif6_ep: endpoint {
- remote-endpoint = <&xbar_admaif6_ep>;
+ amx1_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in3_ep>;
};
};
- admaif7_port: port@7 {
- reg = <0x7>;
+ port@3 {
+ reg = <3>;
- admaif7_ep: endpoint {
- remote-endpoint = <&xbar_admaif7_ep>;
+ amx1_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in4_ep>;
};
};
- admaif8_port: port@8 {
- reg = <0x8>;
+ amx1_out_port: port@4 {
+ reg = <4>;
- admaif8_ep: endpoint {
- remote-endpoint = <&xbar_admaif8_ep>;
+ amx1_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_out_ep>;
};
};
+ };
+ };
- admaif9_port: port@9 {
- reg = <0x9>;
+ amx@2903100 {
+ status = "okay";
- admaif9_ep: endpoint {
- remote-endpoint = <&xbar_admaif9_ep>;
- };
- };
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- admaif10_port: port@a {
- reg = <0xa>;
+ port@0 {
+ reg = <0>;
- admaif10_ep: endpoint {
- remote-endpoint = <&xbar_admaif10_ep>;
+ amx2_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in1_ep>;
};
};
- admaif11_port: port@b {
- reg = <0xb>;
+ port@1 {
+ reg = <1>;
- admaif11_ep: endpoint {
- remote-endpoint = <&xbar_admaif11_ep>;
+ amx2_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in2_ep>;
};
};
- admaif12_port: port@c {
- reg = <0xc>;
+ amx2_in3_port: port@2 {
+ reg = <2>;
- admaif12_ep: endpoint {
- remote-endpoint = <&xbar_admaif12_ep>;
+ amx2_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in3_ep>;
};
};
- admaif13_port: port@d {
- reg = <0xd>;
+ amx2_in4_port: port@3 {
+ reg = <3>;
- admaif13_ep: endpoint {
- remote-endpoint = <&xbar_admaif13_ep>;
+ amx2_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in4_ep>;
};
};
- admaif14_port: port@e {
- reg = <0xe>;
+ amx2_out_port: port@4 {
+ reg = <4>;
- admaif14_ep: endpoint {
- remote-endpoint = <&xbar_admaif14_ep>;
+ amx2_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_out_ep>;
};
};
+ };
+ };
- admaif15_port: port@f {
- reg = <0xf>;
+ amx@2903200 {
+ status = "okay";
- admaif15_ep: endpoint {
- remote-endpoint = <&xbar_admaif15_ep>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx3_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in1_ep>;
};
};
- admaif16_port: port@10 {
- reg = <0x10>;
+ port@1 {
+ reg = <1>;
- admaif16_ep: endpoint {
- remote-endpoint = <&xbar_admaif16_ep>;
+ amx3_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in2_ep>;
};
};
- admaif17_port: port@11 {
- reg = <0x11>;
+ port@2 {
+ reg = <2>;
- admaif17_ep: endpoint {
- remote-endpoint = <&xbar_admaif17_ep>;
+ amx3_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in3_ep>;
};
};
- admaif18_port: port@12 {
- reg = <0x12>;
+ port@3 {
+ reg = <3>;
- admaif18_ep: endpoint {
- remote-endpoint = <&xbar_admaif18_ep>;
+ amx3_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in4_ep>;
};
};
- admaif19_port: port@13 {
- reg = <0x13>;
+ amx3_out_port: port@4 {
+ reg = <4>;
- admaif19_ep: endpoint {
- remote-endpoint = <&xbar_admaif19_ep>;
+ amx3_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_out_ep>;
};
};
};
};
- i2s@2901200 {
+ amx@2903300 {
status = "okay";
ports {
port@0 {
reg = <0>;
- i2s3_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s3_ep>;
+ amx4_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in1_ep>;
};
};
- i2s3_port: port@1 {
+ port@1 {
reg = <1>;
- i2s3_dap_ep: endpoint {
- dai-format = "i2s";
- /* Place holder for external Codec */
+ amx4_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in2_ep>;
};
};
- };
- };
- i2s@2901400 {
- status = "okay";
+ port@2 {
+ reg = <2>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ amx4_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in3_ep>;
+ };
+ };
- port@0 {
- reg = <0>;
+ port@3 {
+ reg = <3>;
- i2s5_cif_ep: endpoint {
- remote-endpoint = <&xbar_i2s5_ep>;
+ amx4_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in4_ep>;
};
};
- i2s5_port: port@1 {
- reg = <1>;
+ amx4_out_port: port@4 {
+ reg = <4>;
- i2s5_dap_ep: endpoint@0 {
- dai-format = "i2s";
- /* Place holder for external Codec */
+ amx4_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_out_ep>;
};
};
};
};
- dmic@2904000 {
+ adx@2903800 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dmic1_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic1_ep>;
+ adx1_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_in_ep>;
};
};
- dmic1_port: port@1 {
+ adx1_out1_port: port@1 {
reg = <1>;
- dmic1_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx1_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out1_ep>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out2_ep>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out3_ep>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out4_ep>;
};
};
};
};
- dmic@2904100 {
+ adx@2903900 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dmic2_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic2_ep>;
+ adx2_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_in_ep>;
};
};
- dmic2_port: port@1 {
+ adx2_out1_port: port@1 {
reg = <1>;
- dmic2_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx2_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out1_ep>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out2_ep>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out3_ep>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out4_ep>;
};
};
};
};
- dmic@2904300 {
+ adx@2903a00 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dmic4_cif_ep: endpoint {
- remote-endpoint = <&xbar_dmic4_ep>;
+ adx3_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_in_ep>;
};
};
- dmic4_port: port@1 {
+ adx3_out1_port: port@1 {
reg = <1>;
- dmic4_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx3_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out1_ep>;
+ };
+ };
+
+ adx3_out2_port: port@2 {
+ reg = <2>;
+
+ adx3_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out2_ep>;
+ };
+ };
+
+ adx3_out3_port: port@3 {
+ reg = <3>;
+
+ adx3_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out3_ep>;
+ };
+ };
+
+ adx3_out4_port: port@4 {
+ reg = <4>;
+
+ adx3_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out4_ep>;
};
};
};
};
- dspk@2905000 {
+ adx@2903b00 {
status = "okay";
ports {
port@0 {
reg = <0>;
- dspk1_cif_ep: endpoint {
- remote-endpoint = <&xbar_dspk1_ep>;
+ adx4_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_in_ep>;
};
};
- dspk1_port: port@1 {
+ adx4_out1_port: port@1 {
reg = <1>;
- dspk1_dap_ep: endpoint {
- /* Place holder for external Codec */
+ adx4_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out1_ep>;
+ };
+ };
+
+ adx4_out2_port: port@2 {
+ reg = <2>;
+
+ adx4_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out2_ep>;
+ };
+ };
+
+ adx4_out3_port: port@3 {
+ reg = <3>;
+
+ adx4_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out3_ep>;
+ };
+ };
+
+ adx4_out4_port: port@4 {
+ reg = <4>;
+
+ adx4_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out4_ep>;
};
};
};
};
- dspk@2905100 {
+ amixer@290bb00 {
status = "okay";
ports {
#size-cells = <0>;
port@0 {
- reg = <0>;
+ reg = <0x0>;
- dspk2_cif_ep: endpoint {
- remote-endpoint = <&xbar_dspk2_ep>;
+ mixer_in1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in1_ep>;
};
};
- dspk2_port: port@1 {
- reg = <1>;
+ port@1 {
+ reg = <0x1>;
- dspk2_dap_ep: endpoint {
- /* Place holder for external Codec */
+ mixer_in2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mixer_in3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mixer_in4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mixer_in5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mixer_in6_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mixer_in7_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in7_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mixer_in8_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in8_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mixer_in9_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in9_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mixer_in10_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in10_ep>;
+ };
+ };
+
+ mixer_out1_port: port@a {
+ reg = <0xa>;
+
+ mixer_out1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out1_ep>;
+ };
+ };
+
+ mixer_out2_port: port@b {
+ reg = <0xb>;
+
+ mixer_out2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out2_ep>;
+ };
+ };
+
+ mixer_out3_port: port@c {
+ reg = <0xc>;
+
+ mixer_out3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out3_ep>;
+ };
+ };
+
+ mixer_out4_port: port@d {
+ reg = <0xd>;
+
+ mixer_out4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out4_ep>;
+ };
+ };
+
+ mixer_out5_port: port@e {
+ reg = <0xe>;
+
+ mixer_out5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out5_ep>;
};
};
};
"p2u-5", "p2u-6", "p2u-7";
};
- pcie_ep@141a0000 {
+ pcie-ep@141a0000 {
status = "disabled";
vddio-pex-ctl-supply = <&vdd_1v8ao>;
<&xbar_i2s3_port>, <&xbar_i2s5_port>,
<&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>,
<&xbar_dspk1_port>, <&xbar_dspk2_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+ <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+ <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+ <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+ <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
+ <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
+ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
+ <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
+ <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&amx3_out_port>, <&amx4_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&adx3_out1_port>, <&adx3_out2_port>,
+ <&adx3_out3_port>, <&adx3_out4_port>,
+ <&adx4_out1_port>, <&adx4_out2_port>,
+ <&adx4_out3_port>, <&adx4_out4_port>,
+ <&mixer_out1_port>, <&mixer_out2_port>,
+ <&mixer_out3_port>, <&mixer_out4_port>,
+ <&mixer_out5_port>,
/* BE I/O Ports */
<&i2s3_port>, <&i2s5_port>,
<&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
reg = <0x2200000 0x10000>,
<0x2210000 0x10000>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
sound-name-prefix = "DSPK2";
status = "disabled";
};
+
+ tegra_sfc1: sfc@2902000 {
+ compatible = "nvidia,tegra194-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902000 0x200>;
+ sound-name-prefix = "SFC1";
+ status = "disabled";
+ };
+
+ tegra_sfc2: sfc@2902200 {
+ compatible = "nvidia,tegra194-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902200 0x200>;
+ sound-name-prefix = "SFC2";
+ status = "disabled";
+ };
+
+ tegra_sfc3: sfc@2902400 {
+ compatible = "nvidia,tegra194-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902400 0x200>;
+ sound-name-prefix = "SFC3";
+ status = "disabled";
+ };
+
+ tegra_sfc4: sfc@2902600 {
+ compatible = "nvidia,tegra194-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902600 0x200>;
+ sound-name-prefix = "SFC4";
+ status = "disabled";
+ };
+
+ tegra_mvc1: mvc@290a000 {
+ compatible = "nvidia,tegra194-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x290a000 0x200>;
+ sound-name-prefix = "MVC1";
+ status = "disabled";
+ };
+
+ tegra_mvc2: mvc@290a200 {
+ compatible = "nvidia,tegra194-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x290a200 0x200>;
+ sound-name-prefix = "MVC2";
+ status = "disabled";
+ };
+
+ tegra_amx1: amx@2903000 {
+ compatible = "nvidia,tegra194-amx";
+ reg = <0x2903000 0x100>;
+ sound-name-prefix = "AMX1";
+ status = "disabled";
+ };
+
+ tegra_amx2: amx@2903100 {
+ compatible = "nvidia,tegra194-amx";
+ reg = <0x2903100 0x100>;
+ sound-name-prefix = "AMX2";
+ status = "disabled";
+ };
+
+ tegra_amx3: amx@2903200 {
+ compatible = "nvidia,tegra194-amx";
+ reg = <0x2903200 0x100>;
+ sound-name-prefix = "AMX3";
+ status = "disabled";
+ };
+
+ tegra_amx4: amx@2903300 {
+ compatible = "nvidia,tegra194-amx";
+ reg = <0x2903300 0x100>;
+ sound-name-prefix = "AMX4";
+ status = "disabled";
+ };
+
+ tegra_adx1: adx@2903800 {
+ compatible = "nvidia,tegra194-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903800 0x100>;
+ sound-name-prefix = "ADX1";
+ status = "disabled";
+ };
+
+ tegra_adx2: adx@2903900 {
+ compatible = "nvidia,tegra194-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903900 0x100>;
+ sound-name-prefix = "ADX2";
+ status = "disabled";
+ };
+
+ tegra_adx3: adx@2903a00 {
+ compatible = "nvidia,tegra194-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903a00 0x100>;
+ sound-name-prefix = "ADX3";
+ status = "disabled";
+ };
+
+ tegra_adx4: adx@2903b00 {
+ compatible = "nvidia,tegra194-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903b00 0x100>;
+ sound-name-prefix = "ADX4";
+ status = "disabled";
+ };
+
+ tegra_amixer: amixer@290bb00 {
+ compatible = "nvidia,tegra194-amixer",
+ "nvidia,tegra210-amixer";
+ reg = <0x290bb00 0x800>;
+ sound-name-prefix = "MIXER1";
+ status = "disabled";
+ };
};
};
reg-names = "security", "gpio";
reg = <0xc2f0000 0x1000>,
<0xc2f1000 0x1000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA194_SID_HOST1X>;
+ nvdec@15140000 {
+ compatible = "nvidia,tegra194-nvdec";
+ reg = <0x15140000 0x00040000>;
+ clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
+ clock-names = "nvdec";
+ resets = <&bpmp TEGRA194_RESET_NVDEC1>;
+ reset-names = "nvdec";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA194_SID_NVDEC1>;
+ dma-coherent;
+
+ nvidia,host1x-class = <0xf5>;
+ };
+
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
reg = <0x15200000 0x00040000>;
iommus = <&smmu TEGRA194_SID_VIC>;
};
+ nvdec@15480000 {
+ compatible = "nvidia,tegra194-nvdec";
+ reg = <0x15480000 0x00040000>;
+ clocks = <&bpmp TEGRA194_CLK_NVDEC>;
+ clock-names = "nvdec";
+ resets = <&bpmp TEGRA194_RESET_NVDEC>;
+ reset-names = "nvdec";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA194_SID_NVDEC>;
+ dma-coherent;
+
+ nvidia,host1x-class = <0xf0>;
+ };
+
dpaux0: dpaux@155c0000 {
compatible = "nvidia,tegra194-dpaux";
reg = <0x155c0000 0x10000>;
dma-coherent;
};
- pcie_ep@14160000 {
+ pcie-ep@14160000 {
compatible = "nvidia,tegra194-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
dma-coherent;
};
- pcie_ep@14180000 {
+ pcie-ep@14180000 {
compatible = "nvidia,tegra194-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
dma-coherent;
};
- pcie_ep@141a0000 {
+ pcie-ep@141a0000 {
compatible = "nvidia,tegra194-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
};
};
+ sfc@702d2000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_in_ep>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@702d2200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_in_ep>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@702d2400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_in_ep>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@702d2600 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_in_ep>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@702da000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_in_ep>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@702da200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_in_ep>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@702d3000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx1_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in4_ep>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@702d3100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx2_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx2_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in2_ep>;
+ };
+ };
+
+ amx2_in3_port: port@2 {
+ reg = <2>;
+
+ amx2_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in3_ep>;
+ };
+ };
+
+ amx2_in4_port: port@3 {
+ reg = <3>;
+
+ amx2_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in4_ep>;
+ };
+ };
+
+ amx2_out_port: port@4 {
+ reg = <4>;
+
+ amx2_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_out_ep>;
+ };
+ };
+ };
+ };
+
+ adx@702d3800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx1_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_in_ep>;
+ };
+ };
+
+ adx1_out1_port: port@1 {
+ reg = <1>;
+
+ adx1_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out1_ep>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out2_ep>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out3_ep>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out4_ep>;
+ };
+ };
+ };
+ };
+
+ adx@702d3900 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx2_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_in_ep>;
+ };
+ };
+
+ adx2_out1_port: port@1 {
+ reg = <1>;
+
+ adx2_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out1_ep>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out2_ep>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out3_ep>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out4_ep>;
+ };
+ };
+ };
+ };
+
+ amixer@702dbb00 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ mixer_in1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ mixer_in2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mixer_in3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mixer_in4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mixer_in5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mixer_in6_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mixer_in7_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in7_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mixer_in8_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in8_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mixer_in9_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in9_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mixer_in10_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in10_ep>;
+ };
+ };
+
+ mixer_out1_port: port@a {
+ reg = <0xa>;
+
+ mixer_out1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out1_ep>;
+ };
+ };
+
+ mixer_out2_port: port@b {
+ reg = <0xb>;
+
+ mixer_out2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out2_ep>;
+ };
+ };
+
+ mixer_out3_port: port@c {
+ reg = <0xc>;
+
+ mixer_out3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out3_ep>;
+ };
+ };
+
+ mixer_out4_port: port@d {
+ reg = <0xd>;
+
+ mixer_out4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out4_ep>;
+ };
+ };
+
+ mixer_out5_port: port@e {
+ reg = <0xe>;
+
+ mixer_out5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out5_ep>;
+ };
+ };
+ };
+ };
+
ports {
xbar_i2s1_port: port@a {
reg = <0xa>;
remote-endpoint = <&dmic3_cif_ep>;
};
};
+
+ xbar_sfc1_in_port: port@12 {
+ reg = <0x12>;
+
+ xbar_sfc1_in_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_in_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_sfc1_out_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@14 {
+ reg = <0x14>;
+
+ xbar_sfc2_in_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_in_ep>;
+ };
+ };
+
+ port@15 {
+ reg = <0x15>;
+
+ xbar_sfc2_out_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@16 {
+ reg = <0x16>;
+
+ xbar_sfc3_in_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_in_ep>;
+ };
+ };
+
+ port@17 {
+ reg = <0x17>;
+
+ xbar_sfc3_out_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@18 {
+ reg = <0x18>;
+
+ xbar_sfc4_in_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_in_ep>;
+ };
+ };
+
+ port@19 {
+ reg = <0x19>;
+
+ xbar_sfc4_out_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_mvc1_in_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_in_ep>;
+ };
+ };
+
+ port@1b {
+ reg = <0x1b>;
+
+ xbar_mvc1_out_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@1c {
+ reg = <0x1c>;
+
+ xbar_mvc2_in_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_in_ep>;
+ };
+ };
+
+ port@1d {
+ reg = <0x1d>;
+
+ xbar_mvc2_out_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_out_ep>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_amx1_in1_ep: endpoint {
+ remote-endpoint = <&amx1_in1_ep>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_amx1_in2_ep: endpoint {
+ remote-endpoint = <&amx1_in2_ep>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@20 {
+ reg = <0x20>;
+
+ xbar_amx1_in3_ep: endpoint {
+ remote-endpoint = <&amx1_in3_ep>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@21 {
+ reg = <0x21>;
+
+ xbar_amx1_in4_ep: endpoint {
+ remote-endpoint = <&amx1_in4_ep>;
+ };
+ };
+
+ port@22 {
+ reg = <0x22>;
+
+ xbar_amx1_out_ep: endpoint {
+ remote-endpoint = <&amx1_out_ep>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@23 {
+ reg = <0x23>;
+
+ xbar_amx2_in1_ep: endpoint {
+ remote-endpoint = <&amx2_in1_ep>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@24 {
+ reg = <0x24>;
+
+ xbar_amx2_in2_ep: endpoint {
+ remote-endpoint = <&amx2_in2_ep>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@25 {
+ reg = <0x25>;
+
+ xbar_amx2_in3_ep: endpoint {
+ remote-endpoint = <&amx2_in3_ep>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@26 {
+ reg = <0x26>;
+
+ xbar_amx2_in4_ep: endpoint {
+ remote-endpoint = <&amx2_in4_ep>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_amx2_out_ep: endpoint {
+ remote-endpoint = <&amx2_out_ep>;
+ };
+ };
+
+ xbar_adx1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_adx1_in_ep: endpoint {
+ remote-endpoint = <&adx1_in_ep>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_adx1_out1_ep: endpoint {
+ remote-endpoint = <&adx1_out1_ep>;
+ };
+ };
+
+ port@2a {
+ reg = <0x2a>;
+
+ xbar_adx1_out2_ep: endpoint {
+ remote-endpoint = <&adx1_out2_ep>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_adx1_out3_ep: endpoint {
+ remote-endpoint = <&adx1_out3_ep>;
+ };
+ };
+
+ port@2c {
+ reg = <0x2c>;
+
+ xbar_adx1_out4_ep: endpoint {
+ remote-endpoint = <&adx1_out4_ep>;
+ };
+ };
+
+ xbar_adx2_in_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_adx2_in_ep: endpoint {
+ remote-endpoint = <&adx2_in_ep>;
+ };
+ };
+
+ port@2e {
+ reg = <0x2e>;
+
+ xbar_adx2_out1_ep: endpoint {
+ remote-endpoint = <&adx2_out1_ep>;
+ };
+ };
+
+ port@2f {
+ reg = <0x2f>;
+
+ xbar_adx2_out2_ep: endpoint {
+ remote-endpoint = <&adx2_out2_ep>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_adx2_out3_ep: endpoint {
+ remote-endpoint = <&adx2_out3_ep>;
+ };
+ };
+
+ port@31 {
+ reg = <0x31>;
+
+ xbar_adx2_out4_ep: endpoint {
+ remote-endpoint = <&adx2_out4_ep>;
+ };
+ };
+
+ xbar_mixer_in1_port: port@32 {
+ reg = <0x32>;
+
+ xbar_mixer_in1_ep: endpoint {
+ remote-endpoint = <&mixer_in1_ep>;
+ };
+ };
+
+ xbar_mixer_in2_port: port@33 {
+ reg = <0x33>;
+
+ xbar_mixer_in2_ep: endpoint {
+ remote-endpoint = <&mixer_in2_ep>;
+ };
+ };
+
+ xbar_mixer_in3_port: port@34 {
+ reg = <0x34>;
+
+ xbar_mixer_in3_ep: endpoint {
+ remote-endpoint = <&mixer_in3_ep>;
+ };
+ };
+
+ xbar_mixer_in4_port: port@35 {
+ reg = <0x35>;
+
+ xbar_mixer_in4_ep: endpoint {
+ remote-endpoint = <&mixer_in4_ep>;
+ };
+ };
+
+ xbar_mixer_in5_port: port@36 {
+ reg = <0x36>;
+
+ xbar_mixer_in5_ep: endpoint {
+ remote-endpoint = <&mixer_in5_ep>;
+ };
+ };
+
+ xbar_mixer_in6_port: port@37 {
+ reg = <0x37>;
+
+ xbar_mixer_in6_ep: endpoint {
+ remote-endpoint = <&mixer_in6_ep>;
+ };
+ };
+
+ xbar_mixer_in7_port: port@38 {
+ reg = <0x38>;
+
+ xbar_mixer_in7_ep: endpoint {
+ remote-endpoint = <&mixer_in7_ep>;
+ };
+ };
+
+ xbar_mixer_in8_port: port@39 {
+ reg = <0x39>;
+
+ xbar_mixer_in8_ep: endpoint {
+ remote-endpoint = <&mixer_in8_ep>;
+ };
+ };
+
+ xbar_mixer_in9_port: port@3a {
+ reg = <0x3a>;
+
+ xbar_mixer_in9_ep: endpoint {
+ remote-endpoint = <&mixer_in9_ep>;
+ };
+ };
+
+ xbar_mixer_in10_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_mixer_in10_ep: endpoint {
+ remote-endpoint = <&mixer_in10_ep>;
+ };
+ };
+
+ port@3c {
+ reg = <0x3c>;
+
+ xbar_mixer_out1_ep: endpoint {
+ remote-endpoint = <&mixer_out1_ep>;
+ };
+ };
+
+ port@3d {
+ reg = <0x3d>;
+
+ xbar_mixer_out2_ep: endpoint {
+ remote-endpoint = <&mixer_out2_ep>;
+ };
+ };
+
+ port@3e {
+ reg = <0x3e>;
+
+ xbar_mixer_out3_ep: endpoint {
+ remote-endpoint = <&mixer_out3_ep>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_mixer_out4_ep: endpoint {
+ remote-endpoint = <&mixer_out4_ep>;
+ };
+ };
+
+ port@40 {
+ reg = <0x40>;
+
+ xbar_mixer_out5_ep: endpoint {
+ remote-endpoint = <&mixer_out5_ep>;
+ };
+ };
};
};
};
<&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
<&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>,
<&xbar_dmic2_port>, <&xbar_dmic3_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
+ <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
+ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
+ <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
+ <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&mixer_out1_port>, <&mixer_out2_port>,
+ <&mixer_out3_port>, <&mixer_out4_port>,
+ <&mixer_out5_port>,
/* I/O DAP Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
};
};
+ sfc@702d2000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_in_ep>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@702d2200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_in_ep>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@702d2400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_in_ep>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@702d2600 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_in_ep>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@702da000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_in_ep>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@702da200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_in_ep>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@702d3000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx1_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in4_ep>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@702d3100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx2_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx2_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in2_ep>;
+ };
+ };
+
+ amx2_in3_port: port@2 {
+ reg = <2>;
+
+ amx2_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in3_ep>;
+ };
+ };
+
+ amx2_in4_port: port@3 {
+ reg = <3>;
+
+ amx2_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in4_ep>;
+ };
+ };
+
+ amx2_out_port: port@4 {
+ reg = <4>;
+
+ amx2_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_out_ep>;
+ };
+ };
+ };
+ };
+
+ adx@702d3800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx1_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_in_ep>;
+ };
+ };
+
+ adx1_out1_port: port@1 {
+ reg = <1>;
+
+ adx1_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out1_ep>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out2_ep>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out3_ep>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out4_ep>;
+ };
+ };
+ };
+ };
+
+ adx@702d3900 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx2_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_in_ep>;
+ };
+ };
+
+ adx2_out1_port: port@1 {
+ reg = <1>;
+
+ adx2_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out1_ep>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out2_ep>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out3_ep>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out4_ep>;
+ };
+ };
+ };
+ };
+
+ amixer@702dbb00 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ mixer_in1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ mixer_in2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mixer_in3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mixer_in4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mixer_in5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mixer_in6_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mixer_in7_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in7_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mixer_in8_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in8_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mixer_in9_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in9_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mixer_in10_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in10_ep>;
+ };
+ };
+
+ mixer_out1_port: port@a {
+ reg = <0xa>;
+
+ mixer_out1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out1_ep>;
+ };
+ };
+
+ mixer_out2_port: port@b {
+ reg = <0xb>;
+
+ mixer_out2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out2_ep>;
+ };
+ };
+
+ mixer_out3_port: port@c {
+ reg = <0xc>;
+
+ mixer_out3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out3_ep>;
+ };
+ };
+
+ mixer_out4_port: port@d {
+ reg = <0xd>;
+
+ mixer_out4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out4_ep>;
+ };
+ };
+
+ mixer_out5_port: port@e {
+ reg = <0xe>;
+
+ mixer_out5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out5_ep>;
+ };
+ };
+ };
+ };
+
ports {
xbar_i2s3_port: port@c {
reg = <0xc>;
remote-endpoint = <&dmic2_cif_ep>;
};
};
+
+ xbar_sfc1_in_port: port@12 {
+ reg = <0x12>;
+
+ xbar_sfc1_in_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_in_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_sfc1_out_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@14 {
+ reg = <0x14>;
+
+ xbar_sfc2_in_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_in_ep>;
+ };
+ };
+
+ port@15 {
+ reg = <0x15>;
+
+ xbar_sfc2_out_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@16 {
+ reg = <0x16>;
+
+ xbar_sfc3_in_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_in_ep>;
+ };
+ };
+
+ port@17 {
+ reg = <0x17>;
+
+ xbar_sfc3_out_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@18 {
+ reg = <0x18>;
+
+ xbar_sfc4_in_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_in_ep>;
+ };
+ };
+
+ port@19 {
+ reg = <0x19>;
+
+ xbar_sfc4_out_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_mvc1_in_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_in_ep>;
+ };
+ };
+
+ port@1b {
+ reg = <0x1b>;
+
+ xbar_mvc1_out_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@1c {
+ reg = <0x1c>;
+
+ xbar_mvc2_in_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_in_ep>;
+ };
+ };
+
+ port@1d {
+ reg = <0x1d>;
+
+ xbar_mvc2_out_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_out_ep>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_amx1_in1_ep: endpoint {
+ remote-endpoint = <&amx1_in1_ep>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_amx1_in2_ep: endpoint {
+ remote-endpoint = <&amx1_in2_ep>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@20 {
+ reg = <0x20>;
+
+ xbar_amx1_in3_ep: endpoint {
+ remote-endpoint = <&amx1_in3_ep>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@21 {
+ reg = <0x21>;
+
+ xbar_amx1_in4_ep: endpoint {
+ remote-endpoint = <&amx1_in4_ep>;
+ };
+ };
+
+ port@22 {
+ reg = <0x22>;
+
+ xbar_amx1_out_ep: endpoint {
+ remote-endpoint = <&amx1_out_ep>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@23 {
+ reg = <0x23>;
+
+ xbar_amx2_in1_ep: endpoint {
+ remote-endpoint = <&amx2_in1_ep>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@24 {
+ reg = <0x24>;
+
+ xbar_amx2_in2_ep: endpoint {
+ remote-endpoint = <&amx2_in2_ep>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@25 {
+ reg = <0x25>;
+
+ xbar_amx2_in3_ep: endpoint {
+ remote-endpoint = <&amx2_in3_ep>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@26 {
+ reg = <0x26>;
+
+ xbar_amx2_in4_ep: endpoint {
+ remote-endpoint = <&amx2_in4_ep>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_amx2_out_ep: endpoint {
+ remote-endpoint = <&amx2_out_ep>;
+ };
+ };
+
+ xbar_adx1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_adx1_in_ep: endpoint {
+ remote-endpoint = <&adx1_in_ep>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_adx1_out1_ep: endpoint {
+ remote-endpoint = <&adx1_out1_ep>;
+ };
+ };
+
+ port@2a {
+ reg = <0x2a>;
+
+ xbar_adx1_out2_ep: endpoint {
+ remote-endpoint = <&adx1_out2_ep>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_adx1_out3_ep: endpoint {
+ remote-endpoint = <&adx1_out3_ep>;
+ };
+ };
+
+ port@2c {
+ reg = <0x2c>;
+
+ xbar_adx1_out4_ep: endpoint {
+ remote-endpoint = <&adx1_out4_ep>;
+ };
+ };
+
+ xbar_adx2_in_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_adx2_in_ep: endpoint {
+ remote-endpoint = <&adx2_in_ep>;
+ };
+ };
+
+ port@2e {
+ reg = <0x2e>;
+
+ xbar_adx2_out1_ep: endpoint {
+ remote-endpoint = <&adx2_out1_ep>;
+ };
+ };
+
+ port@2f {
+ reg = <0x2f>;
+
+ xbar_adx2_out2_ep: endpoint {
+ remote-endpoint = <&adx2_out2_ep>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_adx2_out3_ep: endpoint {
+ remote-endpoint = <&adx2_out3_ep>;
+ };
+ };
+
+ port@31 {
+ reg = <0x31>;
+
+ xbar_adx2_out4_ep: endpoint {
+ remote-endpoint = <&adx2_out4_ep>;
+ };
+ };
+
+ xbar_mixer_in1_port: port@32 {
+ reg = <0x32>;
+
+ xbar_mixer_in1_ep: endpoint {
+ remote-endpoint = <&mixer_in1_ep>;
+ };
+ };
+
+ xbar_mixer_in2_port: port@33 {
+ reg = <0x33>;
+
+ xbar_mixer_in2_ep: endpoint {
+ remote-endpoint = <&mixer_in2_ep>;
+ };
+ };
+
+ xbar_mixer_in3_port: port@34 {
+ reg = <0x34>;
+
+ xbar_mixer_in3_ep: endpoint {
+ remote-endpoint = <&mixer_in3_ep>;
+ };
+ };
+
+ xbar_mixer_in4_port: port@35 {
+ reg = <0x35>;
+
+ xbar_mixer_in4_ep: endpoint {
+ remote-endpoint = <&mixer_in4_ep>;
+ };
+ };
+
+ xbar_mixer_in5_port: port@36 {
+ reg = <0x36>;
+
+ xbar_mixer_in5_ep: endpoint {
+ remote-endpoint = <&mixer_in5_ep>;
+ };
+ };
+
+ xbar_mixer_in6_port: port@37 {
+ reg = <0x37>;
+
+ xbar_mixer_in6_ep: endpoint {
+ remote-endpoint = <&mixer_in6_ep>;
+ };
+ };
+
+ xbar_mixer_in7_port: port@38 {
+ reg = <0x38>;
+
+ xbar_mixer_in7_ep: endpoint {
+ remote-endpoint = <&mixer_in7_ep>;
+ };
+ };
+
+ xbar_mixer_in8_port: port@39 {
+ reg = <0x39>;
+
+ xbar_mixer_in8_ep: endpoint {
+ remote-endpoint = <&mixer_in8_ep>;
+ };
+ };
+
+ xbar_mixer_in9_port: port@3a {
+ reg = <0x3a>;
+
+ xbar_mixer_in9_ep: endpoint {
+ remote-endpoint = <&mixer_in9_ep>;
+ };
+ };
+
+ xbar_mixer_in10_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_mixer_in10_ep: endpoint {
+ remote-endpoint = <&mixer_in10_ep>;
+ };
+ };
+
+ port@3c {
+ reg = <0x3c>;
+
+ xbar_mixer_out1_ep: endpoint {
+ remote-endpoint = <&mixer_out1_ep>;
+ };
+ };
+
+ port@3d {
+ reg = <0x3d>;
+
+ xbar_mixer_out2_ep: endpoint {
+ remote-endpoint = <&mixer_out2_ep>;
+ };
+ };
+
+ port@3e {
+ reg = <0x3e>;
+
+ xbar_mixer_out3_ep: endpoint {
+ remote-endpoint = <&mixer_out3_ep>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_mixer_out4_ep: endpoint {
+ remote-endpoint = <&mixer_out4_ep>;
+ };
+ };
+
+ port@40 {
+ reg = <0x40>;
+
+ xbar_mixer_out5_ep: endpoint {
+ remote-endpoint = <&mixer_out5_ep>;
+ };
+ };
};
};
};
/* Router */
<&xbar_i2s3_port>, <&xbar_i2s4_port>,
<&xbar_dmic1_port>, <&xbar_dmic2_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
+ <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
+ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
+ <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
+ <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&mixer_out1_port>, <&mixer_out2_port>,
+ <&mixer_out3_port>, <&mixer_out4_port>,
+ <&mixer_out5_port>,
/* I/O DAP Ports */
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;
status = "disabled";
};
+ tegra_sfc1: sfc@702d2000 {
+ compatible = "nvidia,tegra210-sfc";
+ reg = <0x702d2000 0x200>;
+ sound-name-prefix = "SFC1";
+ status = "disabled";
+ };
+
+ tegra_sfc2: sfc@702d2200 {
+ compatible = "nvidia,tegra210-sfc";
+ reg = <0x702d2200 0x200>;
+ sound-name-prefix = "SFC2";
+ status = "disabled";
+ };
+
+ tegra_sfc3: sfc@702d2400 {
+ compatible = "nvidia,tegra210-sfc";
+ reg = <0x702d2400 0x200>;
+ sound-name-prefix = "SFC3";
+ status = "disabled";
+ };
+
+ tegra_sfc4: sfc@702d2600 {
+ compatible = "nvidia,tegra210-sfc";
+ reg = <0x702d2600 0x200>;
+ sound-name-prefix = "SFC4";
+ status = "disabled";
+ };
+
+ tegra_mvc1: mvc@702da000 {
+ compatible = "nvidia,tegra210-mvc";
+ reg = <0x702da000 0x200>;
+ sound-name-prefix = "MVC1";
+ status = "disabled";
+ };
+
+ tegra_mvc2: mvc@702da200 {
+ compatible = "nvidia,tegra210-mvc";
+ reg = <0x702da200 0x200>;
+ sound-name-prefix = "MVC2";
+ status = "disabled";
+ };
+
+ tegra_amx1: amx@702d3000 {
+ compatible = "nvidia,tegra210-amx";
+ reg = <0x702d3000 0x100>;
+ sound-name-prefix = "AMX1";
+ status = "disabled";
+ };
+
+ tegra_amx2: amx@702d3100 {
+ compatible = "nvidia,tegra210-amx";
+ reg = <0x702d3100 0x100>;
+ sound-name-prefix = "AMX2";
+ status = "disabled";
+ };
+
+ tegra_adx1: adx@702d3800 {
+ compatible = "nvidia,tegra210-adx";
+ reg = <0x702d3800 0x100>;
+ sound-name-prefix = "ADX1";
+ status = "disabled";
+ };
+
+ tegra_adx2: adx@702d3900 {
+ compatible = "nvidia,tegra210-adx";
+ reg = <0x702d3900 0x100>;
+ sound-name-prefix = "ADX2";
+ status = "disabled";
+ };
+
+ tegra_amixer: amixer@702dbb00 {
+ compatible = "nvidia,tegra210-amixer";
+ reg = <0x702dbb00 0x800>;
+ sound-name-prefix = "MIXER1";
+ status = "disabled";
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
};
usb@7d000000 {
- compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
};
usb@7d004000 {
- compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
status = "okay";
};
+&mpss {
+ status = "okay";
+
+ firmware-name = "qcom/msm8916/mba.mbn", "qcom/msm8916/modem.mbn";
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
&pronto {
status = "okay";
+
+ firmware-name = "qcom/msm8916/wcnss.mbn";
};
&sdhc_1 {
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
+&wcnss_ctrl {
+ firmware-name = "qcom/msm8916/WCNSS_qcom_wlan_nv.bin";
+};
+
/* Enable CoreSight */
&cti0 { status = "okay"; };
&cti1 { status = "okay"; };
&blsp1_uart2 {
label = "BT-UART";
status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart2_default>;
- pinctrl-1 = <&blsp1_uart2_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
};
};
- blsp1_uart2_default: blsp1_uart2_default {
- mux {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- function = "blsp_uart2";
- };
-
- config {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp1_uart2_sleep: blsp1_uart2_sleep {
- mux {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- function = "gpio";
- };
-
- config {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
hdmi_hpd_active: hdmi_hpd_active {
mux {
pins = "gpio34";
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
- qcom,controlled-remotely = <1>;
+ qcom,controlled-remotely;
qcom,config-pipe-trust-reg = <0>;
};
};
};
+ ssphy_0: ssphy@78000 {
+ compatible = "qcom,ipq6018-qmp-usb3-phy";
+ reg = <0x0 0x78000 0x0 0x1C4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #clock-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: lane@78200 {
+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
+ <0x0 0x00078400 0x0 0x200>, /* Rx */
+ <0x0 0x00078800 0x0 0x1F8>, /* PCS */
+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: qusb@79000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x079000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb3: usb3@8A00000 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x8AF8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "sys_noc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <20000000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8A00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x8A00000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,ref-clock-period-ns = <0x32>;
+ dr_mode = "host";
+ };
+ };
};
wcss: wcss-smp2p {
status = "disabled";
};
- cryptobam: dma@704000 {
+ cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
- qcom,controlled-remotely = <1>;
+ qcom,controlled-remotely;
status = "disabled";
};
#reset-cells = <0x1>;
};
+ spmi_bus: spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0200f000 0x001000>,
+ <0x02400000 0x800000>,
+ <0x02c00000 0x800000>,
+ <0x03800000 0x200000>,
+ <0x0200a000 0x000700>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
- tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>, <&usb1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
- tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
};
};
- // FIXME: Use extcon device provided by charger driver when available
- usb_vbus: usb-vbus {
- compatible = "linux,extcon-usb-gpio";
- vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb_vbus_default>;
- };
-
gpio-keys {
compatible = "gpio-keys";
status = "okay";
accelerometer@10 {
- compatible = "bosch,bmc150_accel";
+ compatible = "bosch,bmc156_accel";
reg = <0x10>;
+ /*
+ * For some reason the interrupt line is usually not connected
+ * to the BMC156. However, there are two pads next to the chip
+ * that can be shorted to make it work if needed.
+ *
+ * interrupt-parent = <&msmgpio>;
+ * interrupts = <116 IRQ_TYPE_EDGE_RISING>;
+ */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_int_default>;
+
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
};
magnetometer@12 {
- compatible = "bosch,bmc150_magn";
+ compatible = "bosch,bmc156_magn";
reg = <0x12>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <113 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&magn_int_default>;
+
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
};
reg = <0x68>;
interrupt-parent = <&msmgpio>;
- interrupts = <23 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <23 IRQ_TYPE_EDGE_RISING>,
+ <22 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&gyro_int_default>;
linux,code = <KEY_VOLUMEDOWN>;
};
+&pm8916_usbin {
+ status = "okay";
+};
+
&pm8916_vib {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "peripheral";
- extcon = <&usb_vbus>;
+ extcon = <&pm8916_usbin>;
};
&usb_hs_phy {
- extcon = <&usb_vbus>;
+ extcon = <&pm8916_usbin>;
};
&smd_rpm_regulators {
};
&msmgpio {
+ accel_int_default: accel-int-default {
+ pins = "gpio116";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
camera_flash_default: camera-flash-default {
pins = "gpio31", "gpio32";
function = "gpio";
};
gyro_int_default: gyro-int-default {
- pins = "gpio23";
+ pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- tp_int_default: tp-int-default {
- pins = "gpio13";
+ magn_int_default: magn-int-default {
+ pins = "gpio113";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- usb_vbus_default: usb-vbus-default {
- pins = "gpio62";
+ tp_int_default: tp-int-default {
+ pins = "gpio13";
function = "gpio";
- bias-pull-up;
+ drive-strength = <2>;
+ bias-disable;
};
};
};
};
- soc: soc {
+ soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
lpass: audio-controller@7708000 {
status = "disabled";
compatible = "qcom,lpass-cpu-apq8016";
+
+ /*
+ * Note: Unlike the name would suggest, the SEC_I2S_CLK
+ * is actually only used by Tertiary MI2S while
+ * Primary/Secondary MI2S both use the PRI_I2S_CLK.
+ */
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
- <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
};
sdhc_1: sdhci@7824000 {
- compatible = "qcom,sdhci-msm-v4";
+ compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem";
};
sdhc_2: sdhci@7864000 {
- compatible = "qcom,sdhci-msm-v4";
+ compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc_mem", "core_mem";
label = "pronto";
- wcnss {
+ wcnss_ctrl: wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ clocks {
+ compatible = "simple-bus";
+
+ divclk1_cdc: divclk1 {
+ compatible = "gpio-gate-clock";
+ clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+ #clock-cells = <0>;
+ enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&divclk1_default>;
+ };
+
+ divclk4: divclk4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "divclk4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&divclk4_pin_a>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ vol_up {
+ label = "Volume Up";
+ gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ dome {
+ label = "Home";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ memory@88800000 {
+ reg = <0x0 0x88800000 0x0 0x1400000>;
+ no-map;
+ };
+
+ /* This platform has all PIL regions offset by 0x1400000 */
+ /delete-node/ mpss@88800000;
+ mpss_region: mpss@89c00000 {
+ reg = <0x0 0x89c00000 0x0 0x6200000>;
+ no-map;
+ };
+
+ /delete-node/ adsp@8ea00000;
+ adsp_region: adsp@8ea00000 {
+ reg = <0x0 0x8fe00000 0x0 0x1b00000>;
+ no-map;
+ };
+
+ /delete-node/ slpi@90b00000;
+ slpi_region: slpi@91900000 {
+ reg = <0x0 0x91900000 0x0 0xa00000>;
+ no-map;
+ };
+
+ /delete-node/ gpu@8f200000;
+ zap_shader_region: gpu@92300000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x92300000 0x0 0x2000>;
+ no-map;
+ };
+
+ /delete-node/ venus@91000000;
+ venus_region: venus@90400000 {
+ reg = <0x0 0x92400000 0x0 0x500000>;
+ no-map;
+ };
+
+ ramoops@92900000 {
+ compatible = "ramoops";
+ reg = <0x0 0x92900000 0x0 0x100000>;
+ no-map;
+
+ record-size = <0x8000>;
+ console-size = <0x80000>;
+ ftrace-size = <0x20000>;
+ pmsg-size = <0x40000>;
+ };
+
+ /delete-node/ rmtfs@86700000;
+ rmtfs@f6c00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0 0xf6c00000 0 0x200000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
+
+ /delete-node/ mba@91500000;
+ mba_region: mba@f6f00000 {
+ reg = <0x0 0xf6f00000 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v2_tp: vdd-3v2-tp {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v2_tp";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ startup-delay-us = <4000>;
+ vin-supply = <&vph_pwr>;
+
+ gpio = <&tlmm 73 0>;
+ enable-active-high;
+ };
+
+ vdd_3v3: rome-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <4000>;
+ vin-supply = <&vph_pwr_bbyp>;
+
+ gpio = <&pm8994_gpios 9 0>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rome_enable_default>;
+
+ /* Required by QCA6174a - vddpe-3v3 */
+ regulator-always-on;
+ };
+
+ /* WL_EN pin defined as a fixed regulator */
+ wlan_en: wlan-en-1-8v {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8994_gpios 8 0>;
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_default>;
+ };
+};
+
+&adsp_pil {
+ status = "okay";
+};
+
+&blsp2_i2c2 {
+ status = "okay";
+ label = "NFC_I2C";
+
+ nfc: pn548@28 {
+ compatible = "nxp,nxp-nci-i2c";
+
+ reg = <0x28>;
+ clock-frequency = <400000>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default>;
+ };
+};
+
+&blsp2_i2c3 {
+ status = "okay";
+ label = "TYPEC_I2C";
+
+ typec: tusb320@47 {
+ compatible = "ti,tusb320";
+ reg = <0x47>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <63 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&blsp2_i2c6 {
+ status = "okay";
+ label = "MSM_TS_I2C";
+};
+
+&blsp1_uart2 {
+ status = "okay";
+ label = "QCA_UART";
+
+ bluetooth: qca6174a {
+ compatible = "qcom,qca6174-bt";
+
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+ clocks = <&divclk4>;
+ };
+};
+
+&dsi0 {
+ status = "okay";
+
+ vdd-supply = <&vreg_l2a_1p25>;
+ vddio-supply = <&vreg_l14a_1p8>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mdss_dsi_default &mdss_te_default>;
+ pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>;
+};
+
+&dsi0_out {
+ status = "okay";
+
+ data-lanes = <0 1 2 3>;
+};
+
+&dsi0_phy {
+ status = "okay";
+
+ vcca-supply = <&vreg_l28a_0p925>;
+};
+
+&gpu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mmcc {
+ vdd-gfx-supply = <&vdd_gfx>;
+};
+
+&pcie0 {
+ status = "okay";
+
+ /* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */
+ vddpe-3v3-supply = <&wlan_en>;
+ vdda-supply = <&vreg_l28a_0p925>;
+
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+};
+
+&pm8994_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&usb3 {
+ status = "okay";
+ extcon = <&typec>;
+
+ qcom,select-utmi-as-pipe-clk;
+
+ dwc3@6a00000 {
+ extcon = <&typec>;
+
+ /* usb3-phy is not used on this device */
+ phys = <&hsusb_phy1>;
+ phy-names = "usb2-phy";
+
+ maximum-speed = "high-speed";
+ snps,is-utmi-l1-suspend;
+ snps,usb2-gadget-lpm-disable;
+ snps,hird-threshold = /bits/ 8 <0>;
+ };
+};
+
+&hsusb_phy1 {
+ status = "okay";
+ extcon = <&typec>;
+
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+};
+
+&ufshc {
+ status = "okay";
+
+ vcc-supply = <&vreg_l20a_2p95>;
+ vccq-supply = <&vreg_l25a_1p2>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+
+ vcc-max-microamp = <600000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <450000>;
+};
+
+&ufsphy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+
+ vdda-phy-max-microamp = <18380>;
+ vdda-pll-max-microamp = <9440>;
+
+ vddp-ref-clk-supply = <&vreg_l25a_1p2>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+};
+
+&venus {
+ status = "okay";
+};
+
+&wcd9335 {
+ clock-names = "mclk", "slimbus";
+ clocks = <&divclk1_cdc>,
+ <&rpmcc RPM_SMD_BB_CLK1>;
+
+ vdd-buck-supply = <&vreg_s4a_1p8>;
+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+ vdd-rx-supply = <&vreg_s4a_1p8>;
+ vdd-tx-supply = <&vreg_s4a_1p8>;
+ vdd-vbat-supply = <&vph_pwr>;
+ vdd-micbias-supply = <&vph_pwr_bbyp>;
+ vdd-io-supply = <&vreg_s4a_1p8>;
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_s7-supply = <&vph_pwr>;
+ vdd_s8-supply = <&vph_pwr>;
+ vdd_s9-supply = <&vph_pwr>;
+ vdd_s10-supply = <&vph_pwr>;
+ vdd_s11-supply = <&vph_pwr>;
+ vdd_s12-supply = <&vph_pwr>;
+ vdd_l1-supply = <&vreg_s1b_1p025>;
+ vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
+ vdd_l3_l11-supply = <&vreg_s3a_1p3>;
+ vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
+ vdd_l5_l7-supply = <&vreg_s5a_2p15>;
+ vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
+ vdd_l8_l16_l30-supply = <&vph_pwr>;
+ vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
+ vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
+ vdd_l14_l15-supply = <&vreg_s5a_2p15>;
+ vdd_l17_l29-supply = <&vph_pwr_bbyp>;
+ vdd_l20_l21-supply = <&vph_pwr_bbyp>;
+ vdd_l25-supply = <&vreg_s3a_1p3>;
+ vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p3: s3 {
+ regulator-name = "vreg_s3a_1p3";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+
+ /* Required by QCA6174a - vdd-core */
+ regulator-always-on;
+ };
+ vreg_s4a_1p8: s4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+
+ /* Required by QCA6174a - vddio */
+ regulator-always-on;
+ };
+ vreg_s5a_2p15: s5 {
+ regulator-name = "vreg_s5a_2p15";
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+ vreg_s7a_0p8: s7 {
+ regulator-name = "vreg_s7a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+ vreg_l1a_1p0: l1 {
+ regulator-name = "vreg_l1a_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ vreg_l2a_1p25: l2 {
+ regulator-name = "vreg_l2a_1p25";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+ vreg_l4a_1p225: l4 {
+ regulator-name = "vreg_l4a_1p225";
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ vreg_l6a_1p8: l6 {
+ regulator-name = "vreg_l6a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l8a_1p8: l8 {
+ regulator-name = "vreg_l8a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l9a_1p8: l9 {
+ regulator-name = "vreg_l9a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l10a_1p8: l10 {
+ regulator-name = "vreg_l10a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l12a_1p8: l12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ };
+ vreg_l13a_2p95: l13 {
+ regulator-name = "vreg_l13a_2p95";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ vreg_l14a_1p8: l14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l15a_1p8: l15 {
+ regulator-name = "vreg_l15a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l16a_2p7: l16 {
+ regulator-name = "vreg_l16a_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+ vreg_l19a_3p3: l19 {
+ regulator-name = "vreg_l19a_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ vreg_l20a_2p95: l20 {
+ regulator-name = "vreg_l20a_2p95";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+ vreg_l21a_2p95: l21 {
+ regulator-name = "vreg_l21a_2p95";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vreg_l23a_2p8: l23 {
+ regulator-name = "vreg_l23a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ vreg_l24a_3p075: l24 {
+ regulator-name = "vreg_l24a_3p075";
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ vreg_l25a_1p2: l25 {
+ regulator-name = "vreg_l25a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ };
+ vreg_l27a_1p2: l27 {
+ regulator-name = "vreg_l27a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ vreg_l28a_0p925: l28 {
+ regulator-name = "vreg_l28a_0p925";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-allow-set-load;
+ };
+ vreg_l30a_1p8: l30 {
+ regulator-name = "vreg_l30a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ /* Required by QCA6174a - vddio-xtal */
+ regulator-always-on;
+ };
+ vreg_l32a_1p8: l32 {
+ regulator-name = "vreg_l32a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_lvs1a_1p8: lvs1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_lvs2a_1p8: lvs2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+
+ pmi8994-regulators {
+ compatible = "qcom,rpm-pmi8994-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_bst_byp-supply = <&vph_pwr>;
+
+ vreg_s1b_1p025: s1 {
+ regulator-name = "vreg_s1b_1p025";
+ regulator-min-microvolt = <1025000>;
+ regulator-max-microvolt = <1025000>;
+ };
+
+ vph_pwr_bbyp: boost-bypass {
+ regulator-name = "vph_pwr_bbyp";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3600000>;
+ };
+ };
+};
+
+&pm8994_spmi_regulators {
+ qcom,saw-reg = <&saw3>;
+ s8 {
+ qcom,saw-slave;
+ };
+ s9 {
+ qcom,saw-slave;
+ };
+ s10 {
+ qcom,saw-slave;
+ };
+ vreg_apc_0p8: s11 {
+ qcom,saw-leader;
+ regulator-name = "vreg_apc_0p8";
+ regulator-min-microvolt = <470000>;
+ regulator-max-microvolt = <1140000>;
+ regulator-max-step-microvolt = <150000>;
+ regulator-always-on;
+ };
+};
+
+&pmi8994_spmi_regulators {
+ vdd_gfx: s2 {
+ regulator-name = "vdd_gfx";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1015000>;
+ regulator-enable-ramp-delay = <500>;
+ };
+};
+
+&pm8994_gpios {
+ wlan_en_default: wlan-en-default {
+ pins = "gpio8";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ power-source = <PM8994_GPIO_S4>;
+ bias-disable;
+ };
+
+ rome_enable_default: rome-enable-default {
+ pins = "gpio9";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-high;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ power-source = <PM8994_GPIO_VPH>;
+ };
+
+ divclk1_default: divclk1_default {
+ pins = "gpio15";
+ function = PMIC_GPIO_FUNC_FUNC1;
+ bias-disable;
+ power-source = <PM8994_GPIO_S4>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ };
+
+ divclk4_pin_a: divclk4 {
+ pins = "gpio18";
+ function = PMIC_GPIO_FUNC_FUNC2;
+ bias-disable;
+ power-source = <PM8994_GPIO_S4>;
+ };
+};
+
+&tlmm {
+ mdss_dsi_default: mdss_dsi_default {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mdss_dsi_sleep: mdss_dsi_sleep {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_te_default: mdss_te_default {
+ pins = "gpio10";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_te_sleep: mdss_te_sleep {
+ pins = "gpio10";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ nfc_default: nfc_default {
+ pins = "gpio12", "gpio21";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Raffaele Tranquillini <raffaele.tranquillini@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8996-xiaomi-common.dtsi"
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+#include <dt-bindings/input/ti-drv260x.h>
+
+/ {
+ model = "Xiaomi Mi 5";
+ compatible = "xiaomi,gemini", "qcom,msm8996";
+ qcom,msm-id = <246 0x30001>;
+ qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>;
+ qcom,board-id = <31 0>;
+
+ clocks {
+ divclk2_haptics: divclk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "divclk2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&divclk2_pin_a>;
+ };
+ };
+};
+
+&adsp_pil {
+ firmware-name = "qcom/msm8996/gemini/adsp.mbn";
+};
+
+&blsp2_i2c3 {
+ haptics: drv2604@5a {
+ compatible = "ti,drv2604";
+ reg = <0x5a>;
+ enable-gpio = <&tlmm 93 0x00>;
+ mode = <DRV260X_LRA_MODE>;
+ library-sel = <DRV260X_LIB_LRA>;
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&vibrator_default>;
+ pinctrl-1 = <&vibrator_sleep>;
+ };
+
+ lp5562@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-gpio = <&pm8994_gpios 7 1>;
+ clock-mode = /bits/8 <2>;
+ label = "button-backlight";
+
+ led@0 {
+ reg = <0>;
+ chan-name = "button-backlight";
+ led-cur = /bits/ 8 <0x32>;
+ max-cur = /bits/ 8 <0xC8>;
+ };
+
+ led@1 {
+ reg = <0>;
+ chan-name = "button-backlight1";
+ led-cur = /bits/ 8 <0x32>;
+ max-cur = /bits/ 8 <0xC8>;
+ };
+ };
+};
+
+&blsp2_i2c6 {
+ synaptics@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
+ vdda-supply = <&vreg_l6a_1p8>;
+ vdd-supply = <&vdd_3v2_tp>;
+ reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-1 = <&touchscreen_sleep>;
+ };
+
+};
+
+&gpu {
+ zap-shader {
+ firmware-name = "qcom/msm8996/gemini/a530_zap.mbn";
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
+&sound {
+ compatible = "qcom,apq8096-sndcard";
+ model = "gemini";
+ audio-routing = "RX_BIAS", "MCLK",
+ "MM_DL1", "MultiMedia1 Playback",
+ "MM_DL2", "MultiMedia2 Playback",
+ "MultiMedia3 Capture", "MM_UL3";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ slim-dai-link {
+ link-name = "SLIM Playback";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_6_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9335 6>;
+ };
+ };
+
+ slimcap-dai-link {
+ link-name = "SLIM Capture";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9335 1>;
+ };
+ };
+};
+
+&venus {
+ firmware-name = "qcom/msm8996/gemini/venus.mbn";
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ vreg_l17a_2p8: l17 {
+ regulator-name = "vreg_l17a_2p8";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+ vreg_l29a_2p7: l29 {
+ regulator-name = "vreg_l29a_2p7";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ };
+};
+
+&pm8994_gpios {
+ gpio-line-names =
+ "NC", /* GPIO_1 */
+ "VOL_UP_N", /* GPIO_2 */
+ "SPKR_ID", /* GPIO_3 */
+ "PWM_HAPTICS", /* GPIO_4 */
+ "INFARED_DRV", /* GPIO_5 */
+ "NC", /* GPIO_6 */
+ "KEYPAD_LED_EN", /* GPIO_7 */
+ "WL_EN", /* GPIO_8 */
+ "3P3_ENABLE", /* GPIO_9 */
+ "FP_ID", /* GPIO_10 */
+ "NC", /* GPIO_11 */
+ "NC", /* GPIO_12 */
+ "NC", /* GPIO_13 */
+ "NC", /* GPIO_14 */
+ "DIVCLK1_CDC", /* GPIO_15 */
+ "DIVCLK2_HAPTICS", /* GPIO_16 */
+ "NC", /* GPIO_17 */
+ "32KHz_CLK_IN", /* GPIO_18 */
+ "BT_EN", /* GPIO_19 */
+ "PMIC_SLB", /* GPIO_20 */
+ "UIM_BATT_ALARM", /* GPIO_21 */
+ "NC"; /* GPIO_22 */
+
+ divclk2_pin_a: divclk2 {
+ pins = "gpio16";
+ function = PMIC_GPIO_FUNC_FUNC2;
+ bias-disable;
+ power-source = <PM8994_GPIO_S4>;
+ };
+};
+
+&pm8994_mpps {
+ gpio-line-names =
+ "NC", /* MPP_1 */
+ "CCI_TIMER1", /* MPP_2 */
+ "PMIC_SLB", /* MPP_3 */
+ "EXT_FET_WLED_PWR_EN_N",/* MPP_4 */
+ "NC", /* MPP_5 */
+ "NC", /* MPP_6 */
+ "NC", /* MPP_7 */
+ "NC"; /* MPP_8 */
+};
+
+&pmi8994_gpios {
+ gpio-line-names =
+ "NC", /* GPIO_1 */
+ "SPKR_PA_RST", /* GPIO_2 */
+ "NC", /* GPIO_3 */
+ "NC", /* GPIO_4 */
+ "NC", /* GPIO_5 */
+ "NC", /* GPIO_6 */
+ "NC", /* GPIO_7 */
+ "NC", /* GPIO_8 */
+ "NC", /* GPIO_9 */
+ "NC"; /* GPIO_10 */
+};
+
+&tlmm {
+ gpio-line-names =
+ "ESE_SPI_MOSI", /* GPIO_0 */
+ "ESE_SPI_MISO", /* GPIO_1 */
+ "ERR_INT_N", /* GPIO_2 */
+ "ESE_SPI_CLK", /* GPIO_3 */
+ "MSM_UART_TX", /* GPIO_4 */
+ "MSM_UART_RX", /* GPIO_5 */
+ "NFC_I2C_SDA", /* GPIO_6 */
+ "NFC_I2C_SCL", /* GPIO_7 */
+ "LCD0_RESET_N", /* GPIO_8 */
+ "NFC_IRQ", /* GPIO_9 */
+ "LCD_TE", /* GPIO_10 */
+ "LCD_ID_DET1", /* GPIO_11 */
+ "NFC_DISABLE", /* GPIO_12 */
+ "CAM_MCLK0", /* GPIO_13 */
+ "NC", /* GPIO_14 */
+ "CAM_MCLK2", /* GPIO_15 */
+ "ESE_PWR_REQ", /* GPIO_16 */
+ "CCI_I2C_SDA0", /* GPIO_17 */
+ "CCI_I2C_SCL0", /* GPIO_18 */
+ "CCI_I2C_SDA1", /* GPIO_19 */
+ "CCI_I2C_SCL1", /* GPIO_20 */
+ "NFC_DWL_REQ", /* GPIO_21 */
+ "CCI_TIMER1", /* GPIO_22 */
+ "WEBCAM1_RESET_N", /* GPIO_23 */
+ "ESE_IRQ", /* GPIO_24 */
+ "NC", /* GPIO_25 */
+ "WEBCAM1_STANDBY", /* GPIO_26 */
+ "NC", /* GPIO_27 */
+ "NC", /* GPIO_28 */
+ "NC", /* GPIO_29 */
+ "CAM1_RST_N", /* GPIO_30 */
+ "NC", /* GPIO_31 */
+ "NC", /* GPIO_32 */
+ "NC", /* GPIO_33 */
+ "FP_DOME_SW", /* GPIO_34 */
+ "PCI_E0_RST_N", /* GPIO_35 */
+ "PCI_E0_CLKREQ_N", /* GPIO_36 */
+ "PCI_E0_WAKE", /* GPIO_37 */
+ "FM_INT_N", /* GPIO_38 */
+ "FM_RESET_N", /* GPIO_39 */
+ "NC", /* GPIO_40 */
+ "QCA_UART_TXD", /* GPIO_41 */
+ "QCA_UART_RXD", /* GPIO_42 */
+ "QCA_UART_CTS", /* GPIO_43 */
+ "QCA_UART_RTS", /* GPIO_44 */
+ "MAWC_UART_TX", /* GPIO_45 */
+ "MAWC_UART_RX", /* GPIO_46 */
+ "NC", /* GPIO_47 */
+ "NC", /* GPIO_48 */
+ "AUDIO_SWITCH_EN", /* GPIO_49 */
+ "FP_SPI_RST", /* GPIO_50 */
+ "TYPEC_I2C_SDA", /* GPIO_51 */
+ "TYPEC_I2C_SCL", /* GPIO_52 */
+ "CODEC_INT2_N", /* GPIO_53 */
+ "CODEC_INT1_N", /* GPIO_54 */
+ "APPS_I2C7_SDA", /* GPIO_55 */
+ "APPS_I2C7_SCL", /* GPIO_56 */
+ "FORCE_USB_BOOT", /* GPIO_57 */
+ "SPKR_I2S_BCK", /* GPIO_58 */
+ "SPKR_I2S_WS", /* GPIO_59 */
+ "SPKR_I2S_DOUT", /* GPIO_60 */
+ "SPKR_I2S_DIN", /* GPIO_61 */
+ "ESE_RSTN", /* GPIO_62 */
+ "TYPEC_INT", /* GPIO_63 */
+ "CODEC_RESET_N", /* GPIO_64 */
+ "PCM_CLK", /* GPIO_65 */
+ "PCM_SYNC", /* GPIO_66 */
+ "PCM_DIN", /* GPIO_67 */
+ "PCM_DOUT", /* GPIO_68 */
+ "HIFI_CLK", /* GPIO_69 */
+ "SLIMBUS_CLK", /* GPIO_70 */
+ "SLIMBUS_DATA0", /* GPIO_71 */
+ "SLIMBUS_DATA1", /* GPIO_72 */
+ "LDO_5V_IN_EN", /* GPIO_73 */
+ "NC", /* GPIO_74 */
+ "FM_I2S_CLK", /* GPIO_75 */
+ "FM_I2S_SYNC", /* GPIO_76 */
+ "FM_I2S_DATA", /* GPIO_77 */
+ "FM_STATUS", /* GPIO_78 */
+ "NC", /* GPIO_79 */
+ "SENSOR_RESET_N", /* GPIO_80 */
+ "FP_SPI_MOSI", /* GPIO_81 */
+ "FP_SPI_MISO", /* GPIO_82 */
+ "FP_SPI_CS_N", /* GPIO_83 */
+ "FP_SPI_CLK", /* GPIO_84 */
+ "NC", /* GPIO_85 */
+ "CAM_VDD_1P05_EN", /* GPIO_86 */
+ "MSM_TS_I2C_SDA", /* GPIO_87 */
+ "MSM_TS_I2C_SCL", /* GPIO_88 */
+ "TS_RESOUT_N", /* GPIO_89 */
+ "ESE_SPI_CS_N", /* GPIO_90 */
+ "NC", /* GPIO_91 */
+ "NC", /* GPIO_92 */
+ "HAPTICS_EN", /* GPIO_93 */
+ "NC", /* GPIO_94 */
+ "NC", /* GPIO_95 */
+ "NC", /* GPIO_96 */
+ "NC", /* GPIO_97 */
+ "GRFC_1", /* GPIO_98 */
+ "NC", /* GPIO_99 */
+ "GRFC_3", /* GPIO_100 */
+ "GRFC_4", /* GPIO_101 */
+ "NC", /* GPIO_102 */
+ "NC", /* GPIO_103 */
+ "GRFC_7", /* GPIO_104 */
+ "UIM2_DATA", /* GPIO_105 */
+ "UIM2_CLK", /* GPIO_106 */
+ "UIM2_RESET", /* GPIO_107 */
+ "UIM2_PRESENT", /* GPIO_108 */
+ "UIM1_DATA", /* GPIO_109 */
+ "UIM1_CLK", /* GPIO_110 */
+ "UIM1_RESET", /* GPIO_111 */
+ "UIM1_PRESENT", /* GPIO_112 */
+ "UIM_BATT_ALARM", /* GPIO_113 */
+ "GRFC_8", /* GPIO_114 */
+ "GRFC_9", /* GPIO_115 */
+ "TX_GTR_THRES", /* GPIO_116 */
+ "ACCEL_INT", /* GPIO_117 */
+ "GYRO_INT", /* GPIO_118 */
+ "COMPASS_INT", /* GPIO_119 */
+ "PROXIMITY_INT_N", /* GPIO_120 */
+ "FP_IRQ", /* GPIO_121 */
+ "NC", /* GPIO_122 */
+ "HALL_INTR2", /* GPIO_123 */
+ "HALL_INTR1", /* GPIO_124 */
+ "TS_INT_N", /* GPIO_125 */
+ "NC", /* GPIO_126 */
+ "GRFC_11", /* GPIO_127 */
+ "NC", /* GPIO_128 */
+ "EXT_GPS_LNA_EN", /* GPIO_129 */
+ "NC", /* GPIO_130 */
+ "NC", /* GPIO_131 */
+ "NC", /* GPIO_132 */
+ "GRFC_14", /* GPIO_133 */
+ "GSM_TX2_PHASE_D", /* GPIO_134 */
+ "NC", /* GPIO_135 */
+ "NC", /* GPIO_136 */
+ "RFFE3_DATA", /* GPIO_137 */
+ "RFFE3_CLK", /* GPIO_138 */
+ "NC", /* GPIO_139 */
+ "NC", /* GPIO_140 */
+ "RFFE5_DATA", /* GPIO_141 */
+ "RFFE5_CLK", /* GPIO_142 */
+ "NC", /* GPIO_143 */
+ "COEX_UART_TX", /* GPIO_144 */
+ "COEX_UART_RX", /* GPIO_145 */
+ "RFFE2_DATA", /* GPIO_146 */
+ "RFFE2_CLK", /* GPIO_147 */
+ "RFFE1_DATA", /* GPIO_148 */
+ "RFFE1_CLK"; /* GPIO_149 */
+
+ touchscreen_default: touchscreen_default {
+ pins = "gpio89", "gpio125";
+ function = "gpio";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ touchscreen_sleep: touchscreen_sleep {
+ pins = "gpio89", "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ vibrator_default: vibrator_default {
+ pins = "gpio93";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ vibrator_sleep: vibrator_sleep {
+ pins = "gpio93";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8996-xiaomi-common.dtsi"
+#include "pmi8996.dtsi"
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+
+/ {
+ model = "Xiaomi Mi Note 2";
+ compatible = "xiaomi,scorpio", "qcom,msm8996";
+ qcom,msm-id = <305 0x10000>;
+ qcom,board-id = <34 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer0: framebuffer@83401000 {
+ compatible = "simple-framebuffer";
+ reg = <0x00 0x83401000 0x00 (1080 * 1920 * 3)>;
+ width = <1080>;
+ height = <1920>;
+ stride = <(1080 * 3)>;
+ format = "r8g8b8";
+
+ /* DSI0 and MDP SMMU clocks */
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MMSS_MMAGIC_AHB_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>,
+ <&mmcc SMMU_MDP_AXI_CLK>;
+
+ /* MDSS power domain */
+ power-domains = <&mmcc MDSS_GDSC>;
+ };
+ };
+
+ reserved-memory {
+ cont_splash_mem: memory@83401000 {
+ reg = <0x0 0x83401000 0x0 (1080 * 1920 * 3)>;
+ no-map;
+ };
+ };
+};
+
+&adsp_pil {
+ firmware-name = "qcom/msm8996/scorpio/adsp.mbn";
+};
+
+&blsp2_i2c6 {
+ touchscreen: atmel-mxt-ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
+ vdda-supply = <&vreg_l6a_1p8>;
+ vdd-supply = <&vdd_3v2_tp>;
+ reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-1 = <&touchscreen_sleep>;
+ };
+};
+
+&gpu {
+ zap-shader {
+ firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn";
+ };
+};
+
+&mdp_smmu {
+ /*
+ * Probing this SMMU causes a crash due to writing to some secure
+ * registers. Disable it for now.
+ */
+ status = "disabled";
+};
+
+&mdss {
+ /*
+ * MDSS depends on the MDP SMMU, and probing it alters the bootloader
+ * configured framebuffer used by simplefb. Disable it for now.
+ */
+ status = "disabled";
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
+&sound {
+ compatible = "qcom,apq8096-sndcard";
+ model = "scorpio";
+ audio-routing = "RX_BIAS", "MCLK";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ slim-dai-link {
+ link-name = "SLIM Playback";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_6_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9335 6>;
+ };
+ };
+
+ slimcap-dai-link {
+ link-name = "SLIM Capture";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9335 1>;
+ };
+ };
+};
+
+&venus {
+ firmware-name = "qcom/msm8996/scorpio/venus.mbn";
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ vreg_l3a_0p875: l3 {
+ regulator-name = "vreg_l3a_0p875";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ vreg_l11a_1p1: l11 {
+ regulator-name = "vreg_l11a_1p1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+ vreg_l17a_2p8: l17 {
+ regulator-name = "vreg_l17a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ vreg_l18a_2p8: l18 {
+ regulator-name = "vreg_l18a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ vreg_l22a_3p0: l22 {
+ regulator-name = "vreg_l22a_3p0";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ vreg_l29a_2p7: l29 {
+ regulator-name = "vreg_l29a_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+ };
+};
+
+&vdd_gfx {
+ regulator-max-microvolt = <1065000>;
+};
+
+&pm8994_gpios {
+ gpio-line-names =
+ "NC", /* GPIO_1 */
+ "VOL_UP_N", /* GPIO_2 */
+ "SPKR_ID", /* GPIO_3 */
+ "PWM_HAPTICS", /* GPIO_4 */
+ "INFARED_DRV", /* GPIO_5 */
+ "NC", /* GPIO_6 */
+ "KEYPAD_LED_EN_A", /* GPIO_7 */
+ "WL_EN", /* GPIO_8 */
+ "3P3_ENABLE", /* GPIO_9 */
+ "KEYPAD_LED_EN_B", /* GPIO_10 */
+ "FP_ID", /* GPIO_11 */
+ "NC", /* GPIO_12 */
+ "NC", /* GPIO_13 */
+ "NC", /* GPIO_14 */
+ "DIVCLK1_CDC", /* GPIO_15 */
+ "DIVCLK2_HAPTICS", /* GPIO_16 */
+ "NC", /* GPIO_17 */
+ "32KHz_CLK_IN", /* GPIO_18 */
+ "BT_EN", /* GPIO_19 */
+ "PMIC_SLB", /* GPIO_20 */
+ "UIM_BATT_ALARM", /* GPIO_21 */
+ "NC"; /* GPIO_22 */
+};
+
+&pm8994_mpps {
+ gpio-line-names =
+ "VREF_SDC_UIM_APC", /* MPP_1 */
+ "NC", /* MPP_2 */
+ "VREF_DACX", /* MPP_3 */
+ "NC", /* MPP_4 */
+ "NC", /* MPP_5 */
+ "STAT_SMB1351", /* MPP_6 */
+ "NC", /* MPP_7 */
+ "NC"; /* MPP_8 */
+};
+
+&pmi8994_gpios {
+ gpio-line-names =
+ "NC", /* GPIO_1 */
+ "SPKR_PA_RST", /* GPIO_2 */
+ "NC", /* GPIO_3 */
+ "NC", /* GPIO_4 */
+ "NC", /* GPIO_5 */
+ "NC", /* GPIO_6 */
+ "NC", /* GPIO_7 */
+ "NC", /* GPIO_8 */
+ "NC", /* GPIO_9 */
+ "NC"; /* GPIO_10 */
+};
+
+&tlmm {
+ gpio-line-names =
+ "ESE_SPI_MOSI", /* GPIO_0 */
+ "ESE_SPI_MISO", /* GPIO_1 */
+ "NC", /* GPIO_2 */
+ "ESE_SPI_CLK", /* GPIO_3 */
+ "MSM_UART_TX", /* GPIO_4 */
+ "MSM_UART_RX", /* GPIO_5 */
+ "NFC_I2C_SDA", /* GPIO_6 */
+ "NFC_I2C_SCL", /* GPIO_7 */
+ "OLED_RESET_N", /* GPIO_8 */
+ "NFC_IRQ", /* GPIO_9 */
+ "OLED_TE", /* GPIO_10 */
+ "OLED_ID_DET1", /* GPIO_11 */
+ "NFC_DISABLE", /* GPIO_12 */
+ "CAM_MCLK0", /* GPIO_13 */
+ "OLED_ID_DET2", /* GPIO_14 */
+ "CAM_MCLK2", /* GPIO_15 */
+ "ESE_PWR_REQ", /* GPIO_16 */
+ "CCI_I2C_SDA0", /* GPIO_17 */
+ "CCI_I2C_SCL0", /* GPIO_18 */
+ "CCI_I2C_SDA1", /* GPIO_19 */
+ "CCI_I2C_SCL1", /* GPIO_20 */
+ "NFC_DWL_REQ", /* GPIO_21 */
+ "CCI_TIMER1", /* GPIO_22 */
+ "WEBCAM1_RESET_N", /* GPIO_23 */
+ "ESE_IRQ", /* GPIO_24 */
+ "NC", /* GPIO_25 */
+ "WEBCAM1_STANDBY", /* GPIO_26 */
+ "NC", /* GPIO_27 */
+ "NC", /* GPIO_28 */
+ "OLED_ERR_FG", /* GPIO_29 */
+ "CAM1_RST_N", /* GPIO_30 */
+ "HIFI_SW_MUTE", /* GPIO_31 */
+ "NC", /* GPIO_32 */
+ "NC", /* GPIO_33 */
+ "FP_DOME_SW", /* GPIO_34 */
+ "PCI_E0_RST_N", /* GPIO_35 */
+ "PCI_E0_CLKREQ_N", /* GPIO_36 */
+ "PCI_E0_WAKE", /* GPIO_37 */
+ "OV_PWDN", /* GPIO_38 */
+ "NC", /* GPIO_39 */
+ "VDDR_1P6_EN", /* GPIO_40 */
+ "QCA_UART_TXD", /* GPIO_41 */
+ "QCA_UART_RXD", /* GPIO_42 */
+ "QCA_UART_CTS", /* GPIO_43 */
+ "QCA_UART_RTS", /* GPIO_44 */
+ "MAWC_UART_TX", /* GPIO_45 */
+ "MAWC_UART_RX", /* GPIO_46 */
+ "NC", /* GPIO_47 */
+ "NC", /* GPIO_48 */
+ "AUDIO_SWITCH_EN", /* GPIO_49 */
+ "FP_SPI_RST", /* GPIO_50 */
+ "TYPEC_I2C_SDA", /* GPIO_51 */
+ "TYPEC_I2C_SCL", /* GPIO_52 */
+ "CODEC_INT2_N", /* GPIO_53 */
+ "CODEC_INT1_N", /* GPIO_54 */
+ "APPS_I2C7_SDA", /* GPIO_55 */
+ "APPS_I2C7_SCL", /* GPIO_56 */
+ "FORCE_USB_BOOT", /* GPIO_57 */
+ "SPKR_I2S_BCK", /* GPIO_58 */
+ "SPKR_I2S_WS", /* GPIO_59 */
+ "SPKR_I2S_DOUT", /* GPIO_60 */
+ "SPKR_I2S_DIN", /* GPIO_61 */
+ "ESE_RSTN", /* GPIO_62 */
+ "TYPEC_INT", /* GPIO_63 */
+ "CODEC_RESET_N", /* GPIO_64 */
+ "PCM_CLK", /* GPIO_65 */
+ "PCM_SYNC", /* GPIO_66 */
+ "PCM_DIN", /* GPIO_67 */
+ "PCM_DOUT", /* GPIO_68 */
+ "CDC_44K1_CLK", /* GPIO_69 */
+ "SLIMBUS_CLK", /* GPIO_70 */
+ "SLIMBUS_DATA0", /* GPIO_71 */
+ "SLIMBUS_DATA1", /* GPIO_72 */
+ "LDO_5V_IN_EN", /* GPIO_73 */
+ "NC", /* GPIO_74 */
+ "TSP_RST_N", /* GPIO_75 */
+ "NC", /* GPIO_76 */
+ "TOUCHKEY_INT", /* GPIO_77 */
+ "SPKR_I2S_MCLK", /* GPIO_78 */
+ "SPKR_PA_INT", /* GPIO_79 */
+ "SENSOR_RESET_N", /* GPIO_80 */
+ "FP_SPI_MOSI", /* GPIO_81 */
+ "FP_SPI_MISO", /* GPIO_82 */
+ "FP_SPI_CS_N", /* GPIO_83 */
+ "FP_SPI_CLK", /* GPIO_84 */
+ "HIFI_SD", /* GPIO_85 */
+ "CAM_VDD_1P05_EN", /* GPIO_86 */
+ "MSM_TS_I2C_SDA", /* GPIO_87 */
+ "MSM_TS_I2C_SCL", /* GPIO_88 */
+ "NC", /* GPIO_89 */
+ "ESE_SPI_CS_N", /* GPIO_90 */
+ "NC", /* GPIO_91 */
+ "NC", /* GPIO_92 */
+ "NC", /* GPIO_93 */
+ "NC", /* GPIO_94 */
+ "NC", /* GPIO_95 */
+ "NC", /* GPIO_96 */
+ "GRFC_0", /* GPIO_97 */
+ "GRFC_1", /* GPIO_98 */
+ "NC", /* GPIO_99 */
+ "GRFC_3", /* GPIO_100 */
+ "GRFC_4", /* GPIO_101 */
+ "NC", /* GPIO_102 */
+ "NC", /* GPIO_103 */
+ "GRFC_7", /* GPIO_104 */
+ "UIM2_DATA", /* GPIO_105 */
+ "UIM2_CLK", /* GPIO_106 */
+ "UIM2_RESET", /* GPIO_107 */
+ "UIM2_PRESENT", /* GPIO_108 */
+ "UIM1_DATA", /* GPIO_109 */
+ "UIM1_CLK", /* GPIO_110 */
+ "UIM1_RESET", /* GPIO_111 */
+ "UIM1_PRESENT", /* GPIO_112 */
+ "UIM_BATT_ALARM", /* GPIO_113 */
+ "GRFC_8", /* GPIO_114 */
+ "GRFC_9", /* GPIO_115 */
+ "TX_GTR_THRES", /* GPIO_116 */
+ "ACC_INT", /* GPIO_117 */
+ "GYRO_INT", /* GPIO_118 */
+ "COMPASS_INT", /* GPIO_119 */
+ "PROXIMITY_INT_N", /* GPIO_120 */
+ "FP_IRQ", /* GPIO_121 */
+ "TSP_TA", /* GPIO_122 */
+ "HALL_INTR2", /* GPIO_123 */
+ "HALL_INTR1", /* GPIO_124 */
+ "TS_INT_N", /* GPIO_125 */
+ "NC", /* GPIO_126 */
+ "GRFC_11", /* GPIO_127 */
+ "HIFI_PWR_EN", /* GPIO_128 */
+ "EXT_GPS_LNA_EN", /* GPIO_129 */
+ "NC", /* GPIO_130 */
+ "NC", /* GPIO_131 */
+ "NC", /* GPIO_132 */
+ "GRFC_14", /* GPIO_133 */
+ "GSM_TX2_PHASE_D", /* GPIO_134 */
+ "HIFI_SW_SEL", /* GPIO_135 */
+ "GRFC_15", /* GPIO_136 */
+ "RFFE3_DATA", /* GPIO_137 */
+ "RFFE3_CLK", /* GPIO_138 */
+ "NC", /* GPIO_139 */
+ "NC", /* GPIO_140 */
+ "RFFE5_DATA", /* GPIO_141 */
+ "RFFE5_CLK", /* GPIO_142 */
+ "NC", /* GPIO_143 */
+ "COEX_UART_TX", /* GPIO_144 */
+ "COEX_UART_RX", /* GPIO_145 */
+ "RFFE2_DATA", /* GPIO_146 */
+ "RFFE2_CLK", /* GPIO_147 */
+ "RFFE1_DATA", /* GPIO_148 */
+ "RFFE1_CLK"; /* GPIO_149 */
+
+ touchscreen_default: touchscreen_default {
+ pins = "gpio75", "gpio125";
+ function = "gpio";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ touchscreen_sleep: touchscreen_sleep {
+ pins = "gpio75", "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
};
};
+ blsp1_uart2_default: blsp1-uart2-default {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "blsp_uart2";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_uart2_sleep: blsp1-uart2-sleep {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
blsp1_i2c3_default: blsp1-i2c2-default {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
bias-disable;
};
+ blsp2_i2c3_default: blsp2-i2c3 {
+ pins = "gpio51", "gpio52";
+ function = "blsp_i2c9";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c3_sleep: blsp2-i2c3-sleep {
+ pins = "gpio51", "gpio52";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
wcd_intr_default: wcd-intr-default{
pins = "gpio54";
function = "gpio";
status = "disabled";
};
- blsp1_dma: dma@7544000 {
+ blsp1_dma: dma-controller@7544000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07544000 0x2b000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
dma-names = "tx", "rx";
status = "disabled";
status = "disabled";
};
- blsp2_dma: dma@7584000 {
+ blsp2_dma: dma-controller@7584000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07584000 0x2b000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+ blsp2_i2c3: i2c@75b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x075b7000 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c3_default>;
+ pinctrl-1 = <&blsp2_i2c3_sleep>;
+ dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp2_i2c5: i2c@75b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>;
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "msm8998-mtp.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "F(x)tec Pro1 (QX1000)";
+ compatible = "fxtec,pro1", "qcom,msm8998";
+ qcom,board-id = <0x02000b 0x10>;
+
+ /*
+ * Until we hook up type-c detection, we
+ * have to stick with this. But it works.
+ */
+ extcon_usb: extcon-usb {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-hall-sensors {
+ compatible = "gpio-keys";
+ input-name = "hall-sensors";
+ label = "Hall sensors";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hall_sensor1_default>;
+
+ hall-sensor1 {
+ label = "Keyboard Hall Sensor";
+ gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>;
+ debounce-interval = <15>;
+ gpio-key,wakeup;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_KEYPAD_SLIDE>;
+ };
+ };
+
+ gpio-kb-extra-keys {
+ compatible = "gpio-keys";
+ input-name = "extra-kb-keys";
+ label = "Keyboard extra keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_kb_pins_extra>;
+
+ home {
+ label = "Home";
+ gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ super-l {
+ label = "Super Left";
+ gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_FN>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ super-r {
+ label = "Super Right";
+ gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_FN>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ shift {
+ label = "Shift";
+ gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RIGHTSHIFT>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ ctrl {
+ label = "Ctrl";
+ gpios = <&tlmm 128 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_LEFTCTRL>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ alt {
+ label = "Alt";
+ gpios = <&tlmm 129 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_LEFTALT>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "side-buttons";
+ label = "Side buttons";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_up_pin_a>, <&cam_focus_pin_a>,
+ <&cam_snapshot_pin_a>;
+ vol-up {
+ label = "Volume Up";
+ gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ };
+
+ camera-snapshot {
+ label = "Camera Snapshot";
+ gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_CAMERA>;
+ debounce-interval = <15>;
+ };
+
+ camera-focus {
+ label = "Camera Focus";
+ gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ debounce-interval = <15>;
+ };
+ };
+
+ keyboard-leds {
+ compatible = "gpio-leds";
+
+ backlight {
+ color = <LED_COLOR_ID_WHITE>;
+ default-state = "off";
+ function = LED_FUNCTION_KBD_BACKLIGHT;
+ gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+ label = "white:kbd_backlight";
+ retain-state-suspended;
+ };
+
+ caps-lock {
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ function = LED_FUNCTION_CAPSLOCK;
+ gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ label = "yellow:capslock";
+ linux,default-trigger = "kbd-capslock";
+ };
+ };
+
+ reserved-memory {
+ cont_splash_mem: memory@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x2000000>;
+ no-map;
+ };
+
+ zap_shader_region: memory@f6400000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xf6400000 0x0 0x2000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ console-size = <0x60000>;
+ ecc-size = <16>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x20000>;
+ record-size = <0x10000>;
+ };
+ };
+
+ ts_vio_vreg: ts-vio-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "ts_vio_reg";
+ startup-delay-us = <2>;
+ enable-active-high;
+ gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_vio_default>;
+ regulator-always-on;
+ };
+};
+
+&blsp2_i2c1 {
+ status = "ok";
+
+ touchscreen@14 {
+ compatible = "goodix,gt9286";
+ reg = <0x14>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ AVDD28-supply = <&vreg_l28_3p0>;
+ VDDIO-supply = <&ts_vio_vreg>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&ts_rst_n>, <&ts_int_n>;
+ };
+};
+
+&mmcc {
+ status = "ok";
+};
+
+&mmss_smmu {
+ status = "ok";
+};
+
+&pm8998_gpio {
+ vol_up_pin_a: vol-up-active {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+
+ cam_focus_pin_a: cam-focus-btn-active {
+ pins = "gpio7";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+
+ cam_snapshot_pin_a: cam-snapshot-btn-active {
+ pins = "gpio8";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+};
+
+&pm8998_pon {
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ bias-pull-up;
+ debounce = <15625>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>;
+
+ mdp_vsync_n: mdp-vsync-n {
+ pins = "gpio10";
+ function = "mdp_vsync_a";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ gpio_kb_pins_extra: gpio-kb-pins-extra {
+ pins = "gpio21", "gpio32", "gpio33", "gpio114",
+ "gpio128", "gpio129";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ ts_vio_default: ts-vio-def {
+ pins = "gpio81";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ ts_rst_n: ts-rst-n {
+ pins = "gpio89";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ hall_sensor1_default: hall-sensor1-def {
+ pins = "gpio124";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ input-enable;
+ };
+
+ ts_int_n: ts-int-n {
+ pins = "gpio125";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <8>;
+ };
+};
+
+&ufshc {
+ status = "ok";
+};
+
+&ufsphy {
+ status = "ok";
+};
+
+&usb3_dwc3 {
+ dr_mode = "peripheral";
+ extcon = <&extcon_usb>;
+};
+
+/* GT9286 analog supply */
+&vreg_l28_3p0 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "msm8998-sony-xperia-yoshino.dtsi"
+
+/ {
+ model = "Sony Xperia XZ1 Compact";
+ compatible = "sony,xperia-lilac", "qcom,msm8998";
+};
+
+&ibb {
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+};
+
+&lab {
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ qcom,soft-start-us = <800>;
+};
+
+&vreg_l22a_2p85 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "msm8998-sony-xperia-yoshino.dtsi"
+
+/ {
+ model = "Sony Xperia XZ Premium";
+ compatible = "sony,xperia-maple", "qcom,msm8998";
+
+ disp_dvdd_vreg: disp-dvdd-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "disp_dvdd_en";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ startup-delay-us = <0>;
+ enable-active-high;
+ gpio = <&pmi8998_gpio 10 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_dvdd_en>;
+ };
+};
+
+&ibb {
+ regulator-min-microvolt = <5600000>;
+ regulator-max-microvolt = <5600000>;
+};
+
+&lab {
+ regulator-min-microvolt = <5800000>;
+ regulator-max-microvolt = <5800000>;
+ qcom,soft-start-us = <200>;
+};
+
+&pmi8998_gpio {
+ disp_dvdd_en: disp-dvdd-en-active {
+ pins = "gpio10";
+ function = "normal";
+ bias-disable;
+ drive-push-pull;
+ output-high;
+ power-source = <0>;
+ qcom,drive-strength = <1>;
+ };
+};
+
+&vreg_l22a_2p85 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "msm8998-sony-xperia-yoshino.dtsi"
+
+/ {
+ model = "Sony Xperia XZ1";
+ compatible = "sony,xperia-poplar", "qcom,msm8998";
+};
+
+&ibb {
+ regulator-min-microvolt = <5600000>;
+ regulator-max-microvolt = <5600000>;
+};
+
+&lab {
+ regulator-min-microvolt = <5600000>;
+ regulator-max-microvolt = <5600000>;
+ qcom,soft-start-us = <800>;
+};
+
+&vreg_l18a_2p85 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+};
+
+&vreg_l22a_2p85 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include "msm8998.dtsi"
+#include "pm8005.dtsi"
+#include "pm8998.dtsi"
+#include "pmi8998.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+
+/ {
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */
+ qcom,board-id = <8 0>;
+
+ clocks {
+ compatible = "simple-bus";
+
+ div1_mclk: divclk1 {
+ compatible = "gpio-gate-clock";
+ pinctrl-0 = <&audio_mclk_pin>;
+ pinctrl-names = "default";
+ clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+ #clock-cells = <0>;
+ enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ board_vbat: vbat-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VBAT";
+
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ cam0_vdig_vreg: cam0-vdig {
+ compatible = "regulator-fixed";
+ regulator-name = "cam0_vdig";
+ startup-delay-us = <0>;
+ enable-active-high;
+ gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam0_vdig_default>;
+ };
+
+ cam1_vdig_vreg: cam1-vdig {
+ compatible = "regulator-fixed";
+ regulator-name = "cam1_vdig";
+ startup-delay-us = <0>;
+ enable-active-high;
+ gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam1_vdig_default>;
+ vin-supply = <&vreg_s3a_1p35>;
+ };
+
+ cam_vio_vreg: cam-vio-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_vio_vreg";
+ startup-delay-us = <0>;
+ enable-active-high;
+ gpio = <&pmi8998_gpio 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam_vio_default>;
+ vin-supply = <&vreg_lvs1a_1p8>;
+ };
+
+ touch_vddio_vreg: touch-vddio-vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_vddio_vreg";
+ startup-delay-us = <10000>;
+ gpio = <&tlmm 133 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_vddio_en>;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ label = "Side buttons";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>,
+ <&cam_snapshot_pin_a>;
+ vol-down {
+ label = "Volume Down";
+ gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ };
+
+ camera-snapshot {
+ label = "Camera Snapshot";
+ gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_CAMERA>;
+ debounce-interval = <15>;
+ };
+
+ camera-focus {
+ label = "Camera Focus";
+ gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ debounce-interval = <15>;
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+ input-name = "hall-sensors";
+ label = "Hall sensors";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hall_sensor0_default>;
+
+ hall-sensor0 {
+ label = "Cover Hall Sensor";
+ gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ gpio-key,wakeup;
+ debounce-interval = <30>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@85800000 {
+ reg = <0x0 0x85800000 0x0 0x3700000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x2400000>;
+ no-map;
+ };
+
+ zap_shader_region: memory@f6400000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xf6400000 0x0 0x2000>;
+ no-map;
+ };
+
+ adsp_region: memory@fe000000 {
+ reg = <0x0 0xfe000000 0x0 0x800000>;
+ no-map;
+ };
+
+ qseecom_region: memory@fe800000 {
+ reg = <0x0 0xfe800000 0x0 0x1400000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x10000>;
+ console-size = <0x60000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x20000>;
+ ecc-size = <16>;
+ };
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vib_default>;
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+ clock-frequency = <355000>;
+
+ touchscreen@2c {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x2c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_n>;
+
+ vdd-supply = <&vreg_l28_3p0>;
+ vio-supply = <&touch_vddio_vreg>;
+
+ syna,reset-delay-ms = <220>;
+ syna,startup-delay-ms = <1000>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_i2c5_sleep {
+ bias-disable;
+};
+
+&blsp1_uart3 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3990-bt";
+
+ vddio-supply = <&vreg_s4a_1p8>;
+ vddxo-supply = <&vreg_l7a_1p8>;
+ vddrf-supply = <&vreg_l17a_1p3>;
+ vddch0-supply = <&vreg_l25a_3p3>;
+ max-speed = <3200000>;
+
+ clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
+ };
+};
+
+&blsp2_uart1 {
+ status = "okay";
+};
+
+&ibb {
+ regulator-min-microamp = <800000>;
+ regulator-max-microamp = <800000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-over-current-protection;
+ regulator-pull-down;
+ regulator-ramp-delay = <1>;
+ regulator-settling-time-up-us = <600>;
+ regulator-settling-time-down-us = <1000>;
+ regulator-soft-start;
+ qcom,discharge-resistor-kohms = <300>;
+};
+
+&lab {
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-enable-ramp-delay = <500>;
+ regulator-over-current-protection;
+ regulator-pull-down;
+ regulator-ramp-delay = <1>;
+ regulator-settling-time-up-us = <50000>;
+ regulator-settling-time-down-us = <3000>;
+ regulator-soft-start;
+};
+
+&mmcc {
+ status = "ok";
+};
+
+&mmss_smmu {
+ status = "ok";
+};
+
+&pm8005_lsid1 {
+ pm8005-regulators {
+ compatible = "qcom,pm8005-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+
+ /* VDD_GFX supply */
+ pm8005_s1: s1 {
+ regulator-min-microvolt = <524000>;
+ regulator-max-microvolt = <1088000>;
+ regulator-enable-ramp-delay = <500>;
+ regulator-always-on;
+ };
+ };
+};
+
+&pm8998_gpio {
+ vol_down_pin_a: vol-down-active {
+ pins = "gpio5";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+
+ cam_focus_pin_a: cam-focus-btn-active {
+ pins = "gpio7";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+
+ cam_snapshot_pin_a: cam-snapshot-btn-active {
+ pins = "gpio8";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+
+ audio_mclk_pin: audio-mclk-pin-active {
+ pins = "gpio13";
+ function = "func2";
+ power-source = <0>;
+ };
+};
+
+&pmi8998_gpio {
+ cam_vio_default: cam-vio-active {
+ pins = "gpio1";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-disable;
+ drive-push-pull;
+ output-low;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ power-source = <1>;
+ };
+
+ vib_default: vib-en {
+ pins = "gpio5";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-disable;
+ drive-push-pull;
+ output-low;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <0>;
+ };
+};
+
+&pm8998_pon {
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+};
+
+&qusb2phy {
+ status = "okay";
+
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+};
+
+&rpm_requests {
+ pm8998-regulators {
+ compatible = "qcom,rpm-pm8998-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_s7-supply = <&vph_pwr>;
+ vdd_s8-supply = <&vph_pwr>;
+ vdd_s9-supply = <&vph_pwr>;
+ vdd_s10-supply = <&vph_pwr>;
+ vdd_s11-supply = <&vph_pwr>;
+ vdd_s12-supply = <&vph_pwr>;
+ vdd_s13-supply = <&vph_pwr>;
+ vdd_l1_l27-supply = <&vreg_s7a_1p025>;
+ vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
+ vdd_l3_l11-supply = <&vreg_s7a_1p025>;
+ vdd_l4_l5-supply = <&vreg_s7a_1p025>;
+ vdd_l6-supply = <&vreg_s5a_2p04>;
+ vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
+ vdd_l9-supply = <&vreg_bob>;
+ vdd_l10_l23_l25-supply = <&vreg_bob>;
+ vdd_l13_l19_l21-supply = <&vreg_bob>;
+ vdd_l16_l28-supply = <&vreg_bob>;
+ vdd_l18_l22-supply = <&vreg_bob>;
+ vdd_l20_l24-supply = <&vreg_bob>;
+ vdd_l26-supply = <&vreg_s3a_1p35>;
+ vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p35: s3 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+ vreg_s4a_1p8: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-system-load = <100000>;
+ regulator-allow-set-load;
+ };
+ vreg_s5a_2p04: s5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2032000>;
+ };
+ vreg_s7a_1p025: s7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1028000>;
+ };
+ vreg_l1a_0p875: l1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-system-load = <73400>;
+ regulator-allow-set-load;
+ };
+ vreg_l2a_1p2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-system-load = <12560>;
+ regulator-allow-set-load;
+ };
+ vreg_l3a_1p0: l3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ vreg_l5a_0p8: l5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+ vreg_l6a_1p8: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l7a_1p8: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l8a_1p2: l8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ vreg_l9a_1p8: l9 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ };
+ vreg_l10a_1p8: l10 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ };
+ vreg_l11a_1p0: l11 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ vreg_l12a_1p8: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l13a_2p95: l13 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-allow-set-load;
+ };
+ vreg_l14a_1p85: l14 {
+ regulator-min-microvolt = <1848000>;
+ regulator-max-microvolt = <1856000>;
+ regulator-system-load = <32000>;
+ regulator-allow-set-load;
+ };
+ vreg_l15a_1p8: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l16a_2p7: l16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ };
+ vreg_l17a_1p3: l17 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ };
+ vreg_l18a_2p85: l18 {};
+ vreg_l19a_2p7: l19 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <2704000>;
+ };
+ vreg_l20a_2p95: l20 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-system-load = <10000>;
+ regulator-allow-set-load;
+ };
+ vreg_l21a_2p95: l21 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-system-load = <800000>;
+ regulator-allow-set-load;
+ };
+ vreg_l22a_2p85: l22 { };
+ vreg_l23a_3p3: l23 {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ };
+ vreg_l24a_3p075: l24 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ };
+ vreg_l25a_3p3: l25 {
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3312000>;
+ };
+ vreg_l26a_1p2: l26 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ };
+ vreg_l28_3p0: l28 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ vreg_lvs1a_1p8: lvs1 { };
+ vreg_lvs2a_1p8: lvs2 { };
+ };
+
+ pmi8998-regulators {
+ compatible = "qcom,rpm-pmi8998-regulators";
+
+ vdd_bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ };
+ };
+};
+
+&sdhc2 {
+ status = "okay";
+ cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vreg_l21a_2p95>;
+ vqmmc-supply = <&vreg_l13a_2p95>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <81 4>;
+
+ mdp_vsync_n: mdp-vsync-n {
+ pins = "gpio10";
+ function = "mdp_vsync_a";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ nfc_ven: nfc-ven {
+ pins = "gpio12";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ output-low;
+ };
+
+ msm_mclk0_default: msm-mclk0-active {
+ pins = "gpio13";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ msm_mclk1_default: msm-mclk1-active {
+ pins = "gpio14";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci0_default: cci0-default {
+ pins = "gpio18", "gpio19";
+ function = "cci_i2c";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cci1_default: cci1-default {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cam0_vdig_default: cam0-vdig-default {
+ pins = "gpio21";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cam1_vdig_default: cam1-vdig-default {
+ pins = "gpio25";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ hall_sensor0_default: acc-cover-open {
+ pins = "gpio124";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ input-enable;
+ };
+
+ ts_int_n: ts-int-n {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ ts_vddio_en: ts-vddio-en-default {
+ pins = "gpio133";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ output-low;
+ };
+};
+
+/*
+ * WARNING:
+ * Disable UFS until card quirks are in to avoid unrecoverable hard-brick
+ * that would happen as soon as the UFS card gets probed as, without the
+ * required quirks, the bootloader will be erased right after card probe.
+ */
+&ufshc {
+ status = "disabled";
+};
+
+&ufsphy {
+ status = "disabled";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ /* Force to peripheral until we have Type-C hooked up */
+ dr_mode = "peripheral";
+};
+
+&usb3phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l2a_1p2>;
+};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
+#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
clock-output-names = "xo_board";
};
- sleep_clk {
+ sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-retention";
+ /* CPU Retention (C2D), L2 Active */
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <81>;
exit-latency-us = <86>;
- min-residency-us = <200>;
+ min-residency-us = <504>;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
+ /* CPU + L2 Power Collapse (C3, D4) */
arm,psci-suspend-param = <0x40000003>;
- entry-latency-us = <273>;
- exit-latency-us = <612>;
- min-residency-us = <1000>;
+ entry-latency-us = <814>;
+ exit-latency-us = <4562>;
+ min-residency-us = <9183>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-retention";
+ /* CPU Retention (C2D), L2 Active */
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <79>;
exit-latency-us = <82>;
- min-residency-us = <200>;
+ min-residency-us = <1302>;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
+ /* CPU + L2 Power Collapse (C3, D4) */
arm,psci-suspend-param = <0x40000003>;
- entry-latency-us = <336>;
- exit-latency-us = <525>;
- min-residency-us = <1000>;
+ entry-latency-us = <724>;
+ exit-latency-us = <2027>;
+ min-residency-us = <9419>;
local-timer-stop;
};
};
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00100000 0xb0000>;
+
+ clock-names = "xo", "sleep_clk";
+ clocks = <&xo>, <&sleep_clk>;
};
rpm_msg_ram: memory@778000 {
reg = <0x00778000 0x7000>;
};
- qfprom: qfprom@780000 {
+ qfprom: qfprom@784000 {
compatible = "qcom,qfprom";
- reg = <0x00780000 0x621c>;
+ reg = <0x00784000 0x621c>;
#address-cells = <1>;
#size-cells = <1>;
- qusb2_hstx_trim: hstx-trim@423a {
- reg = <0x423a 0x1>;
+ qusb2_hstx_trim: hstx-trim@23a {
+ reg = <0x23a 0x1>;
bits = <0 4>;
};
};
};
};
+ adreno_gpu: gpu@5000000 {
+ compatible = "qcom,adreno-540.1", "qcom,adreno";
+ reg = <0x05000000 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gpucc RBBMTIMER_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_GPU_BIMC_GFX_CLK>,
+ <&gpucc RBCPR_CLK>,
+ <&gpucc GFX3D_CLK>;
+ clock-names = "iface",
+ "rbbmtimer",
+ "mem",
+ "mem_iface",
+ "rbcpr",
+ "core";
+
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmpd MSM8998_VDDMX>;
+ #stream-id-cells = <16>;
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-710000097 {
+ opp-hz = /bits/ 64 <710000097>;
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-670000048 {
+ opp-hz = /bits/ 64 <670000048>;
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-596000097 {
+ opp-hz = /bits/ 64 <596000097>;
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-515000097 {
+ opp-hz = /bits/ 64 <515000097>;
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-414000000 {
+ opp-hz = /bits/ 64 <414000000>;
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-342000000 {
+ opp-hz = /bits/ 64 <342000000>;
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-257000000 {
+ opp-hz = /bits/ 64 <257000000>;
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ opp-supported-hw = <0xFF>;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@5040000 {
+ compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
+ reg = <0x05040000 0x10000>;
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_GPU_BIMC_GFX_CLK>;
+ clock-names = "iface", "mem", "mem_iface";
+
+ #global-interrupts = <0>;
+ #iommu-cells = <1>;
+ interrupts =
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
+ * GPU-CX for SMMU but we need both of them up for Adreno.
+ * Contemporarily, we also need to manage the VDDMX rpmpd
+ * domain in the Adreno driver.
+ * Enable GPU CX/GX GDSCs here so that we can manage the
+ * SoC VDDMX RPM Power Domain in the Adreno driver.
+ */
+ power-domains = <&gpucc GPU_GX_GDSC>;
+ status = "disabled";
+ };
+
gpucc: clock-controller@5065000 {
compatible = "qcom,msm8998-gpucc";
#clock-cells = <1>;
#size-cells = <0>;
};
- blsp2_dma: dma@c184000 {
+ blsp2_dma: dma-controller@c184000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0c184000 0x25000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
#size-cells = <0>;
};
+ mmcc: clock-controller@c8c0000 {
+ compatible = "qcom,mmcc-msm8998";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xc8c0000 0x40000>;
+ status = "disabled";
+
+ clock-names = "xo",
+ "gpll0",
+ "dsi0dsi",
+ "dsi0byte",
+ "dsi1dsi",
+ "dsi1byte",
+ "hdmipll",
+ "dplink",
+ "dpvco",
+ "core_bi_pll_test_se";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_MMSS_GPLL0_CLK>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ };
+
+ mmss_smmu: iommu@cd00000 {
+ compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
+ reg = <0x0cd00000 0x40000>;
+ #iommu-cells = <1>;
+
+ clocks = <&mmcc MNOC_AHB_CLK>,
+ <&mmcc BIMC_SMMU_AHB_CLK>,
+ <&rpmcc RPM_SMD_MMAXI_CLK>,
+ <&mmcc BIMC_SMMU_AXI_CLK>;
+ clock-names = "iface-mm", "iface-smmu",
+ "bus-mm", "bus-smmu";
+ status = "disabled";
+
+ #global-interrupts = <0>;
+ interrupts =
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
remoteproc_adsp: remoteproc@17300000 {
compatible = "qcom,msm8998-adsp-pas";
reg = <0x17300000 0x4040>;
// SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
};
pon: pon@800 {
- compatible = "qcom,pm8916-pon";
-
+ compatible = "qcom,pm8998-pon";
reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
#size-cells = <0>;
pon: power-on@800 {
- compatible = "qcom,pm8916-pon";
+ compatible = "qcom,pm8998-pon";
reg = <0x0800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
pon_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
};
};
+ pm8916_usbin: extcon@1300 {
+ compatible = "qcom,pm8941-misc";
+ reg = <0x1300>;
+ interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "usb_vbus";
+ status = "disabled";
+ };
+
pm8916_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>;
- reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
interrupt-names = "sc-err", "ocp";
};
};
+
+ pmi8998_wled: leds@d800 {
+ compatible = "qcom,pmi8998-wled";
+ reg = <0xd800 0xd900>;
+ interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ovp", "short";
+ label = "backlight";
+
+ status = "disabled";
+ };
+
};
};
};
};
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
&qupv3_id_0 {
status = "okay";
};
status = "disabled";
};
+&pm6150_adc {
+ status = "disabled";
+
+ /delete-node/ skin-temp-thermistor@4e;
+ /delete-node/ charger-thermistor@4f;
+};
+
+&pm6150_adc_tm {
+ status = "disabled";
+
+ /delete-node/ charger-thermistor@0;
+ /delete-node/ skin-temp-thermistor@1;
+};
+
/*
* CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature,
* which currently is not supported by the PM6150 ADC driver. Disable the
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
- sustainable-power = <814>;
+ sustainable-power = <965>;
trips {
skin_temp_alert0: trip-point0 {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Homestar board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-homestar.dtsi"
+
+/ {
+ model = "Google Homestar (rev2)";
+ compatible = "google,homestar-rev2","google,homestar-rev23", "qcom,sc7180";
+};
+
+&panel {
+ /delete-property/hpd-gpios;
+ no-hpd;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Homestar board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-homestar.dtsi"
+
+/ {
+ model = "Google Homestar (rev3+)";
+ compatible = "google,homestar", "qcom,sc7180";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Homestar board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+#include "sc7180.dtsi"
+
+ap_ec_spi: &spi6 {};
+ap_h1_spi: &spi0 {};
+
+#include "sc7180-trogdor.dtsi"
+
+/ {
+ /* BOARD-SPECIFIC TOP LEVEL NODES */
+
+ max98360a_1: max98360a_1 {
+ compatible = "maxim,max98360a";
+ #sound-dai-cells = <0>;
+ };
+
+ max98360a_2: max98360a_2 {
+ compatible = "maxim,max98360a";
+ #sound-dai-cells = <0>;
+ };
+
+ max98360a_3: max98360a_3 {
+ compatible = "maxim,max98360a";
+ #sound-dai-cells = <0>;
+ };
+
+ pp3300_touch: pp3300-touch {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_touch";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&en_pp3300_touch>;
+
+ vin-supply = <&pp3300_a>;
+ };
+
+ thermal-zones {
+ skin_temp_thermal: skin-temp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6150_adc_tm 1>;
+ sustainable-power = <965>;
+
+ trips {
+ skin_temp_alert0: trip-point0 {
+ temperature = <55000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin_temp_alert1: trip-point1 {
+ temperature = <58000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin-temp-crit {
+ temperature = <73000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&skin_temp_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&skin_temp_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+};
+
+&ap_tp_i2c {
+ status = "disabled";
+};
+
+ap_ts_pen_1v8: &i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ap_ts: touchscreen@14 {
+ compatible = "goodix,gt7375p";
+ reg = <0x14>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&pp3300_touch>;
+ };
+};
+
+/* Panel controls backlight over aux channel */
+
+&backlight {
+ status = "disabled";
+};
+
+&camcc {
+ status = "okay";
+};
+
+&panel {
+ compatible = "samsung,atna33xc20";
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ /delete-property/ backlight;
+};
+
+&pm6150_adc {
+ skin-temp-thermistor@4d {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150_adc_tm {
+ status = "okay";
+
+ skin-temp-thermistor@1 {
+ reg = <1>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pp3300_dx_edp {
+ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+};
+
+&secondary_mi2s {
+ qcom,playback-sd-lines = <0 1>;
+};
+
+&sound_multimedia1_codec {
+ sound-dai = <&max98360a>, <&max98360a_1>, <&max98360a_2>, <&max98360a_3> ;
+};
+
+&wifi {
+ qcom,ath10k-calibration-variant = "GO_HOMESTAR";
+};
+
+/* PINCTRL - modifications to sc7180-trogdor.dtsi */
+
+&en_pp3300_dx_edp {
+ pinmux {
+ pins = "gpio67";
+ };
+
+ pinconf {
+ pins = "gpio67";
+ };
+};
+
+&sec_mi2s_active{
+ pinmux {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "mi2s_1";
+ };
+};
+
+&ts_reset_l {
+ pinconf {
+ /*
+ * We want reset state by default and it will be up to the
+ * driver to disable this when it's ready.
+ */
+ output-low;
+ };
+};
+
+/* PINCTRL - board-specific pinctrl */
+
+&tlmm {
+ gpio-line-names = "HUB_RST_L",
+ "AP_RAM_ID0",
+ "AP_SKU_ID2",
+ "AP_RAM_ID1",
+ "",
+ "AP_RAM_ID2",
+ "UF_CAM_EN",
+ "WF_CAM_EN",
+ "TS_RESET_L",
+ "TS_INT_L",
+ "",
+ "EDP_BRIJ_IRQ",
+ "AP_EDP_BKLTEN",
+ "UF_CAM_MCLK",
+ "WF_CAM_CLK",
+ "EDP_BRIJ_I2C_SDA",
+ "EDP_BRIJ_I2C_SCL",
+ "UF_CAM_SDA",
+ "UF_CAM_SCL",
+ "WF_CAM_SDA",
+ "WF_CAM_SCL",
+ "AVEE_LCD_EN",
+ "",
+ "AMP_EN",
+ "AMP_EN2",
+ "AP_SAR_SENSOR_SDA",
+ "AP_SAR_SENSOR_SCL",
+ "SEL_LCM",
+ "HP_IRQ",
+ "WF_CAM_RST_L",
+ "UF_CAM_RST_L",
+ "AP_BRD_ID2",
+ "BRIJ_SUSPEND",
+ "AP_BRD_ID0",
+ "AP_H1_SPI_MISO",
+ "AP_H1_SPI_MOSI",
+ "AP_H1_SPI_CLK",
+ "AP_H1_SPI_CS_L",
+ "BT_UART_CTS",
+ "BT_UART_RTS",
+ "BT_UART_TXD",
+ "BT_UART_RXD",
+ "H1_AP_INT_ODL",
+ "",
+ "UART_AP_TX_DBG_RX",
+ "UART_DBG_TX_AP_RX",
+ "HP_I2C_SDA",
+ "HP_I2C_SCL",
+ "FORCED_USB_BOOT",
+ "AMP_BCLK",
+ "AMP_LRCLK",
+ "AMP_DIN",
+ "AMP_DIN_2",
+ "HP_BCLK",
+ "HP_LRCLK",
+ "HP_DOUT",
+ "HP_DIN",
+ "HP_MCLK",
+ "AP_SKU_ID0",
+ "AP_EC_SPI_MISO",
+ "AP_EC_SPI_MOSI",
+ "AP_EC_SPI_CLK",
+ "AP_EC_SPI_CS_L",
+ "AP_SPI_CLK",
+ "AP_SPI_MOSI",
+ "AP_SPI_MISO",
+ /*
+ * AP_FLASH_WP_L is crossystem ABI. Schematics
+ * call it BIOS_FLASH_WP_L.
+ */
+ "AP_FLASH_WP_L",
+ "EN_PP3300_DX_EDP",
+ "AP_SPI_CS0_L",
+ "SD_CD_ODL",
+ "",
+ "",
+ "",
+ "WLAN_SW_CTRL",
+ "",
+ "REPORT_E",
+ "VDD_RESET_1.8V",
+ "ID0",
+ "",
+ "ID1",
+ "AVDD_LCD_EN",
+ "MIPI_1.8V_EN",
+ "",
+ "CODEC_PWR_EN",
+ "HUB_EN",
+ "",
+ "PP1800_MIPI_SW_EN",
+ "EN_PP3300_TOUCH",
+ "",
+ "",
+ "AP_SKU_ID1",
+ "AP_RST_REQ",
+ "",
+ "AP_BRD_ID1",
+ "AP_EC_INT_L",
+ "SDM_GRFC_3",
+ "",
+ "",
+ "BOOT_CONFIG_4",
+ "BOOT_CONFIG_2",
+ "",
+ "",
+ "",
+ "",
+ "EDP_BRIJ_EN",
+ "",
+ "",
+ "BOOT_CONFIG_3",
+ "WCI2_LTE_COEX_TXD",
+ "WCI2_LTE_COEX_RXD",
+ "",
+ "",
+ "",
+ "",
+ "FORCED_USB_BOOT_POL",
+ "AP_TS_PEN_I2C_SDA",
+ "AP_TS_PEN_I2C_SCL",
+ "DP_HOT_PLUG_DET",
+ "EC_IN_RW_ODL";
+
+ en_pp3300_touch: en-pp3300-touch {
+ pinmux {
+ pins = "gpio87";
+ function = "gpio";
+ };
+
+ pinconf {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+};
compatible = "boe,nv133fhm-n62";
};
+&pm6150_adc {
+ status = "disabled";
+
+ /delete-node/ charger-thermistor@4f;
+};
+
+&pm6150_adc_tm {
+ status = "disabled";
+
+ /delete-node/ charger-thermistor@0;
+};
+
&trackpad {
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
};
firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn",
"qcom/sc7180-trogdor/modem/qdsp6sw.mbn";
};
+
+&ipa {
+ status = "okay";
+
+ /*
+ * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the
+ * modem needs to cover certain init steps (GSI init), and
+ * the AP needs to wait for it.
+ */
+ modem-init;
+};
status = "disabled";
};
+&pm6150_adc {
+ /delete-node/ charger-thermistor@4f;
+};
+
+&pm6150_adc_tm {
+ /delete-node/ charger-thermistor@0;
+};
+
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
&charger_thermal {
status = "disabled";
};
+
+&pm6150_adc {
+ /delete-node/ charger-thermistor@4f;
+};
+
+&pm6150_adc_tm {
+ /delete-node/ charger-thermistor@0;
+};
};
&cpu6_thermal {
- sustainable-power = <948>;
+ sustainable-power = <1124>;
};
&cpu7_alert0 {
};
&cpu7_thermal {
- sustainable-power = <948>;
+ sustainable-power = <1124>;
};
&cpu8_alert0 {
};
&cpu8_thermal {
- sustainable-power = <948>;
+ sustainable-power = <1124>;
};
&cpu9_alert0 {
};
&cpu9_thermal {
- sustainable-power = <948>;
+ sustainable-power = <1124>;
};
&gpio_keys {
};
};
-&ipa {
- status = "okay";
-
- /*
- * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the
- * modem needs to cover certain init steps (GSI init), and
- * the AP needs to wait for it.
- */
- modem-init;
-};
-
&lpass_cpu {
status = "okay";
pinconf-cmd {
pins = "sdc1_cmd";
bias-pull-up;
- drive-strength = <10>;
+ drive-strength = <16>;
};
pinconf-data {
pins = "sdc1_data";
bias-pull-up;
- drive-strength = <10>;
+ drive-strength = <16>;
};
pinconf-rclk {
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <415>;
+ dynamic-power-coefficient = <137>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <415>;
+ dynamic-power-coefficient = <137>;
next-level-cache = <&L2_100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <415>;
+ dynamic-power-coefficient = <137>;
next-level-cache = <&L2_200>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <415>;
+ dynamic-power-coefficient = <137>;
next-level-cache = <&L2_300>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <415>;
+ dynamic-power-coefficient = <137>;
next-level-cache = <&L2_400>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <415>;
+ dynamic-power-coefficient = <137>;
next-level-cache = <&L2_500>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1740>;
- dynamic-power-coefficient = <405>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <480>;
next-level-cache = <&L2_600>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
- capacity-dmips-mhz = <1740>;
- dynamic-power-coefficient = <405>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <480>;
next-level-cache = <&L2_700>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
clock-names = "iface", "bus", "nav", "snoc_axi",
"mnoc_axi", "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd SC7180_CX>,
+ power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
cell-index = <0>;
};
+ imem@146aa000 {
+ compatible = "simple-mfd";
+ reg = <0 0x146aa000 0 0x2000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146aa000 0x2000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
- sustainable-power = <768>;
+ sustainable-power = <1052>;
trips {
cpu0_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
- sustainable-power = <768>;
+ sustainable-power = <1052>;
trips {
cpu1_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
- sustainable-power = <768>;
+ sustainable-power = <1052>;
trips {
cpu2_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
- sustainable-power = <768>;
+ sustainable-power = <1052>;
trips {
cpu3_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
- sustainable-power = <768>;
+ sustainable-power = <1052>;
trips {
cpu4_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
- sustainable-power = <768>;
+ sustainable-power = <1052>;
trips {
cpu5_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
- sustainable-power = <1202>;
+ sustainable-power = <1425>;
trips {
cpu6_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
- sustainable-power = <1202>;
+ sustainable-power = <1425>;
trips {
cpu7_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
- sustainable-power = <1202>;
+ sustainable-power = <1425>;
trips {
cpu8_alert0: trip-point0 {
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
- sustainable-power = <1202>;
+ sustainable-power = <1425>;
trips {
cpu9_alert0: trip-point0 {
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
+/ {
+ gpio-keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ volume-up {
+ label = "volume_up";
+ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+/*
+ * Reserved memory changes
+ *
+ * Delete all unused memory nodes and define the peripheral memory regions
+ * required by the board dts.
+ *
+ */
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_mem;
+/delete-node/ &reserved_xbl_uefi_log;
+/delete-node/ &sec_apps_mem;
+
+/* Increase the size from 2.5MB to 8MB */
+&rmtfs_mem {
+ reg = <0x0 0x9c900000 0x0 0x800000>;
+};
+
+/ {
+ reserved-memory {
+ adsp_mem: memory@86700000 {
+ reg = <0x0 0x86700000 0x0 0x2800000>;
+ no-map;
+ };
+
+ camera_mem: memory@8ad00000 {
+ reg = <0x0 0x8ad00000 0x0 0x500000>;
+ no-map;
+ };
+
+ venus_mem: memory@8b200000 {
+ reg = <0x0 0x8b200000 0x0 0x500000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ wpss_mem: memory@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ mba_mem: memory@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x200000>;
+ no-map;
+ };
+ };
+};
+
&apps_rsc {
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
};
};
+&qfprom {
+ vcc-supply = <&vreg_l1c_1p8>;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <37500000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ status = "okay";
+ compatible = "qcom,sc7280-mss-pil";
+ iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
+ memory-region = <&mba_mem &mpss_mem>;
+};
+
&sdhc_1 {
status = "okay";
};
&uart5 {
+ compatible = "qcom,geni-debug-uart";
status = "okay";
};
vdda18-supply = <&vreg_l1c_1p8>;
};
+&uart7 {
+ status = "okay";
+
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
+};
+
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
-&qup_uart5_default {
- tx {
- pins = "gpio46";
- drive-strength = <2>;
- bias-disable;
+&pm7325_gpios {
+ key_vol_up_default: key-vol-up-default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ qcom,drive-strength = <3>;
+ };
+};
+
+&qspi_cs0 {
+ bias-disable;
+};
+
+&qspi_clk {
+ bias-disable;
+};
+
+&qspi_data01 {
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
+};
+
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-pull-up;
+};
+
+&qup_uart7_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
+
+&qup_uart7_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
+
+&tlmm {
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
};
- rx {
- pins = "gpio47";
- drive-strength = <2>;
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
bias-pull-up;
};
};
};
sd-cd {
+ pins = "gpio91";
bias-pull-up;
};
};
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
chosen { };
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ spi5 = &spi5;
+ spi6 = &spi6;
+ spi7 = &spi7;
+ spi8 = &spi8;
+ spi9 = &spi9;
+ spi10 = &spi10;
+ spi11 = &spi11;
+ spi12 = &spi12;
+ spi13 = &spi13;
+ spi14 = &spi14;
+ spi15 = &spi15;
};
clocks {
#size-cells = <2>;
ranges;
+ hyp_mem: memory@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: memory@80600000 {
+ reg = <0x0 0x80600000 0x0 0x200000>;
+ no-map;
+ };
+
aop_mem: memory@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
no-map;
};
+ reserved_xbl_uefi_log: memory@80880000 {
+ reg = <0x0 0x80884000 0x0 0x10000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ no-map;
+ };
+
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
+ wlan_fw_mem: memory@80c00000 {
+ reg = <0x0 0x80c00000 0x0 0xc00000>;
+ no-map;
+ };
+
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
+
+ rmtfs_mem: memory@9c900000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x9c900000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
};
cpus {
};
};
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
idle-states {
entry-method = "psci";
method = "smc";
};
+ qspi_opp_table: qspi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
+ qup_opp_table: qup-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
- clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ iommus = <&apps_smmu 0x123 0x0>;
status = "disabled";
- uart5: serial@994000 {
- compatible = "qcom,geni-debug-uart";
- reg = <0 0x00994000 0 0x4000>;
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_default>;
- interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
- };
- cnoc2: interconnect@1500000 {
- reg = <0 0x01500000 0 0x1000>;
- compatible = "qcom,sc7280-cnoc2";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- cnoc3: interconnect@1502000 {
- reg = <0 0x01502000 0 0x1000>;
- compatible = "qcom,sc7280-cnoc3";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- mc_virt: interconnect@1580000 {
- reg = <0 0x01580000 0 0x4>;
- compatible = "qcom,sc7280-mc-virt";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- system_noc: interconnect@1680000 {
- reg = <0 0x01680000 0 0x15480>;
- compatible = "qcom,sc7280-system-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- aggre1_noc: interconnect@16e0000 {
- compatible = "qcom,sc7280-aggre1-noc";
- reg = <0 0x016e0000 0 0x1c080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ uart1: serial@984000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- aggre2_noc: interconnect@1700000 {
- reg = <0 0x01700000 0 0x2b080>;
- compatible = "qcom,sc7280-aggre2-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- mmss_noc: interconnect@1740000 {
- reg = <0 0x01740000 0 0x1e080>;
- compatible = "qcom,sc7280-mmss-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- ipa: ipa@1e40000 {
- compatible = "qcom,sc7280-ipa";
+ uart2: serial@988000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- iommus = <&apps_smmu 0x480 0x0>,
- <&apps_smmu 0x482 0x0>;
- reg = <0 0x1e40000 0 0x8000>,
- <0 0x1e50000 0 0x4ad0>,
- <0 0x1e04000 0 0x23000>;
- reg-names = "ipa-reg",
- "ipa-shared",
- "gsi";
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
- <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
- <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ipa",
- "gsi",
- "ipa-clock-query",
- "ipa-setup-ready";
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- clocks = <&rpmhcc RPMH_IPA_CLK>;
- clock-names = "core";
+ uart3: serial@98c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
- interconnect-names = "memory",
- "config";
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- qcom,smem-states = <&ipa_smp2p_out 0>,
- <&ipa_smp2p_out 1>;
- qcom,smem-state-names = "ipa-clock-enabled-valid",
- "ipa-clock-enabled";
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- status = "disabled";
- };
+ uart4: serial@990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- tcsr_mutex: hwlock@1f40000 {
- compatible = "qcom,tcsr-mutex", "syscon";
- reg = <0 0x01f40000 0 0x40000>;
- #hwlock-cells = <1>;
- };
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00994000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- lpasscc: lpasscc@3000000 {
- compatible = "qcom,sc7280-lpasscc";
- reg = <0 0x03000000 0 0x40>,
- <0 0x03c04000 0 0x4>,
- <0 0x03389000 0 0x24>;
- reg-names = "qdsp6ss", "top_cc", "cc";
- clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
- clock-names = "iface";
- #clock-cells = <1>;
- };
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00994000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- lpass_ag_noc: interconnect@3c40000 {
- reg = <0 0x03c40000 0 0xf080>;
- compatible = "qcom,sc7280-lpass-ag-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ uart5: serial@994000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00994000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- gpucc: clock-controller@3d90000 {
- compatible = "qcom,sc7280-gpucc";
- reg = <0 0x03d90000 0 0x9000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_GPU_GPLL0_CLK_SRC>,
- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
- clock-names = "bi_tcxo",
- "gcc_gpu_gpll0_clk_src",
- "gcc_gpu_gpll0_div_clk_src";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
- stm@6002000 {
- compatible = "arm,coresight-stm", "arm,primecell";
- reg = <0 0x06002000 0 0x1000>,
- <0 0x16280000 0 0x180000>;
- reg-names = "stm-base", "stm-stimulus-base";
-
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
-
- out-ports {
- port {
- stm_out: endpoint {
- remote-endpoint = <&funnel0_in7>;
- };
- };
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
};
- };
- funnel@6041000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0 0x06041000 0 0x1000>;
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- out-ports {
- port {
- funnel0_out: endpoint {
- remote-endpoint = <&merge_funnel_in0>;
- };
- };
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
};
- in-ports {
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- port@7 {
- reg = <7>;
- funnel0_in7: endpoint {
- remote-endpoint = <&stm_out>;
- };
- };
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
};
- funnel@6042000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0 0x06042000 0 0x1000>;
-
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ iommus = <&apps_smmu 0x43 0x0>;
+ status = "disabled";
- out-ports {
- port {
- funnel1_out: endpoint {
- remote-endpoint = <&merge_funnel_in1>;
- };
- };
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
};
- in-ports {
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- port@4 {
- reg = <4>;
- funnel1_in4: endpoint {
- remote-endpoint = <&apss_merge_funnel_out>;
- };
- };
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- };
- funnel@6045000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0 0x06045000 0 0x1000>;
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- out-ports {
- port {
- merge_funnel_out: endpoint {
- remote-endpoint = <&swao_funnel_in>;
- };
- };
+ uart9: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- in-ports {
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- port@0 {
- reg = <0>;
- merge_funnel_in0: endpoint {
- remote-endpoint = <&funnel0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- merge_funnel_in1: endpoint {
- remote-endpoint = <&funnel1_out>;
- };
- };
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- };
- replicator@6046000 {
- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
- reg = <0 0x06046000 0 0x1000>;
+ uart10: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- out-ports {
- port {
- replicator_out: endpoint {
- remote-endpoint = <&etr_in>;
- };
- };
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- in-ports {
- port {
- replicator_in: endpoint {
- remote-endpoint = <&swao_replicator_out>;
- };
- };
+ uart11: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- };
- etr@6048000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0 0x06048000 0 0x1000>;
- iommus = <&apps_smmu 0x04c0 0>;
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,scatter-gather;
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- in-ports {
- port {
- etr_in: endpoint {
- remote-endpoint = <&replicator_out>;
- };
- };
+ uart12: serial@a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- };
- funnel@6b04000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0 0x06b04000 0 0x1000>;
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
- out-ports {
- port {
- swao_funnel_out: endpoint {
- remote-endpoint = <&etf_in>;
- };
- };
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
};
- in-ports {
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart14: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart15: serial@a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+ };
+
+ cnoc2: interconnect@1500000 {
+ reg = <0 0x01500000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc2";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc3: interconnect@1502000 {
+ reg = <0 0x01502000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc3";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect@1580000 {
+ reg = <0 0x01580000 0 0x4>;
+ compatible = "qcom,sc7280-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ reg = <0 0x01680000 0 0x15480>;
+ compatible = "qcom,sc7280-system-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sc7280-aggre1-noc";
+ reg = <0 0x016e0000 0 0x1c080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ reg = <0 0x01700000 0 0x2b080>;
+ compatible = "qcom,sc7280-aggre2-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@1740000 {
+ reg = <0 0x01740000 0 0x1e080>;
+ compatible = "qcom,sc7280-mmss-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ ipa: ipa@1e40000 {
+ compatible = "qcom,sc7280-ipa";
+
+ iommus = <&apps_smmu 0x480 0x0>,
+ <&apps_smmu 0x482 0x0>;
+ reg = <0 0x1e40000 0 0x8000>,
+ <0 0x1e50000 0 0x4ad0>,
+ <0 0x1e04000 0 0x23000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
+ interconnect-names = "memory",
+ "config";
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex", "syscon";
+ reg = <0 0x01f40000 0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sc7280-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ };
+
+ lpasscc: lpasscc@3000000 {
+ compatible = "qcom,sc7280-lpasscc";
+ reg = <0 0x03000000 0 0x40>,
+ <0 0x03c04000 0 0x4>,
+ <0 0x03389000 0 0x24>;
+ reg-names = "qdsp6ss", "top_cc", "cc";
+ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
+ clock-names = "iface";
+ #clock-cells = <1>;
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ reg = <0 0x03c40000 0 0xf080>;
+ compatible = "qcom,sc7280-lpass-ag-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-635.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <1804000>;
+ };
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <6832000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d69000 {
+ compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x3de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc 5>,
+ <&gpucc 8>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc 2>,
+ <&gpucc 15>,
+ <&gpucc 11>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc 0>,
+ <&gpucc 1>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0x400>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc7280-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc 2>,
+ <&gpucc 11>,
+ <&gpucc 5>,
+ <&gpucc 15>,
+ <&gpucc 13>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc 0>;
+ };
+
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sc7280-mpss-pas";
+ reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&rpmhcc RPMH_PKA_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
+
+ power-domains = <&rpmhpd SC7280_CX>,
+ <&rpmhpd SC7280_MSS>;
+ power-domain-names = "cx", "mss";
+
+ memory-region = <&mpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+ <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "mss_restart", "pdc_reset";
+
+ qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
+ qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
+ qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ };
+ };
+
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>,
+ <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint = <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
- swao_funnel_in: endpoint {
- remote-endpoint = <&merge_funnel_out>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
};
};
};
};
- etf@6b05000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0 0x06b05000 0 0x1000>;
+ funnel@6042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06042000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
- etf_out: endpoint {
- remote-endpoint = <&swao_replicator_in>;
+ funnel1_out: endpoint {
+ remote-endpoint = <&merge_funnel_in1>;
};
};
};
in-ports {
- port {
- etf_in: endpoint {
- remote-endpoint = <&swao_funnel_out>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ funnel1_in4: endpoint {
+ remote-endpoint = <&apss_merge_funnel_out>;
};
};
};
};
- replicator@6b06000 {
- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
- reg = <0 0x06b06000 0 0x1000>;
+ funnel@6045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint = <&swao_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint = <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint = <&funnel1_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&swao_replicator_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+ iommus = <&apps_smmu 0x04c0 0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint = <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06b04000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ swao_funnel_out: endpoint {
+ remote-endpoint = <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ swao_funnel_in: endpoint {
+ remote-endpoint = <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etf@6b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06b05000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint = <&swao_replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint = <&swao_funnel_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06b06000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ qcom,replicator-loses-context;
+
+ out-ports {
+ port {
+ swao_replicator_out: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ swao_replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 { /* APSS Funnel */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in4>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
+ status = "disabled";
+
+ reg = <0 0x08804000 0 0x1000>;
+
+ iommus = <&apps_smmu 0x100 0x0>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
+ interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ bus-width = <4>;
+
+ qcom,dll-config = <0x0007642c>;
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000 400000>;
+ opp-avg-kBps = <100000 0>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <200000 0>;
+ };
+ };
+
+ };
+
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sc7280-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e3000 0 0x400>;
+ status = "disabled";
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ };
+
+ usb_2_hsphy: phy@88e4000 {
+ compatible = "qcom,sc7280-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e4000 0 0x400>;
+ status = "disabled";
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ };
+
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sc7280-qmp-usb3-dp-phy",
+ "qcom,sm8250-qmp-usb3-dp-phy";
+ reg = <0 0x088e9000 0 0x200>,
+ <0 0x088e8000 0 0x40>,
+ <0 0x088ea000 0 0x200>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "ref_clk_src", "com_aux";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ usb_1_ssphy: usb3-phy@88e9200 {
+ reg = <0 0x088e9200 0 0x200>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x400>,
+ <0 0x088e9600 0 0x200>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+
+ dp_phy: dp-phy@88ea200 {
+ reg = <0 0x088ea200 0 0x200>,
+ <0 0x088ea400 0 0x200>,
+ <0 0x088eaa00 0 0x200>,
+ <0 0x088ea600 0 0x200>,
+ <0 0x088ea800 0 0x200>;
+ #phy-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
+ usb_2: usb@8cf8800 {
+ compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
+ reg = <0 0x08cf8800 0 0x400>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SEC_SLEEP_CLK>;
+ clock-names = "cfg_noc", "core", "iface","mock_utmi",
+ "sleep";
+
+ assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 13 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 12 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hs_phy_irq",
+ "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+
+ resets = <&gcc GCC_USB30_SEC_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ usb_2_dwc3: usb@8c00000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x08c00000 0 0xe000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0xa0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+ };
+ };
+
+ qspi: spi@88dc000 {
+ compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
+ reg = <0 0x088dc000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+ clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &cnoc2 SLAVE_QSPI_0 0>;
+ interconnect-names = "qspi-config";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
+ status = "disabled";
+ };
+
+ dc_noc: interconnect@90e0000 {
+ reg = <0 0x090e0000 0 0x5080>;
+ compatible = "qcom,sc7280-dc-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9100000 {
+ reg = <0 0x9100000 0 0xe2200>;
+ compatible = "qcom,sc7280-gem-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system-cache-controller@9200000 {
+ compatible = "qcom,sc7280-llcc";
+ reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ nsp_noc: interconnect@a0c0000 {
+ reg = <0 0x0a0c0000 0 0x10000>;
+ compatible = "qcom,sc7280-nsp-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
+ "dm_hs_phy_irq", "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xe000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0xe0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ maximum-speed = "super-speed";
+ };
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sc7280-videocc";
+ reg = <0 0xaaf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sc7280-dispcc";
+ reg = <0 0xaf00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "edp_phy_pll_link_clk",
+ "edp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sc7280-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+ <55 306 4>, <59 312 3>, <62 374 2>,
+ <64 434 2>, <66 438 3>, <69 86 1>,
+ <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ pdc_reset: reset-controller@b5e0000 {
+ compatible = "qcom,sc7280-pdc-global";
+ reg = <0 0x0b5e0000 0 0x20000>;
+ #reset-cells = <1>;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <15>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <12>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- qcom,replicator-loses-context;
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
+ reg = <0 0x0c2a0000 0 0x31000>;
+ #reset-cells = <1>;
+ };
- out-ports {
- port {
- swao_replicator_out: endpoint {
- remote-endpoint = <&replicator_in>;
- };
- };
- };
+ aoss_qmp: power-controller@c300000 {
+ compatible = "qcom,sc7280-aoss-qmp";
+ reg = <0 0x0c300000 0 0x100000>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
- in-ports {
- port {
- swao_replicator_in: endpoint {
- remote-endpoint = <&etf_out>;
- };
- };
- };
+ #clock-cells = <0>;
};
- etm@7040000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07040000 0 0x1000>;
-
- cpu = <&CPU0>;
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c440000 0 0x1100>,
+ <0 0x0c600000 0 0x2000000>,
+ <0 0x0e600000 0 0x100000>,
+ <0 0x0e700000 0 0xa0000>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sc7280-pinctrl";
+ reg = <0 0x0f100000 0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 175>;
+ wakeup-parent = <&pdc>;
- out-ports {
- port {
- etm0_out: endpoint {
- remote-endpoint = <&apss_funnel_in0>;
- };
- };
+ qspi_clk: qspi-clk {
+ pins = "gpio14";
+ function = "qspi_clk";
};
- };
- etm@7140000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07140000 0 0x1000>;
+ qspi_cs0: qspi-cs0 {
+ pins = "gpio15";
+ function = "qspi_cs";
+ };
- cpu = <&CPU1>;
+ qspi_cs1: qspi-cs1 {
+ pins = "gpio19";
+ function = "qspi_cs";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qspi_data01: qspi-data01 {
+ pins = "gpio12", "gpio13";
+ function = "qspi_data";
+ };
- out-ports {
- port {
- etm1_out: endpoint {
- remote-endpoint = <&apss_funnel_in1>;
- };
- };
+ qspi_data12: qspi-data12 {
+ pins = "gpio16", "gpio17";
+ function = "qspi_data";
};
- };
- etm@7240000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07240000 0 0x1000>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ };
- cpu = <&CPU2>;
+ qup_i2c1_data_clk: qup-i2c1-data-clk {
+ pins = "gpio4", "gpio5";
+ function = "qup01";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qup_i2c2_data_clk: qup-i2c2-data-clk {
+ pins = "gpio8", "gpio9";
+ function = "qup02";
+ };
- out-ports {
- port {
- etm2_out: endpoint {
- remote-endpoint = <&apss_funnel_in2>;
- };
- };
+ qup_i2c3_data_clk: qup-i2c3-data-clk {
+ pins = "gpio12", "gpio13";
+ function = "qup03";
};
- };
- etm@7340000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07340000 0 0x1000>;
+ qup_i2c4_data_clk: qup-i2c4-data-clk {
+ pins = "gpio16", "gpio17";
+ function = "qup04";
+ };
- cpu = <&CPU3>;
+ qup_i2c5_data_clk: qup-i2c5-data-clk {
+ pins = "gpio20", "gpio21";
+ function = "qup05";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qup_i2c6_data_clk: qup-i2c6-data-clk {
+ pins = "gpio24", "gpio25";
+ function = "qup06";
+ };
- out-ports {
- port {
- etm3_out: endpoint {
- remote-endpoint = <&apss_funnel_in3>;
- };
- };
+ qup_i2c7_data_clk: qup-i2c7-data-clk {
+ pins = "gpio28", "gpio29";
+ function = "qup07";
};
- };
- etm@7440000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07440000 0 0x1000>;
+ qup_i2c8_data_clk: qup-i2c8-data-clk {
+ pins = "gpio32", "gpio33";
+ function = "qup10";
+ };
- cpu = <&CPU4>;
+ qup_i2c9_data_clk: qup-i2c9-data-clk {
+ pins = "gpio36", "gpio37";
+ function = "qup11";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qup_i2c10_data_clk: qup-i2c10-data-clk {
+ pins = "gpio40", "gpio41";
+ function = "qup12";
+ };
- out-ports {
- port {
- etm4_out: endpoint {
- remote-endpoint = <&apss_funnel_in4>;
- };
- };
+ qup_i2c11_data_clk: qup-i2c11-data-clk {
+ pins = "gpio44", "gpio45";
+ function = "qup13";
};
- };
- etm@7540000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07540000 0 0x1000>;
+ qup_i2c12_data_clk: qup-i2c12-data-clk {
+ pins = "gpio48", "gpio49";
+ function = "qup14";
+ };
- cpu = <&CPU5>;
+ qup_i2c13_data_clk: qup-i2c13-data-clk {
+ pins = "gpio52", "gpio53";
+ function = "qup15";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qup_i2c14_data_clk: qup-i2c14-data-clk {
+ pins = "gpio56", "gpio57";
+ function = "qup16";
+ };
- out-ports {
- port {
- etm5_out: endpoint {
- remote-endpoint = <&apss_funnel_in5>;
- };
- };
+ qup_i2c15_data_clk: qup-i2c15-data-clk {
+ pins = "gpio60", "gpio61";
+ function = "qup17";
};
- };
- etm@7640000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07640000 0 0x1000>;
+ qup_spi0_data_clk: qup-spi0-data-clk {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup00";
+ };
- cpu = <&CPU6>;
+ qup_spi0_cs: qup-spi0-cs {
+ pins = "gpio3";
+ function = "qup00";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio {
+ pins = "gpio3";
+ function = "gpio";
+ };
- out-ports {
- port {
- etm6_out: endpoint {
- remote-endpoint = <&apss_funnel_in6>;
- };
- };
+ qup_spi1_data_clk: qup-spi1-data-clk {
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup01";
};
- };
- etm@7740000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0 0x07740000 0 0x1000>;
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio7";
+ function = "qup01";
+ };
- cpu = <&CPU7>;
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio {
+ pins = "gpio7";
+ function = "gpio";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
- arm,coresight-loses-context-with-cpu;
- qcom,skip-power-up;
+ qup_spi2_data_clk: qup-spi2-data-clk {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup02";
+ };
- out-ports {
- port {
- etm7_out: endpoint {
- remote-endpoint = <&apss_funnel_in7>;
- };
- };
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio11";
+ function = "qup02";
};
- };
- funnel@7800000 { /* APSS Funnel */
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0 0x07800000 0 0x1000>;
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio {
+ pins = "gpio11";
+ function = "gpio";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ qup_spi3_data_clk: qup-spi3-data-clk {
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup03";
+ };
- out-ports {
- port {
- apss_funnel_out: endpoint {
- remote-endpoint = <&apss_merge_funnel_in>;
- };
- };
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio15";
+ function = "qup03";
};
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio {
+ pins = "gpio15";
+ function = "gpio";
+ };
- port@0 {
- reg = <0>;
- apss_funnel_in0: endpoint {
- remote-endpoint = <&etm0_out>;
- };
- };
+ qup_spi4_data_clk: qup-spi4-data-clk {
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup04";
+ };
- port@1 {
- reg = <1>;
- apss_funnel_in1: endpoint {
- remote-endpoint = <&etm1_out>;
- };
- };
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio19";
+ function = "qup04";
+ };
- port@2 {
- reg = <2>;
- apss_funnel_in2: endpoint {
- remote-endpoint = <&etm2_out>;
- };
- };
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio {
+ pins = "gpio19";
+ function = "gpio";
+ };
- port@3 {
- reg = <3>;
- apss_funnel_in3: endpoint {
- remote-endpoint = <&etm3_out>;
- };
- };
+ qup_spi5_data_clk: qup-spi5-data-clk {
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup05";
+ };
- port@4 {
- reg = <4>;
- apss_funnel_in4: endpoint {
- remote-endpoint = <&etm4_out>;
- };
- };
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio23";
+ function = "qup05";
+ };
- port@5 {
- reg = <5>;
- apss_funnel_in5: endpoint {
- remote-endpoint = <&etm5_out>;
- };
- };
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio {
+ pins = "gpio23";
+ function = "gpio";
+ };
- port@6 {
- reg = <6>;
- apss_funnel_in6: endpoint {
- remote-endpoint = <&etm6_out>;
- };
- };
+ qup_spi6_data_clk: qup-spi6-data-clk {
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup06";
+ };
- port@7 {
- reg = <7>;
- apss_funnel_in7: endpoint {
- remote-endpoint = <&etm7_out>;
- };
- };
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio27";
+ function = "qup06";
};
- };
- funnel@7810000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0 0x07810000 0 0x1000>;
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio {
+ pins = "gpio27";
+ function = "gpio";
+ };
- clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ qup_spi7_data_clk: qup-spi7-data-clk {
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup07";
+ };
- out-ports {
- port {
- apss_merge_funnel_out: endpoint {
- remote-endpoint = <&funnel1_in4>;
- };
- };
+ qup_spi7_cs: qup-spi7-cs {
+ pins = "gpio31";
+ function = "qup07";
};
- in-ports {
- port {
- apss_merge_funnel_in: endpoint {
- remote-endpoint = <&apss_funnel_out>;
- };
- };
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio {
+ pins = "gpio31";
+ function = "gpio";
};
- };
- sdhc_2: sdhci@8804000 {
- compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
- status = "disabled";
+ qup_spi8_data_clk: qup-spi8-data-clk {
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup10";
+ };
- reg = <0 0x08804000 0 0x1000>;
+ qup_spi8_cs: qup-spi8-cs {
+ pins = "gpio35";
+ function = "qup10";
+ };
- iommus = <&apps_smmu 0x100 0x0>;
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio {
+ pins = "gpio35";
+ function = "gpio";
+ };
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "core", "iface", "xo";
- interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
- interconnect-names = "sdhc-ddr","cpu-sdhc";
- power-domains = <&rpmhpd SC7280_CX>;
- operating-points-v2 = <&sdhc2_opp_table>;
+ qup_spi9_data_clk: qup-spi9-data-clk {
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup11";
+ };
- bus-width = <4>;
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio39";
+ function = "qup11";
+ };
- qcom,dll-config = <0x0007642c>;
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio {
+ pins = "gpio39";
+ function = "gpio";
+ };
- sdhc2_opp_table: opp-table {
- compatible = "operating-points-v2";
+ qup_spi10_data_clk: qup-spi10-data-clk {
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup12";
+ };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <1800000 400000>;
- opp-avg-kBps = <100000 0>;
- };
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio43";
+ function = "qup12";
+ };
- opp-202000000 {
- opp-hz = /bits/ 64 <202000000>;
- required-opps = <&rpmhpd_opp_nom>;
- opp-peak-kBps = <5400000 1600000>;
- opp-avg-kBps = <200000 0>;
- };
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio {
+ pins = "gpio43";
+ function = "gpio";
};
- };
+ qup_spi11_data_clk: qup-spi11-data-clk {
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup13";
+ };
- usb_1_hsphy: phy@88e3000 {
- compatible = "qcom,sc7280-usb-hs-phy",
- "qcom,usb-snps-hs-7nm-phy";
- reg = <0 0x088e3000 0 0x400>;
- status = "disabled";
- #phy-cells = <0>;
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio47";
+ function = "qup13";
+ };
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio {
+ pins = "gpio47";
+ function = "gpio";
+ };
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
- };
+ qup_spi12_data_clk: qup-spi12-data-clk {
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup14";
+ };
- usb_2_hsphy: phy@88e4000 {
- compatible = "qcom,sc7280-usb-hs-phy",
- "qcom,usb-snps-hs-7nm-phy";
- reg = <0 0x088e4000 0 0x400>;
- status = "disabled";
- #phy-cells = <0>;
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio51";
+ function = "qup14";
+ };
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio {
+ pins = "gpio51";
+ function = "gpio";
+ };
- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
- };
+ qup_spi13_data_clk: qup-spi13-data-clk {
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup15";
+ };
- usb_1_qmpphy: phy-wrapper@88e9000 {
- compatible = "qcom,sc7280-qmp-usb3-dp-phy",
- "qcom,sm8250-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x200>,
- <0 0x088e8000 0 0x40>,
- <0 0x088ea000 0 0x200>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio55";
+ function = "qup15";
+ };
- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "com_aux";
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio {
+ pins = "gpio55";
+ function = "gpio";
+ };
- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_PHY_PRIM_BCR>;
- reset-names = "phy", "common";
+ qup_spi14_data_clk: qup-spi14-data-clk {
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup16";
+ };
- usb_1_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x400>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio59";
+ function = "qup16";
};
- dp_phy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eac00 0 0x400>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>,
- <0 0x088eaa00 0 0x100>;
- #phy-cells = <0>;
- #clock-cells = <1>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio {
+ pins = "gpio59";
+ function = "gpio";
};
- };
- usb_2: usb@8cf8800 {
- compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
- reg = <0 0x08cf8800 0 0x400>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- dma-ranges;
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup17";
+ };
- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
- <&gcc GCC_USB30_SEC_MASTER_CLK>,
- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_SEC_SLEEP_CLK>;
- clock-names = "cfg_noc", "core", "iface","mock_utmi",
- "sleep";
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio63";
+ function = "qup17";
+ };
- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_SEC_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio {
+ pins = "gpio63";
+ function = "gpio";
+ };
- interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 13 IRQ_TYPE_EDGE_RISING>,
- <&pdc 12 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "hs_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ qup_uart0_cts: qup-uart0-cts {
+ pins = "gpio0";
+ function = "qup00";
+ };
- power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+ qup_uart0_rts: qup-uart0-rts {
+ pins = "gpio1";
+ function = "qup00";
+ };
- resets = <&gcc GCC_USB30_SEC_BCR>;
+ qup_uart0_tx: qup-uart0-tx {
+ pins = "gpio2";
+ function = "qup00";
+ };
- interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
- interconnect-names = "usb-ddr", "apps-usb";
+ qup_uart0_rx: qup-uart0-rx {
+ pins = "gpio3";
+ function = "qup00";
+ };
- usb_2_dwc3: usb@8c00000 {
- compatible = "snps,dwc3";
- reg = <0 0x08c00000 0 0xe000>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&apps_smmu 0xa0 0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>;
- phy-names = "usb2-phy";
- maximum-speed = "high-speed";
+ qup_uart1_cts: qup-uart1-cts {
+ pins = "gpio4";
+ function = "qup01";
};
- };
- dc_noc: interconnect@90e0000 {
- reg = <0 0x090e0000 0 0x5080>;
- compatible = "qcom,sc7280-dc-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ qup_uart1_rts: qup-uart1-rts {
+ pins = "gpio5";
+ function = "qup01";
+ };
- gem_noc: interconnect@9100000 {
- reg = <0 0x9100000 0 0xe2200>;
- compatible = "qcom,sc7280-gem-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ qup_uart1_tx: qup-uart1-tx {
+ pins = "gpio6";
+ function = "qup01";
+ };
- system-cache-controller@9200000 {
- compatible = "qcom,sc7280-llcc";
- reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
+ qup_uart1_rx: qup-uart1-rx {
+ pins = "gpio7";
+ function = "qup01";
+ };
- nsp_noc: interconnect@a0c0000 {
- reg = <0 0x0a0c0000 0 0x10000>;
- compatible = "qcom,sc7280-nsp-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
+ qup_uart2_cts: qup-uart2-cts {
+ pins = "gpio8";
+ function = "qup02";
+ };
- usb_1: usb@a6f8800 {
- compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
- reg = <0 0x0a6f8800 0 0x400>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- dma-ranges;
+ qup_uart2_rts: qup-uart2-rts {
+ pins = "gpio9";
+ function = "qup02";
+ };
+
+ qup_uart2_tx: qup-uart2-tx {
+ pins = "gpio10";
+ function = "qup02";
+ };
+
+ qup_uart2_rx: qup-uart2-rx {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_uart3_cts: qup-uart3-cts {
+ pins = "gpio12";
+ function = "qup03";
+ };
- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_MASTER_CLK>,
- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
- clock-names = "cfg_noc", "core", "iface", "mock_utmi",
- "sleep";
+ qup_uart3_rts: qup-uart3-rts {
+ pins = "gpio13";
+ function = "qup03";
+ };
- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_PRIM_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
+ qup_uart3_tx: qup-uart3-tx {
+ pins = "gpio14";
+ function = "qup03";
+ };
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "dm_hs_phy_irq", "ss_phy_irq";
+ qup_uart3_rx: qup-uart3-rx {
+ pins = "gpio15";
+ function = "qup03";
+ };
- power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ qup_uart4_cts: qup-uart4-cts {
+ pins = "gpio16";
+ function = "qup04";
+ };
- resets = <&gcc GCC_USB30_PRIM_BCR>;
+ qup_uart4_rts: qup-uart4-rts {
+ pins = "gpio17";
+ function = "qup04";
+ };
- interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
- interconnect-names = "usb-ddr", "apps-usb";
+ qup_uart4_tx: qup-uart4-tx {
+ pins = "gpio18";
+ function = "qup04";
+ };
- usb_1_dwc3: usb@a600000 {
- compatible = "snps,dwc3";
- reg = <0 0x0a600000 0 0xe000>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&apps_smmu 0xe0 0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
- phy-names = "usb2-phy", "usb3-phy";
- maximum-speed = "super-speed";
+ qup_uart4_rx: qup-uart4-rx {
+ pins = "gpio19";
+ function = "qup04";
};
- };
- videocc: clock-controller@aaf0000 {
- compatible = "qcom,sc7280-videocc";
- reg = <0 0xaaf0000 0 0x10000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>;
- clock-names = "bi_tcxo", "bi_tcxo_ao";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
+ qup_uart5_cts: qup-uart5-cts {
+ pins = "gpio20";
+ function = "qup05";
+ };
- dispcc: clock-controller@af00000 {
- compatible = "qcom,sc7280-dispcc";
- reg = <0 0xaf00000 0 0x20000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_DISP_GPLL0_CLK_SRC>,
- <0>, <0>, <0>, <0>, <0>, <0>;
- clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
- "dsi0_phy_pll_out_byteclk",
- "dsi0_phy_pll_out_dsiclk",
- "dp_phy_pll_link_clk",
- "dp_phy_pll_vco_div_clk",
- "edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
+ qup_uart5_rts: qup-uart5-rts {
+ pins = "gpio21";
+ function = "qup05";
+ };
- pdc: interrupt-controller@b220000 {
- compatible = "qcom,sc7280-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
- qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
- <55 306 4>, <59 312 3>, <62 374 2>,
- <64 434 2>, <66 438 3>, <69 86 1>,
- <70 520 54>, <124 609 31>, <155 63 1>,
- <156 716 12>;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- };
+ qup_uart5_tx: qup-uart5-tx {
+ pins = "gpio22";
+ function = "qup05";
+ };
- pdc_reset: reset-controller@b5e0000 {
- compatible = "qcom,sc7280-pdc-global";
- reg = <0 0x0b5e0000 0 0x20000>;
- #reset-cells = <1>;
- };
+ qup_uart5_rx: qup-uart5-rx {
+ pins = "gpio23";
+ function = "qup05";
+ };
- tsens0: thermal-sensor@c263000 {
- compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
- reg = <0 0x0c263000 0 0x1ff>, /* TM */
- <0 0x0c222000 0 0x1ff>; /* SROT */
- #qcom,sensors = <15>;
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow","critical";
- #thermal-sensor-cells = <1>;
- };
+ qup_uart6_cts: qup-uart6-cts {
+ pins = "gpio24";
+ function = "qup06";
+ };
- tsens1: thermal-sensor@c265000 {
- compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
- reg = <0 0x0c265000 0 0x1ff>, /* TM */
- <0 0x0c223000 0 0x1ff>; /* SROT */
- #qcom,sensors = <12>;
- interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow","critical";
- #thermal-sensor-cells = <1>;
- };
+ qup_uart6_rts: qup-uart6-rts {
+ pins = "gpio25";
+ function = "qup06";
+ };
- aoss_reset: reset-controller@c2a0000 {
- compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
- reg = <0 0x0c2a0000 0 0x31000>;
- #reset-cells = <1>;
- };
+ qup_uart6_tx: qup-uart6-tx {
+ pins = "gpio26";
+ function = "qup06";
+ };
- aoss_qmp: power-controller@c300000 {
- compatible = "qcom,sc7280-aoss-qmp";
- reg = <0 0x0c300000 0 0x100000>;
- interrupts-extended = <&ipcc IPCC_CLIENT_AOP
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_AOP
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qup_uart6_rx: qup-uart6-rx {
+ pins = "gpio27";
+ function = "qup06";
+ };
- #clock-cells = <0>;
- #power-domain-cells = <1>;
- };
+ qup_uart7_cts: qup-uart7-cts {
+ pins = "gpio28";
+ function = "qup07";
+ };
- spmi_bus: spmi@c440000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0 0x0c440000 0 0x1100>,
- <0 0x0c600000 0 0x2000000>,
- <0 0x0e600000 0 0x100000>,
- <0 0x0e700000 0 0xa0000>,
- <0 0x0c40a000 0 0x26000>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
+ qup_uart7_rts: qup-uart7-rts {
+ pins = "gpio29";
+ function = "qup07";
+ };
- tlmm: pinctrl@f100000 {
- compatible = "qcom,sc7280-pinctrl";
- reg = <0 0x0f100000 0 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 175>;
- wakeup-parent = <&pdc>;
+ qup_uart7_tx: qup-uart7-tx {
+ pins = "gpio30";
+ function = "qup07";
+ };
- qup_uart5_default: qup-uart5-default {
- pins = "gpio46", "gpio47";
- function = "qup13";
+ qup_uart7_rx: qup-uart7-rx {
+ pins = "gpio31";
+ function = "qup07";
};
sdc1_on: sdc1-on {
data {
pins = "sdc2_data";
};
-
- sd-cd {
- pins = "gpio91";
- };
};
sdc2_off: sdc2-off {
bias-bus-hold;
};
};
+
+ qup_uart8_cts: qup-uart8-cts {
+ pins = "gpio32";
+ function = "qup10";
+ };
+
+ qup_uart8_rts: qup-uart8-rts {
+ pins = "gpio33";
+ function = "qup10";
+ };
+
+ qup_uart8_tx: qup-uart8-tx {
+ pins = "gpio34";
+ function = "qup10";
+ };
+
+ qup_uart8_rx: qup-uart8-rx {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_uart9_cts: qup-uart9-cts {
+ pins = "gpio36";
+ function = "qup11";
+ };
+
+ qup_uart9_rts: qup-uart9-rts {
+ pins = "gpio37";
+ function = "qup11";
+ };
+
+ qup_uart9_tx: qup-uart9-tx {
+ pins = "gpio38";
+ function = "qup11";
+ };
+
+ qup_uart9_rx: qup-uart9-rx {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_uart10_cts: qup-uart10-cts {
+ pins = "gpio40";
+ function = "qup12";
+ };
+
+ qup_uart10_rts: qup-uart10-rts {
+ pins = "gpio41";
+ function = "qup12";
+ };
+
+ qup_uart10_tx: qup-uart10-tx {
+ pins = "gpio42";
+ function = "qup12";
+ };
+
+ qup_uart10_rx: qup-uart10-rx {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_uart11_cts: qup-uart11-cts {
+ pins = "gpio44";
+ function = "qup13";
+ };
+
+ qup_uart11_rts: qup-uart11-rts {
+ pins = "gpio45";
+ function = "qup13";
+ };
+
+ qup_uart11_tx: qup-uart11-tx {
+ pins = "gpio46";
+ function = "qup13";
+ };
+
+ qup_uart11_rx: qup-uart11-rx {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_uart12_cts: qup-uart12-cts {
+ pins = "gpio48";
+ function = "qup14";
+ };
+
+ qup_uart12_rts: qup-uart12-rts {
+ pins = "gpio49";
+ function = "qup14";
+ };
+
+ qup_uart12_tx: qup-uart12-tx {
+ pins = "gpio50";
+ function = "qup14";
+ };
+
+ qup_uart12_rx: qup-uart12-rx {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_uart13_cts: qup-uart13-cts {
+ pins = "gpio52";
+ function = "qup15";
+ };
+
+ qup_uart13_rts: qup-uart13-rts {
+ pins = "gpio53";
+ function = "qup15";
+ };
+
+ qup_uart13_tx: qup-uart13-tx {
+ pins = "gpio54";
+ function = "qup15";
+ };
+
+ qup_uart13_rx: qup-uart13-rx {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_uart14_cts: qup-uart14-cts {
+ pins = "gpio56";
+ function = "qup16";
+ };
+
+ qup_uart14_rts: qup-uart14-rts {
+ pins = "gpio57";
+ function = "qup16";
+ };
+
+ qup_uart14_tx: qup-uart14-tx {
+ pins = "gpio58";
+ function = "qup16";
+ };
+
+ qup_uart14_rx: qup-uart14-rx {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_uart15_cts: qup-uart15-cts {
+ pins = "gpio60";
+ function = "qup17";
+ };
+
+ qup_uart15_rts: qup-uart15-rts {
+ pins = "gpio61";
+ function = "qup17";
+ };
+
+ qup_uart15_tx: qup-uart15-tx {
+ pins = "gpio62";
+ function = "qup17";
+ };
+
+ qup_uart15_rx: qup-uart15-rx {
+ pins = "gpio63";
+ function = "qup17";
+ };
+ };
+
+ imem@146a5000 {
+ compatible = "qcom,sc7280-imem", "syscon";
+ reg = <0 0x146a5000 0 0x6000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146a5000 0x6000>;
+
+ pil-reloc@594c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x594c 0xc8>;
+ };
};
apps_smmu: iommu@15000000 {
};
gpuss0-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss0_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss0_crit: gpuss0-crit {
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpuss1-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss1_crit: gpuss1-crit {
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
nspss0-thermal {
regulator-allow-set-load;
};
- vreg_l4b_29p5: l4 {
+ vreg_l4b_2p95: l4 {
regulator-min-microvolt = <2944000>;
regulator-max-microvolt = <2952000>;
regulator-enable-ramp-delay = <250>;
* Tighten the range to 1.8-3.328 (closest to 3.3) to
* make the mmc driver happy.
*/
- vreg_l5b_29p5: l5 {
+ vreg_l5b_2p95: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3328000>;
regulator-enable-ramp-delay = <250>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
- vmmc-supply = <&vreg_l4b_29p5>;
+ vmmc-supply = <&vreg_l4b_2p95>;
vqmmc-supply = <&vreg_l8a_1p8>;
};
&sdhc_2 {
status = "okay";
- vmmc-supply = <&vreg_l5b_29p5>;
+ vmmc-supply = <&vreg_l5b_2p95>;
vqmmc-supply = <&vreg_l2b_2p95>;
};
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
};
};
- cryptobam: dma@1dc4000 {
+ cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rpmhcc 15>;
+ clocks = <&rpmhcc RPMH_CE_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
- qcom,controlled-remotely = <1>;
+ qcom,controlled-remotely;
iommus = <&apps_smmu 0x704 0x1>,
<&apps_smmu 0x706 0x1>,
<&apps_smmu 0x714 0x1>,
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>,
- <&rpmhcc 15>;
+ <&rpmhcc RPMH_CE_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 6>, <&cryptobam 7>;
dma-names = "rx", "tx";
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng", "xo";
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
- power-domains = <&aoss_qmp 2>,
- <&rpmhpd SDM845_CX>,
+ power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>,
<&rpmhpd SDM845_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
+ power-domain-names = "cx", "mx", "mss";
mba {
memory-region = <&mba_region>;
};
};
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d70800 0 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU4>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d78800 0 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU0>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
sound: sound {
};
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
+ interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu0_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu0_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu1-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu1_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu1_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu2-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu2_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu2_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu3-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu3_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu3_alert1>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu4-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu4_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu4_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu5-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu5_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu5_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu6-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu6_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu6_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
cpu7-thermal {
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&cpu7_alert0>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu7_alert1>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
};
aoss0-thermal {
};
vreg_l23a_3p3: ldo23 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
+ vddch1-supply = <&vreg_l23a_3p3>;
max-speed = <3200000>;
};
};
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+ vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};
tlmm: pinctrl@500000 {
compatible = "qcom,sm6125-tlmm";
reg = <0x00500000 0x400000>,
- <0x00900000 0x400000>,
- <0x00d00000 0x400000>;
+ <0x00900000 0x400000>,
+ <0x00d00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
reg-names = "hc", "core";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
- <&gcc GCC_SDCC1_APPS_CLK>,
- <&xo_board>;
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
clock-names = "iface", "core", "xo";
bus-width = <8>;
non-removable;
reg-names = "hc";
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
clock-names = "iface", "core", "xo";
pinctrl-0 = <&sdc2_state_on>;
ranges;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
- <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
- reg = <0x01c40000 0x1100>,
- <0x01e00000 0x2000000>,
- <0x03e00000 0x100000>,
- <0x03f00000 0xa0000>,
- <0x01c0a000 0x26000>;
+ reg = <0x01c40000 0x1100>,
+ <0x01e00000 0x2000000>,
+ <0x03e00000 0x100000>,
+ <0x03f00000 0xa0000>,
+ <0x01c0a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f120000 0x1000>;
clock-frequency = <19200000>;
- frame@0f121000 {
+ frame@f121000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f121000 0x1000>,
<0x0f122000 0x1000>;
};
- frame@0f123000 {
+ frame@f123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f123000 0x1000>;
status = "disabled";
};
- frame@0f124000 {
+ frame@f124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0f124000 0x1000>;
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0x0f200000 0x20000>,
- <0x0f300000 0x100000>;
+ <0x0f300000 0x100000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 0xf08
- GIC_PPI 2 0xf08
- GIC_PPI 3 0xf08
- GIC_PPI 0 0xf08>;
+ GIC_PPI 2 0xf08
+ GIC_PPI 3 0xf08
+ GIC_PPI 0 0xf08>;
clock-frequency = <19200000>;
};
};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+/dts-v1/;
+
+#include "sm6350.dtsi"
+
+/ {
+ model = "Sony Xperia 10 III";
+ compatible = "sony,pdx213", "qcom,sm6350";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@a0000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0xa0000000 0 0x2300000>;
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ clocks = <&gcc GCC_DISP_AXI_CLK>;
+ };
+ };
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <13 4>, <45 2>, <56 2>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ maximum-speed = "super-speed";
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sm6350.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <76800000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <703>;
+ next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <703>;
+ next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm6350", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ reg = <0 0x80000000 0 0x600000>;
+ no-map;
+ };
+
+ xbl_aop_mem: memory@80700000 {
+ reg = <0 0x80700000 0 0x160000>;
+ no-map;
+ };
+
+ cmd_db: memory@80860000 {
+ compatible = "qcom,cmd-db";
+ reg = <0 0x80860000 0 0x20000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0 0x808ff000 0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: memory@80900000 {
+ reg = <0 0x80900000 0 0x200000>;
+ no-map;
+ };
+
+ cdsp_sec_mem: memory@80b00000 {
+ reg = <0 0x80b00000 0 0x1e00000>;
+ no-map;
+ };
+
+ pil_camera_mem: memory@86000000 {
+ reg = <0 0x86000000 0 0x500000>;
+ no-map;
+ };
+
+ pil_npu_mem: memory@86500000 {
+ reg = <0 0x86500000 0 0x500000>;
+ no-map;
+ };
+
+ pil_video_mem: memory@86a00000 {
+ reg = <0 0x86a00000 0 0x500000>;
+ no-map;
+ };
+
+ pil_cdsp_mem: memory@86f00000 {
+ reg = <0 0x86f00000 0 0x1e00000>;
+ no-map;
+ };
+
+ pil_adsp_mem: memory@88d00000 {
+ reg = <0 0x88d00000 0 0x2800000>;
+ no-map;
+ };
+
+ wlan_fw_mem: memory@8b500000 {
+ reg = <0 0x8b500000 0 0x200000>;
+ no-map;
+ };
+
+ pil_ipa_fw_mem: memory@8b700000 {
+ reg = <0 0x8b700000 0 0x10000>;
+ no-map;
+ };
+
+ pil_ipa_gsi_mem: memory@8b710000 {
+ reg = <0 0x8b710000 0 0x5400>;
+ no-map;
+ };
+
+ pil_gpu_mem: memory@8b715400 {
+ reg = <0 0x8b715400 0 0x2000>;
+ no-map;
+ };
+
+ pil_modem_mem: memory@8b800000 {
+ reg = <0 0x8b800000 0 0xf800000>;
+ no-map;
+ };
+
+ cont_splash_memory: memory@a0000000 {
+ reg = <0 0xa0000000 0 0x2300000>;
+ no-map;
+ };
+
+ dfps_data_memory: memory@a2300000 {
+ reg = <0 0xa2300000 0 0x100000>;
+ no-map;
+ };
+
+ removed_region: memory@c0000000 {
+ reg = <0 0xc0000000 0 0x3900000>;
+ no-map;
+ };
+
+ debug_region: memory@ffb00000 {
+ reg = <0 0xffb00000 0 0xc0000>;
+ no-map;
+ };
+
+ last_log_region: memory@ffbc0000 {
+ reg = <0 0xffbc0000 0 0x40000>;
+ no-map;
+ };
+
+ ramoops: ramoops@ffc00000 {
+ compatible = "removed-dma-pool", "ramoops";
+ reg = <0 0xffc00000 0 0x00100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ ftrace-size = <0x0>;
+ msg-size = <0x20000 0x20000>;
+ cc-size = <0x0>;
+ no-map;
+ };
+
+ cmdline_region: memory@ffd00000 {
+ reg = <0 0xffd00000 0 0x1000>;
+ no-map;
+ };
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sm6350";
+ reg = <0 0x00100000 0 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ };
+
+ ipcc: mailbox@408000 {
+ compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
+ reg = <0 0x00408000 0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ rng: rng@793000 {
+ compatible = "qcom,prng-ee";
+ reg = <0 0x00793000 0 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
+ sdhc_1: sdhci@7c4000 {
+ compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>,
+ <0 0x007c8000 0 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd 0>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ bus-width = <8>;
+ non-removable;
+ supports-cqe;
+
+ status = "disabled";
+
+ sdhc1_opp_table: sdhc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd 0>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ bus-width = <4>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
+ reg = <0 0x088e3000 0 0x400>;
+ status = "disabled";
+ #phy-cells = <0>;
+
+ clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ };
+
+ usb_1_qmpphy: phy@88e9000 {
+ compatible = "qcom,sc7180-qmp-usb3-dp-phy";
+ reg = <0 0x088e9000 0 0x200>,
+ <0 0x088e8000 0 0x40>,
+ <0 0x088ea000 0 0x200>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&xo_board>;
+ clock-names = "aux", "ref", "com_aux", "cfg_ahb";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ usb_1_ssphy: usb3-phy@88e9200 {
+ reg = <0 0x088e9200 0 0x200>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x400>,
+ <0 0x088e9600 0 0x200>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+
+ dp_phy: dp-phy@88ea200 {
+ reg = <0 0x088ea200 0 0x200>,
+ <0 0x088ea400 0 0x200>,
+ <0 0x088eac00 0 0x400>,
+ <0 0x088ea600 0 0x200>,
+ <0 0x088ea800 0 0x200>,
+ <0 0x088eaa00 0 0x100>;
+ #phy-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
+
+ system-cache-controller@9200000 {
+ compatible = "qcom,sm6350-llcc";
+ reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep";
+
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
+ "dm_hs_phy_irq", "ss_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x540 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm6350-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>, <126 655 12>, <138 139 15>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x8>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x8>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-controller@c300000 {
+ compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x1000>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+ };
+
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0xc440000 0 0x1100>,
+ <0 0xc600000 0 0x2000000>,
+ <0 0xe600000 0 0x100000>,
+ <0 0xe700000 0 0xa0000>,
+ <0 0xc40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm6350-tlmm";
+ reg = <0 0x0f100000 0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 157>;
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
+ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog@17c10000 {
+ compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
+ reg = <0 0x17c10000 0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@17c20000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17c20000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c21000 0x0 0x1000>,
+ <0x0 0x17c22000 0x0 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c23000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c25000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c27000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c29000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c2b000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c2d000 0x0 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ label = "apps_rsc";
+ reg = <0x0 0x18200000 0x0 0x10000>,
+ <0x0 0x18210000 0x0 0x10000>,
+ <0x0 0x18220000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 1>;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm6350-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sm6350-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
+
+ cpufreq_hw: cpufreq@18323000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ clock-frequency = <19200000>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 3>,
+ power-domains = <&rpmhpd 3>,
<&rpmhpd 2>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 7>,
+ power-domains = <&rpmhpd 7>,
<&rpmhpd 0>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 7>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd 7>;
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd SM8250_CX>;
- power-domain-names = "load_state", "cx";
+ power-domains = <&rpmhpd SM8250_CX>;
memory-region = <&cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd SM8250_LCX>,
+ power-domains = <&rpmhpd SM8250_LCX>,
<&rpmhpd SM8250_LMX>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 12>;
- power-domain-names = "load_state", "cx", "mss";
+ power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
- <&rpmhpd 0>,
+ power-domains = <&rpmhpd 0>,
<&rpmhpd 10>;
- power-domain-names = "load_state", "cx", "mxc";
+ power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
- <&rpmhpd 4>,
+ power-domains = <&rpmhpd 4>,
<&rpmhpd 5>;
- power-domain-names = "load_state", "lcx", "lmx";
+ power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
+ qcom,qmp = <&aoss_qmp>;
+
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
+
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
+ phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id004d.d074",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c915",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Draak board
+ *
+ * Copyright (C) 2016-2018 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Renesas Draak board";
+ compatible = "renesas,draak";
+
+ aliases {
+ serial0 = &scif2;
+ ethernet0 = &avb;
+ };
+
+ audio_clkout: audio-clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000>;
+
+ brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
+ default-brightness-level = <10>;
+
+ power-supply = <®_12p0v>;
+ enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+ stdout-path = "serial0:115200n8";
+ };
+
+ composite-in {
+ compatible = "composite-video-connector";
+
+ port {
+ composite_con_in: endpoint {
+ remote-endpoint = <&adv7180_in>;
+ };
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keys_pins>;
+ pinctrl-names = "default";
+
+ key-1 {
+ gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW56-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW56-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW56-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW56-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <®_3p3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x18000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_12p0v: regulator-12p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "D12.0V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound_card: sound {
+ compatible = "audio-graph-card";
+
+ dais = <&rsnd_port0 /* ak4613 */
+ /* HDMI is not yet supported */
+ >;
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ x19_clk: x19 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+};
+
+&audio_clk_b {
+ /*
+ * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
+ * and R-Car Sound uses AUDIO_CLKB.
+ * Note is that schematic indicates VI4_FIELD conection only
+ * not AUDIO_CLKB at SoC page.
+ * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
+ * SW60 should be 1-2.
+ */
+
+ clock-frequency = <22579200>;
+};
+
+&avb {
+ pinctrl-0 = <&avb0_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
+ /*
+ * TX clock internal delay mode is required for reliable
+ * 1Gbps communication using the KSZ9031RNX phy present on
+ * the Draak board, however, TX clock internal delay mode
+ * isn't supported on R-Car D3(e). Thus, limit speed to
+ * 100Mbps for reliable communication.
+ */
+ max-speed = <100>;
+ };
+};
+
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&x12_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
+&ehci0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&hsusb {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 0>; /* audio_clkout */
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+
+ port {
+ ak4613_endpoint: endpoint {
+ remote-endpoint = <&rsnd_for_ak4613>;
+ };
+ };
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180cp";
+ reg = <0x20>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7180_in: endpoint {
+ remote-endpoint = <&composite_con_in>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ /*
+ * The VIN4 video input path is shared between
+ * CVBS and HDMI inputs through SW[49-53]
+ * switches.
+ *
+ * CVBS is the default selection, link it to
+ * VIN4 here.
+ */
+ adv7180_out: endpoint {
+ remote-endpoint = <&vin4_in>;
+ };
+ };
+ };
+
+ };
+
+ hdmi-encoder@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
+ reg-names = "main", "edid", "cec", "packet";
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-decoder@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ /*
+ * The VIN4 video input path is shared between
+ * CVBS and HDMI inputs through SW[49-53]
+ * switches.
+ *
+ * CVBS is the default selection, leave HDMI
+ * not connected here.
+ */
+ adv7612_out: endpoint {
+ pclk-sample = <0>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+ };
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lvds0 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&x12_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&lvds1 {
+ /*
+ * Even though the LVDS1 output is not connected, the encoder must be
+ * enabled to supply a pixel clock to the DU for the DPAD output when
+ * LVDS0 is in use.
+ */
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&x12_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+};
+
+&ohci0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&pfc {
+ avb0_pins: avb {
+ groups = "avb0_link", "avb0_mdio", "avb0_mii";
+ function = "avb0";
+ };
+
+ can0_pins: can0 {
+ groups = "can0_data_a";
+ function = "can0";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data_a";
+ function = "can1";
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ keys_pins: keys {
+ pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
+ bias-pull-up;
+ };
+
+ pwm0_pins: pwm0 {
+ groups = "pwm0_c";
+ function = "pwm0";
+ };
+
+ pwm1_pins: pwm1 {
+ groups = "pwm1_c";
+ function = "pwm1";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data";
+ function = "scif2";
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
+ sound_pins: sound {
+ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound-clk {
+ groups = "audio_clk_a", "audio_clk_b",
+ "audio_clkout", "audio_clkout1";
+ function = "audio_clk";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ vin4_pins_cvbs: vin4 {
+ groups = "vin4_data8", "vin4_sync", "vin4_clk";
+ function = "vin4";
+ };
+};
+
+&pwm0 {
+ pinctrl-0 = <&pwm0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
+ <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&cs2000>, <&audio_clk_b>,
+ <&cpg CPG_CORE R8A77995_CLK_ZA2>;
+
+ ports {
+ rsnd_port0: port {
+ rsnd_for_ak4613: endpoint {
+ remote-endpoint = <&ak4613_endpoint>;
+ dai-format = "left_j";
+ bitclock-master = <&rsnd_for_ak4613>;
+ frame-master = <&rsnd_for_ak4613>;
+ playback = <&ssi3>, <&src5>, <&dvc0>;
+ capture = <&ssi4>, <&src6>, <&dvc1>;
+ };
+ };
+ };
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi2 {
+ /* used for on-board eMMC */
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&ssi4 {
+ shared-pin;
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ renesas,no-otg-pins;
+ status = "okay";
+};
+
+&vin4 {
+ pinctrl-0 = <&vin4_pins_cvbs>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ ports {
+ port {
+ vin4_in: endpoint {
+ remote-endpoint = <&adv7180_out>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Ebisu board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Renesas Ebisu board";
+ compatible = "renesas,ebisu";
+
+ aliases {
+ serial0 = &scif2;
+ ethernet0 = &avb;
+ mmc0 = &sdhi3;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+ stdout-path = "serial0:115200n8";
+ };
+
+ audio_clkout: audio-clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 50000>;
+
+ brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
+ default-brightness-level = <10>;
+
+ power-supply = <®_12p0v>;
+ };
+
+ cvbs-in {
+ compatible = "composite-video-connector";
+ label = "CVBS IN";
+
+ port {
+ cvbs_con: endpoint {
+ remote-endpoint = <&adv7482_ain7>;
+ };
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ label = "HDMI IN";
+ type = "a";
+
+ port {
+ hdmi_in_con: endpoint {
+ remote-endpoint = <&adv7482_hdmi>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keys_pins>;
+ pinctrl-names = "default";
+
+ key-1 {
+ gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW4-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW4-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW4-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW4-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <®_3p3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_12p0v: regulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "D12.0V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ rsnd_ak4613: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,name = "rsnd-ak4613";
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcpu>;
+ simple-audio-card,frame-master = <&sndcpu>;
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4613>;
+ };
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS_CN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ x13_clk: x13 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ /*
+ * TX clock internal delay mode is required for reliable
+ * 1Gbps communication using the KSZ9031RNX phy present on
+ * the Ebisu board, however, TX clock internal delay mode
+ * isn't supported on R-Car E3(e). Thus, limit speed to
+ * 100Mbps for reliable communication.
+ */
+ max-speed = <100>;
+ };
+};
+
+&canfd {
+ pinctrl-0 = <&canfd0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+};
+
+&csi40 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ csi40_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&adv7482_txa>;
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&x13_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ io_expander: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ hdmi-encoder@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ video-receiver@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupt-names = "intrq1", "intrq2";
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
+ <17 IRQ_TYPE_LEVEL_LOW>;
+
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_con>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_con>;
+ };
+ };
+
+ port@a {
+ reg = <10>;
+
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+&i2c_dvfs {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ pmic: pmic@30 {
+ pinctrl-0 = <&irq0_pins>;
+ pinctrl-names = "default";
+
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&intc_ex>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rohm,ddr-backup-power = <0x1>;
+ rohm,rstbmode-level;
+ };
+
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&x13_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&lvds1 {
+ /*
+ * Even though the LVDS1 output is not connected, the encoder must be
+ * enabled to supply a pixel clock to the DU for the DPAD output when
+ * LVDS0 is in use.
+ */
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&x13_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ status = "okay";
+};
+
+&pfc {
+ avb_pins: avb {
+ groups = "avb_link", "avb_mii";
+ function = "avb";
+ };
+
+ canfd0_pins: canfd0 {
+ groups = "canfd0_data";
+ function = "canfd0";
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ irq0_pins: irq0 {
+ groups = "intc_ex_irq0";
+ function = "intc_ex";
+ };
+
+ keys_pins: keys {
+ pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
+ bias-pull-up;
+ };
+
+ pwm3_pins: pwm3 {
+ groups = "pwm3_b";
+ function = "pwm3";
+ };
+
+ pwm5_pins: pwm5 {
+ groups = "pwm5_a";
+ function = "pwm5";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
+ "audio_clkout_a", "audio_clkout1_a";
+ function = "audio_clk";
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ usb0_pins: usb {
+ groups = "usb0_b", "usb0_id";
+ function = "usb0";
+ };
+
+ usb30_pins: usb30 {
+ groups = "usb30";
+ function = "usb30";
+ };
+};
+
+&pwm3 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm5 {
+ pinctrl-0 = <&pwm5_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+
+ status = "okay";
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A77990_CLK_ZA2>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0>, <&src0>, <&dvc0>;
+ capture = <&ssi1>, <&src1>, <&dvc1>;
+ };
+ };
+
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi3 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ full-pwr-cycle-in-suspend;
+ status = "okay";
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&vbus0_usb2>;
+ status = "okay";
+};
+
+&usb3_peri0 {
+ companion = <&xhci0>;
+ status = "okay";
+};
+
+&vin4 {
+ status = "okay";
+};
+
+&vin5 {
+ status = "okay";
+};
+
+&xhci0 {
+ pinctrl-0 = <&usb30_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c915",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77961", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a77961",
"renesas,rcar-gen3-msiof";
/dts-v1/;
#include "r8a77970.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Eagle board based on r8a77970";
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
/dts-v1/;
#include "r8a77970.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas V3M Starter Kit board";
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
/dts-v1/;
#include "r8a77980.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Condor board based on r8a77980";
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
};
/dts-v1/;
#include "r8a77980.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas V3H Starter Kit board";
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
};
/dts-v1/;
#include "r8a77990.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "ebisu.dtsi"
/ {
model = "Renesas Ebisu board based on r8a77990";
compatible = "renesas,ebisu", "renesas,r8a77990";
-
- aliases {
- serial0 = &scif2;
- ethernet0 = &avb;
- mmc0 = &sdhi3;
- mmc1 = &sdhi0;
- mmc2 = &sdhi1;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm3 0 50000>;
-
- brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
- default-brightness-level = <10>;
-
- power-supply = <®_12p0v>;
- };
-
- cvbs-in {
- compatible = "composite-video-connector";
- label = "CVBS IN";
-
- port {
- cvbs_con: endpoint {
- remote-endpoint = <&adv7482_ain7>;
- };
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- label = "HDMI IN";
- type = "a";
-
- port {
- hdmi_in_con: endpoint {
- remote-endpoint = <&adv7482_hdmi>;
- };
- };
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW4-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-2 {
- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW4-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-3 {
- gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW4-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW4-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- lvds-decoder {
- compatible = "thine,thc63lvd1024";
- vcc-supply = <®_3p3v>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- thc63lvd1024_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
-
- port@2 {
- reg = <2>;
- thc63lvd1024_out: endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
- };
-
- reg_1p8v: regulator0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator1 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_12p0v: regulator2 {
- compatible = "regulator-fixed";
- regulator-name = "D12.0V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- rsnd_ak4613: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,name = "rsnd-ak4613";
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcpu>;
- simple-audio-card,frame-master = <&sndcpu>;
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4613>;
- };
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
- };
-
- vbus0_usb2: regulator-vbus0-usb2 {
- compatible = "regulator-fixed";
-
- regulator-name = "USB20_VBUS_CN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- x13_clk: x13 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
- /*
- * TX clock internal delay mode is required for reliable
- * 1Gbps communication using the KSZ9031RNX phy present on
- * the Ebisu board, however, TX clock internal delay mode
- * isn't supported on r8a77990. Thus, limit speed to
- * 100Mbps for reliable communication.
- */
- max-speed = <100>;
- };
-};
-
-&canfd {
- pinctrl-0 = <&canfd0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
- };
-};
-
-&csi40 {
- status = "okay";
-
- ports {
- port@0 {
- csi40_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2>;
- remote-endpoint = <&adv7482_txa>;
- };
- };
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&x13_clk>;
- clock-names = "du.0", "du.1", "dclkin.0";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&ehci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <48000000>;
-};
-
-&hsusb {
- dr_mode = "otg";
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- io_expander: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio2>;
- interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
- };
-
- hdmi-encoder@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&thc63lvd1024_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- video-receiver@70 {
- compatible = "adi,adv7482";
- reg = <0x70>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gpio0>;
- interrupt-names = "intrq1", "intrq2";
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
- <17 IRQ_TYPE_LEVEL_LOW>;
-
- port@7 {
- reg = <7>;
-
- adv7482_ain7: endpoint {
- remote-endpoint = <&cvbs_con>;
- };
- };
-
- port@8 {
- reg = <8>;
-
- adv7482_hdmi: endpoint {
- remote-endpoint = <&hdmi_in_con>;
- };
- };
-
- port@a {
- reg = <10>;
-
- adv7482_txa: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2>;
- remote-endpoint = <&csi40_in>;
- };
- };
- };
-};
-
-&i2c3 {
- status = "okay";
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
- };
-
- cs2000: clk-multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&i2c_dvfs {
- status = "okay";
-
- clock-frequency = <400000>;
-
- pmic: pmic@30 {
- pinctrl-0 = <&irq0_pins>;
- pinctrl-names = "default";
-
- compatible = "rohm,bd9571mwv";
- reg = <0x30>;
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- rohm,ddr-backup-power = <0x1>;
- rohm,rstbmode-level;
- };
-
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&lvds0 {
- status = "okay";
-
- clocks = <&cpg CPG_MOD 727>,
- <&x13_clk>,
- <&extal_clk>;
- clock-names = "fck", "dclkin.0", "extal";
-
- ports {
- port@1 {
- lvds0_out: endpoint {
- remote-endpoint = <&thc63lvd1024_in>;
- };
- };
- };
-};
-
-&lvds1 {
- /*
- * Even though the LVDS1 output is not connected, the encoder must be
- * enabled to supply a pixel clock to the DU for the DPAD output when
- * LVDS0 is in use.
- */
- status = "okay";
-
- clocks = <&cpg CPG_MOD 727>,
- <&x13_clk>,
- <&extal_clk>;
- clock-names = "fck", "dclkin.0", "extal";
-};
-
-&ohci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec0 {
- status = "okay";
-};
-
-&pfc {
- avb_pins: avb {
- groups = "avb_link", "avb_mii";
- function = "avb";
- };
-
- canfd0_pins: canfd0 {
- groups = "canfd0_data";
- function = "canfd0";
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
- function = "du";
- };
-
- irq0_pins: irq0 {
- groups = "intc_ex_irq0";
- function = "intc_ex";
- };
-
- keys_pins: keys {
- pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
- bias-pull-up;
- };
-
- pwm3_pins: pwm3 {
- groups = "pwm3_b";
- function = "pwm3";
- };
-
- pwm5_pins: pwm5 {
- groups = "pwm5_a";
- function = "pwm5";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-
- sdhi1_pins_uhs: sd1_uhs {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <1800>;
- };
-
- sdhi3_pins: sd3 {
- groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
- function = "sdhi3";
- power-source = <1800>;
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout1_a";
- function = "audio_clk";
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
- function = "ssi";
- };
-
- usb0_pins: usb {
- groups = "usb0_b", "usb0_id";
- function = "usb0";
- };
-
- usb30_pins: usb30 {
- groups = "usb30";
- function = "usb30";
- };
-};
-
-&pwm3 {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pwm5 {
- pinctrl-0 = <&pwm5_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <12288000 11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A77990_CLK_ZA2>;
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
- };
- };
-
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-1 = <&sdhi1_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi3 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi3_pins>;
- pinctrl-1 = <&sdhi3_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- bus-width = <8>;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- vbus-supply = <&vbus0_usb2>;
- status = "okay";
-};
-
-&usb3_peri0 {
- companion = <&xhci0>;
- status = "okay";
-};
-
-&vin4 {
- status = "okay";
-};
-
-&vin5 {
- status = "okay";
-};
-
-&xhci0 {
- pinctrl-0 = <&usb30_pins>;
- pinctrl-names = "default";
-
- status = "okay";
};
/dts-v1/;
#include "r8a77995.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "draak.dtsi"
/ {
model = "Renesas Draak board based on r8a77995";
compatible = "renesas,draak", "renesas,r8a77995";
-
- aliases {
- serial0 = &scif2;
- ethernet0 = &avb;
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12288000>;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 50000>;
-
- brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
- default-brightness-level = <10>;
-
- power-supply = <®_12p0v>;
- enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- composite-in {
- compatible = "composite-video-connector";
-
- port {
- composite_con_in: endpoint {
- remote-endpoint = <&adv7180_in>;
- };
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&adv7612_in>;
- };
- };
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW56-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-2 {
- gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW56-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-3 {
- gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW56-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW56-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- lvds-decoder {
- compatible = "thine,thc63lvd1024";
- vcc-supply = <®_3p3v>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- thc63lvd1024_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
-
- port@2 {
- reg = <2>;
- thc63lvd1024_out: endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x18000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_12p0v: regulator-12p0v {
- compatible = "regulator-fixed";
- regulator-name = "D12.0V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound_card: sound {
- compatible = "audio-graph-card";
-
- dais = <&rsnd_port0 /* ak4613 */
- /* HDMI is not yet supported */
- >;
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x19_clk: x19 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-};
-
-&audio_clk_b {
- /*
- * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
- * and R-Car Sound uses AUDIO_CLKB.
- * Note is that schematic indicates VI4_FIELD conection only
- * not AUDIO_CLKB at SoC page.
- * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
- * SW60 should be 1-2.
- */
-
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb0_pins>;
- pinctrl-names = "default";
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio5>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
- /*
- * TX clock internal delay mode is required for reliable
- * 1Gbps communication using the KSZ9031RNX phy present on
- * the Draak board, however, TX clock internal delay mode
- * isn't supported on r8a77995. Thus, limit speed to
- * 100Mbps for reliable communication.
- */
- max-speed = <100>;
- };
-};
-
-&can0 {
- pinctrl-0 = <&can0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&can1 {
- pinctrl-0 = <&can1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&x12_clk>;
- clock-names = "du.0", "du.1", "dclkin.0";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&ehci0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <48000000>;
-};
-
-&hsusb {
- dr_mode = "host";
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
- reg = <0x10>;
- clocks = <&rcar_sound 0>; /* audio_clkout */
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
-
- port {
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_for_ak4613>;
- };
- };
- };
-
- composite-in@20 {
- compatible = "adi,adv7180cp";
- reg = <0x20>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7180_in: endpoint {
- remote-endpoint = <&composite_con_in>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- /*
- * The VIN4 video input path is shared between
- * CVBS and HDMI inputs through SW[49-53]
- * switches.
- *
- * CVBS is the default selection, link it to
- * VIN4 here.
- */
- adv7180_out: endpoint {
- remote-endpoint = <&vin4_in>;
- };
- };
- };
-
- };
-
- hdmi-encoder@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
- reg-names = "main", "edid", "cec", "packet";
- interrupt-parent = <&gpio1>;
- interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&thc63lvd1024_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-decoder@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- default-input = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- /*
- * The VIN4 video input path is shared between
- * CVBS and HDMI inputs through SW[49-53]
- * switches.
- *
- * CVBS is the default selection, leave HDMI
- * not connected here.
- */
- adv7612_out: endpoint {
- pclk-sample = <0>;
- hsync-active = <0>;
- vsync-active = <0>;
- };
- };
- };
- };
-
- cs2000: clk-multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&lvds0 {
- status = "okay";
-
- clocks = <&cpg CPG_MOD 727>,
- <&x12_clk>,
- <&extal_clk>;
- clock-names = "fck", "dclkin.0", "extal";
-
- ports {
- port@1 {
- lvds0_out: endpoint {
- remote-endpoint = <&thc63lvd1024_in>;
- };
- };
- };
-};
-
-&lvds1 {
- /*
- * Even though the LVDS1 output is not connected, the encoder must be
- * enabled to supply a pixel clock to the DU for the DPAD output when
- * LVDS0 is in use.
- */
- status = "okay";
-
- clocks = <&cpg CPG_MOD 727>,
- <&x12_clk>,
- <&extal_clk>;
- clock-names = "fck", "dclkin.0", "extal";
-};
-
-&ohci0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&pfc {
- avb0_pins: avb {
- groups = "avb0_link", "avb0_mdio", "avb0_mii";
- function = "avb0";
- };
-
- can0_pins: can0 {
- groups = "can0_data_a";
- function = "can0";
- };
-
- can1_pins: can1 {
- groups = "can1_data_a";
- function = "can1";
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
- function = "du";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- keys_pins: keys {
- pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
- bias-pull-up;
- };
-
- pwm0_pins: pwm0 {
- groups = "pwm0_c";
- function = "pwm0";
- };
-
- pwm1_pins: pwm1 {
- groups = "pwm1_c";
- function = "pwm1";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data";
- function = "scif2";
- };
-
- sdhi2_pins: sd2 {
- groups = "mmc_data8", "mmc_ctrl";
- function = "mmc";
- power-source = <1800>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "mmc_data8", "mmc_ctrl";
- function = "mmc";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound-clk {
- groups = "audio_clk_a", "audio_clk_b",
- "audio_clkout", "audio_clkout1";
- function = "audio_clk";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- vin4_pins_cvbs: vin4 {
- groups = "vin4_data8", "vin4_sync", "vin4_clk";
- function = "vin4";
- };
-};
-
-&pwm0 {
- pinctrl-0 = <&pwm0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pwm1 {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- /* audio_clkout0/1 */
- #clock-cells = <1>;
- clock-frequency = <12288000 11289600>;
-
- status = "okay";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&cs2000>, <&audio_clk_b>,
- <&cpg CPG_CORE R8A77995_CLK_ZA2>;
-
- ports {
- rsnd_port0: port {
- rsnd_for_ak4613: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
- dai-format = "left_j";
- bitclock-master = <&rsnd_for_ak4613>;
- frame-master = <&rsnd_for_ak4613>;
- playback = <&ssi3>, <&src5>, <&dvc0>;
- capture = <&ssi4>, <&src6>, <&dvc1>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- status = "okay";
-};
-
-&ssi4 {
- shared-pin;
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- renesas,no-otg-pins;
- status = "okay";
-};
-
-&vin4 {
- pinctrl-0 = <&vin4_pins_cvbs>;
- pinctrl-names = "default";
-
- status = "okay";
-
- ports {
- port {
- vin4_in: endpoint {
- remote-endpoint = <&adv7180_out>;
- };
- };
- };
};
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "r8a779a0.dtsi"
stdout-path = "serial0:115200n8";
};
+ keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keys_pins>;
+ pinctrl-names = "default";
+
+ key-1 {
+ gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW47";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-2 {
+ gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW48";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-3 {
+ gpios = <&gpio6 20 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW49";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
function = "i2c6";
};
+ keys_pins: keys {
+ pins = "GP_6_18", "GP_6_19", "GP_6_20";
+ bias-pull-up;
+ };
+
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a779a0", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
+ iommus = <&ipmmu_ds0 32>;
status = "disabled";
};
+ ipmmu_rt0: iommu@ee480000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xee480000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_rt1: iommu@ee4c0000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xee4c0000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 19>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ds0: iommu@eed00000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeed00000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ds1: iommu@eed40000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeed40000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 1>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ir: iommu@eed80000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeed80000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 3>;
+ power-domains = <&sysc R8A779A0_PD_A3IR>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: iommu@eedc0000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeedc0000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: iommu@eee80000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeee80000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi1: iommu@eeec0000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeeec0000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 15>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_3dg: iommu@eee00000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeee00000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 6>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip0: iommu@eef00000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeef00000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 5>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip1: iommu@eef40000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeef40000 0 0x20000>;
+ renesas,ipmmu-main = <&ipmmu_mm 11>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: iommu@eefc0000 {
+ compatible = "renesas,ipmmu-r8a779a0";
+ reg = <0 0xeefc0000 0 0x20000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car H3e (R8A779M0) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77951.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m0", "renesas,r8a7795";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car M3e (R8A779M2) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77961.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m2", "renesas,r8a77961";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77965.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m4", "renesas,r8a77965";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3Ne-2G
+ *
+ * Copyright (C) 2021 Glider bv
+ *
+ * Based on r8a77965-salvator-xs.dts
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779m5.dtsi"
+#include "salvator-xs.dtsi"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a779m5";
+ compatible = "renesas,salvator-xs", "renesas,r8a779m5",
+ "renesas,r8a77965";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>,
+ <&versaclock6 1>,
+ <&x21_clk>,
+ <&versaclock6 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car M3Ne-2G (R8A779M5) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77965.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m5", "renesas,r8a77965";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car E3e (R8A779M6) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77990.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m6", "renesas,r8a77990";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car D3e (R8A779M7) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77995.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m7", "renesas,r8a77995";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC
+ *
+ * Copyright (C) 2021 Glider bv
+ */
+
+#include "r8a77951.dtsi"
+
+/ {
+ compatible = "renesas,r8a779m8", "renesas,r8a7795";
+};
#address-cells = <2>;
#size-cells = <2>;
+ audio_clk1: audio_clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio_clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#size-cells = <2>;
ranges;
+ ssi0: ssi@10049c00 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x10049c00 0 0x400>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ dmas = <&dmac 0x2655>, <&dmac 0x2656>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@1004a000 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a000 0 0x400>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
+ dmas = <&dmac 0x2659>, <&dmac 0x265a>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@1004a400 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a400 0 0x400>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
+ dmas = <&dmac 0x265f>;
+ dma-names = "rt";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@1004a800 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a800 0 0x400>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
+ dmas = <&dmac 0x2661>, <&dmac 0x2662>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
};
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g044-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_DMAC_ARESETN>,
+ <&cpg R9A07G044_DMAC_RST_ASYNC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
/dts-v1/;
#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g044l2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
+
+&adc {
+ pinctrl-0 = <&adc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /delete-node/ channel@6;
+ /delete-node/ channel@7;
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&pinctrl {
+ adc_pins: adc {
+ pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
+ };
+};
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/*
+ * SSI-WM8978
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer cset name='Left Input Mixer L2 Switch' on
+ * amixer cset name='Right Input Mixer R2 Switch' on
+ * amixer cset name='Headphone Playback Volume' 100
+ * amixer cset name='PCM Volume' 100%
+ * amixer cset name='Input PGA Volume' 25
+ *
+ */
/ {
aliases {
serial0 = &scif0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c3 = &i2c3;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
+
+ audio_mclock: audio_mclock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ snd_rzg2l: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&cpu_dai>;
+ simple-audio-card,frame-master = <&cpu_dai>;
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,widgets = "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "L2", "Mic Bias",
+ "R2", "Mic Bias",
+ "Mic Bias", "Microphone Jack";
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&ssi0>;
+ };
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&audio_mclock>;
+ sound-dai = <&wm8978>;
+ };
+ };
+
+ usb0_vbus_otg: regulator-usb0-vbus-otg {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB0_VBUS_OTG";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&audio_clk1{
+ clock-frequency = <11289600>;
+};
+
+&audio_clk2{
+ clock-frequency = <12288000>;
+};
+
+&canfd {
+ pinctrl-0 = <&can0_pins &can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
};
-&extal_clk {
- clock-frequency = <24000000>;
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-0 = <&sound_clk_pins>;
+ pinctrl-names = "default";
+
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
+ };
+
+ /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
+ can0-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can0_stb";
+ };
+
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
+ };
+
+ /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+ can1-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can1_stb";
+ };
+
+ i2c0_pins: i2c0 {
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ input-enable;
+ };
+
+ i2c1_pins: i2c1 {
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ input-enable;
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
+ };
+
+ sound_clk_pins: sound_clk {
+ pins = "AUDIO_CLK1", "AUDIO_CLK2";
+ input-enable;
+ };
+
+ ssi0_pins: ssi0 {
+ pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
+ <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
+ <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
+ <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
+ };
+
+ usb0_pins: usb0 {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
+ <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+ };
};
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ssi0 {
+ pinctrl-0 = <&ssi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
cpu-supply = <&vdd_arm>;
};
+&csi_dphy {
+ status = "okay";
+};
+
&display_subsystem {
status = "okay";
};
};
};
+&i2c2 {
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ /* These are relatively safe rise/fall times; TODO: measure */
+ i2c-scl-falling-time-ns = <50>;
+ i2c-scl-rising-time-ns = <300>;
+
+ ov5695: ov5695@36 {
+ compatible = "ovti,ov5695";
+ reg = <0x36>;
+ avdd-supply = <&vcc2v8_dvp>;
+ clocks = <&cru SCLK_CIF_OUT>;
+ clock-names = "xvclk";
+ dvdd-supply = <&vcc1v5_dvp>;
+ dovdd-supply = <&vcc1v8_dvp>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cif_clkout_m0>;
+ reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&i2s1_2ch {
status = "okay";
};
vccio6-supply = <&vccio_flash>;
};
+&isp {
+ status = "okay";
+
+ ports {
+ port@0 {
+ mipi_in_ucam: endpoint@0 {
+ reg = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&ucam_out>;
+ };
+ };
+ };
+};
+
+&isp_mmu {
+ status = "okay";
+};
+
&pinctrl {
headphone {
hp_det: hp-det {
};
};
- cpu0_opp_table: cpu0-opp-table {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
status = "disabled";
};
+ csi_dphy: phy@ff2f0000 {
+ compatible = "rockchip,px30-csi-dphy";
+ reg = <0x0 0xff2f0000 0x0 0x4000>;
+ clocks = <&cru PCLK_MIPICSIPHY>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ power-domains = <&power PX30_PD_VI>;
+ resets = <&cru SRST_MIPICSIPHY_P>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
usb20_otg: usb@ff300000 {
compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
"snps,dwc2";
status = "disabled";
};
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
nfc: nand-controller@ff3b0000 {
compatible = "rockchip,px30-nfc";
reg = <0x0 0xff3b0000 0x0 0x4000>;
status = "disabled";
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-200000000 {
status = "disabled";
};
+ vpu: video-codec@ff442000 {
+ compatible = "rockchip,px30-vpu";
+ reg = <0x0 0xff442000 0x0 0x800>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@ff442800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff442800 0x0 0x100>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;
status = "disabled";
};
+ isp: isp@ff4a0000 {
+ compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
+ reg = <0x0 0xff4a0000 0x0 0x8000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp", "mi", "mipi";
+ clocks = <&cru SCLK_ISP>,
+ <&cru ACLK_ISP>,
+ <&cru HCLK_ISP>,
+ <&cru PCLK_ISP>;
+ clock-names = "isp", "aclk", "hclk", "pclk";
+ iommus = <&isp_mmu>;
+ phys = <&csi_dphy>;
+ phy-names = "dphy";
+ power-domains = <&power PX30_PD_VI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ isp_mmu: iommu@ff4a8000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff4a8000 0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power PX30_PD_VI>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ };
+
qos_gmac: qos@ff518000 {
compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff518000 0x0 0x20>;
};
};
+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
lcdc {
lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
rockchip,pins =
};
};
- cpu0_opp_table: cpu0-opp-table {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
status = "disabled";
};
+ sfc: spi@ff4c0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff4c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
};
};
+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ <3 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <3 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <3 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
gmac {
rmii_pins: rmii-pins {
rockchip,pins =
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
assigned-clock-rate = <50000000>;
assigned-clocks = <&cru SCLK_MAC2PHY>;
- clock_in_out = "output";
status = "okay";
};
};
&hdmi {
- ddc-i2c-scl-high-time-ns = <9625>;
- ddc-i2c-scl-low-time-ns = <10000>;
status = "okay";
};
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
- vin-supply = <&vccsys>;
+ regulator-boot-on;
+ vin-supply = <&usb_midu>;
};
};
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
+ vcc8-supply = <&vccsys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-suspend-microvolt = <3000000>;
};
};
+
+ usb_midu: BOOST {
+ regulator-name = "usb_midu";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
rk817_codec: codec {
status = "okay";
};
+&sfc {
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
&tsadc {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "rk3328-roc-cc.dts"
+
+/ {
+ model = "Firefly ROC-RK3328-PC";
+ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1750000>;
+
+ /* This button is unpopulated out of the factory. */
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ linux,rc-map-name = "rc-khadas";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_en>, <&wifi_host_wake>;
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&codec {
+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
+&pinctrl {
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmcio {
+ sdio_per_pin: sdio-per-pin {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wifi {
+ wifi_en: wifi-en {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
+ };
+
+ bt_rst: bt-rst {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_en: bt-en {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmic_int_l {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&rk805 {
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&usb20_host_drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&vcc_host1_5v {
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+};
+
+&vcc_sdio {
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_per_pin>;
+};
&spi0 {
status = "okay";
- spiflash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
gpu: gpu@ff300000 {
compatible = "rockchip,rk3328-mali", "arm,mali-450";
- reg = <0x0 0xff300000 0x0 0x40000>;
+ reg = <0x0 0xff300000 0x0 0x30000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
compatible = "rockchip,iommu";
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "h265e_mmu";
clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vepu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff350800 0x0 0x40>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff373f00 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
i2c-parent = <&i2c1>;
mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
- /* Q7_GPO_I2C */
- i2c@0 {
+ /* Q7_GP0_I2C */
+ i2c_gp0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* Q7_SMB */
- i2c@1 {
+ i2c_smb: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
/* Q7_LVDS_BLC_I2C */
- i2c@0 {
+ i2c_lvds_blc: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
- /* Q7_GP2_I2C */
- i2c@1 {
+ /* Q7_GP2_I2C = LVDS_DID_CLK/DAT */
+ i2c_gp2: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc33_io>;
- vqmmc-supply = <&vcc18_io>;
+ vqmmc-supply = <&vcc_18>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
status = "okay";
regulator-boot-on;
};
- vcc18_io: LDO_REG4 {
- regulator-name = "vcc18_io";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- };
-
vdd10_video: LDO_REG6 {
regulator-name = "vdd10_video";
regulator-min-microvolt = <1000000>;
regulator-boot-on;
};
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ };
+
vcc18_video: LDO_REG8 {
regulator-name = "vcc18_video";
regulator-min-microvolt = <1800000>;
status = "okay";
};
+/* The RK3368-uQ7 "Lion" has most IO voltages hardwired to 3.3V. */
+&io_domains {
+ audio-supply = <&vcc33_io>;
+ dvp-supply = <&vcc33_io>;
+ flash0-supply = <&vcc_18>;
+ gpio30-supply = <&vcc33_io>;
+ gpio1830-supply = <&vcc33_io>;
+ sdcard-supply = <&vcc33_io>;
+ wifi-supply = <&vcc33_io>;
+ status = "okay";
+};
+
&pinctrl {
leds {
module_led_pins: module-led-pins {
};
};
+&pmu_io_domains {
+ pmu-supply = <&vcc33_io>;
+ vop-supply = <&vcc33_io>;
+ status = "okay";
+};
+
&spi1 {
status = "okay";
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
reg = <0x0 0xff914000 0x0 0x100>,
<0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp_mmu";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
reg = <0x0 0xff9a0440 0x0 0x40>,
<0x0 0xff9a0480 0x0 0x40>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
reg = <0x0 0xff9a0800 0x0 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vepu_mmu", "vdpu_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
};
};
+&gpio0 {
+ gpio-line-names = /* GPIO0 A 0-7 */
+ "AP_RTC_CLK_IN",
+ "EC_AP_INT_L",
+ "PP1800_AUDIO_EN",
+ "BT_HOST_WAKE_L",
+ "WLAN_MODULE_PD_L",
+ "H1_INT_OD_L",
+ "CENTERLOGIC_DVS_PWM",
+ "",
+
+ /* GPIO0 B 0-4 */
+ "WIFI_HOST_WAKE_L",
+ "PMUIO2_33_18_L",
+ "PP1500_EN",
+ "AP_EC_WARM_RESET_REQ",
+ "PP3000_EN";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A 0-7 */
+ "",
+ "",
+ "SPK_PA_EN",
+ "",
+ "TRACKPAD_INT_L",
+ "AP_EC_S3_S0_L",
+ "AP_EC_OVERTEMP",
+ "AP_SPI_FLASH_MISO",
+
+ /* GPIO1 B 0-7 */
+ "AP_SPI_FLASH_MOSI_R",
+ "AP_SPI_FLASH_CLK_R",
+ "AP_SPI_FLASH_CS_L_R",
+ "WLAN_MODULE_RESET_L",
+ "WIFI_DISABLE_L",
+ "MIC_INT",
+ "",
+ "AP_I2C_DVS_SDA",
+
+ /* GPIO1 C 0-7 */
+ "AP_I2C_DVS_SCL",
+ "AP_BL_EN",
+ /*
+ * AP_FLASH_WP is crossystem ABI. Schematics call it
+ * AP_FW_WP or CPU1_FW_WP, depending on the variant.
+ */
+ "AP_FLASH_WP",
+ "LITCPU_DVS_PWM",
+ "AP_I2C_AUDIO_SDA",
+ "AP_I2C_AUDIO_SCL",
+ "",
+ "HEADSET_INT_L";
+};
+
+&gpio2 {
+ gpio-line-names = /* GPIO2 A 0-7 */
+ "",
+ "",
+ "SD_IO_PWR_EN",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO2 B 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO2 C 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "AP_SPI_EC_MISO",
+ "AP_SPI_EC_MOSI",
+ "AP_SPI_EC_CLK",
+ "AP_SPI_EC_CS_L",
+
+ /* GPIO2 D 0-4 */
+ "BT_DEV_WAKE_L",
+ "",
+ "WIFI_PCIE_CLKREQ_L",
+ "WIFI_PERST_L",
+ "SD_PWR_3000_1800_L";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "AP_SPI_TPM_MISO",
+ "AP_SPI_TPM_MOSI_R",
+ "AP_SPI_TPM_CLK_R",
+ "AP_SPI_TPM_CS_L_R",
+
+ /* GPIO3 B 0-7 */
+ "EC_IN_RW",
+ "",
+ "AP_I2C_TP_SDA",
+ "AP_I2C_TP_SCL",
+ "AP_I2C_TP_PU_EN",
+ "TOUCH_INT_L",
+ "",
+ "",
+
+ /* GPIO3 C 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO3 D 0-7 */
+ "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI_0",
+ "I2S0_SDI_1",
+ "",
+ "I2S0_SDO_1",
+ "I2S0_SDO_0";
+};
+
+&gpio4 {
+ gpio-line-names = /* GPIO4 A 0-7 */
+ "I2S_MCLK",
+ "AP_I2C_MIC_SDA",
+ "AP_I2C_MIC_SCL",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO4 B 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO4 C 0-7 */
+ "AP_I2C_TS_SDA",
+ "AP_I2C_TS_SCL",
+ "GPU_DVS_PWM",
+ "UART_DBG_TX_AP_RX",
+ "UART_AP_TX_DBG_RX",
+ "",
+ "BIGCPU_DVS_PWM",
+ "EDP_HPD_3V0",
+
+ /* GPIO4 D 0-5 */
+ "SD_CARD_DET_L",
+ "USB_DP_HPD",
+ "TOUCH_RESET_L",
+ "PP3300_DISP_EN",
+ "",
+ "SD_SLOT_PWR_EN";
+};
+
ap_i2c_mic: &i2c1 {
status = "okay";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Gru-Scarlet Rev5+ (SKU-0) board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "rk3399-gru-scarlet.dtsi"
+
+/ {
+ model = "Google Scarlet";
+ compatible = "google,scarlet-rev15-sku0", "google,scarlet-rev15",
+ "google,scarlet-rev14-sku0", "google,scarlet-rev14",
+ "google,scarlet-rev13-sku0", "google,scarlet-rev13",
+ "google,scarlet-rev12-sku0", "google,scarlet-rev12",
+ "google,scarlet-rev11-sku0", "google,scarlet-rev11",
+ "google,scarlet-rev10-sku0", "google,scarlet-rev10",
+ "google,scarlet-rev9-sku0", "google,scarlet-rev9",
+ "google,scarlet-rev8-sku0", "google,scarlet-rev8",
+ "google,scarlet-rev7-sku0", "google,scarlet-rev7",
+ "google,scarlet-rev6-sku0", "google,scarlet-rev6",
+ "google,scarlet-rev5-sku0", "google,scarlet-rev5",
+ "google,scarlet", "google,gru", "rockchip,rk3399";
+};
+
+&mipi_panel {
+ compatible = "innolux,p097pfg";
+ avdd-supply = <&ppvarp_lcd>;
+ avee-supply = <&ppvarn_lcd>;
+};
+
+&pci_rootport {
+ wifi@0,0 {
+ compatible = "qcom,ath10k";
+ reg = <0x00010000 0x0 0x00000000 0x0 0x00000000>,
+ <0x03010010 0x0 0x00000000 0x0 0x00200000>;
+ qcom,ath10k-calibration-variant = "GO_DUMO";
+ };
+};
<400000000>;
};
+&gpio0 {
+ gpio-line-names = /* GPIO0 A 0-7 */
+ "CLK_32K_AP",
+ "EC_IN_RW_OD",
+ "SPK_PA_EN",
+ "WLAN_PERST_1V8_L",
+ "WLAN_PD_1V8_L",
+ "WLAN_RF_KILL_1V8_L",
+ "BIGCPU_DVS_PWM",
+ "SD_CD_L_JTAG_EN",
+
+ /* GPIO0 B 0-5 */
+ "BT_EN_BT_RF_KILL_1V8_L",
+ "PMUIO2_33_18_L_PP3300_S0_EN",
+ "TOUCH_RESET_L",
+ "AP_EC_WARM_RESET_REQ",
+ "PEN_RESET_L",
+ /*
+ * AP_FLASH_WP_L is crossystem ABI. Schematics call
+ * it AP_FLASH_WP_R_ODL.
+ */
+ "AP_FLASH_WP_L";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A 0-7 */
+ "PEN_INT_ODL",
+ "PEN_EJECT_ODL",
+ "BT_HOST_WAKE_1V8_L",
+ "WLAN_HOST_WAKE_1V8_L",
+ "TOUCH_INT_ODL",
+ "AP_EC_S3_S0_L",
+ "AP_EC_OVERTEMP",
+ "AP_SPI_FLASH_MISO",
+
+ /* GPIO1 B 0-7 */
+ "AP_SPI_FLASH_MOSI_R",
+ "AP_SPI_FLASH_CLK_R",
+ "AP_SPI_FLASH_CS_L_R",
+ "SD_CARD_DET_ODL",
+ "",
+ "AP_EXPANSION_IO1",
+ "AP_EXPANSION_IO2",
+ "AP_I2C_DISP_SDA",
+
+ /* GPIO1 C 0-7 */
+ "AP_I2C_DISP_SCL",
+ "H1_INT_ODL",
+ "EC_AP_INT_ODL",
+ "LITCPU_DVS_PWM",
+ "AP_I2C_AUDIO_SDA",
+ "AP_I2C_AUDIO_SCL",
+ "AP_EXPANSION_IO3",
+ "HEADSET_INT_ODL",
+
+ /* GPIO1 D0 */
+ "AP_EXPANSION_IO4";
+};
+
+&gpio2 {
+ gpio-line-names = /* GPIO2 A 0-7 */
+ "AP_I2C_PEN_SDA",
+ "AP_I2C_PEN_SCL",
+ "SD_IO_PWR_EN",
+ "UCAM_RST_L",
+ "PP1250_CAM_EN",
+ "WCAM_RST_L",
+ "AP_EXPANSION_IO5",
+ "AP_I2C_CAM_SDA",
+
+ /* GPIO2 B 0-7 */
+ "AP_I2C_CAM_SCL",
+ "AP_H1_SPI_MISO",
+ "AP_H1_SPI_MOSI",
+ "AP_H1_SPI_CLK",
+ "AP_H1_SPI_CS_L",
+ "",
+ "",
+ "",
+
+ /* GPIO2 C 0-7 */
+ "UART_EXPANSION_TX_AP_RX",
+ "UART_AP_TX_EXPANSION_RX",
+ "UART_EXPANSION_RTS_AP_CTS",
+ "UART_AP_RTS_EXPANSION_CTS",
+ "AP_SPI_EC_MISO",
+ "AP_SPI_EC_MOSI",
+ "AP_SPI_EC_CLK",
+ "AP_SPI_EC_CS_L",
+
+ /* GPIO2 D 0-4 */
+ "PP2800_CAM_EN",
+ "CLK_24M_CAM",
+ "WLAN_PCIE_CLKREQ_1V8_L",
+ "",
+ "SD_PWR_3000_1800_L";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO3 B 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO3 C 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO3 D 0-7 */
+ "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI_0",
+ "STRAP_LCDBIAS_L",
+ "STRAP_FEATURE_1",
+ "STRAP_FEATURE_2",
+ "I2S0_SDO_0";
+};
+
+&gpio4 {
+ gpio-line-names = /* GPIO4 A 0-7 */
+ "I2S_MCLK",
+ "AP_I2C_EXPANSION_SDA",
+ "AP_I2C_EXPANSION_SCL",
+ "DMIC_EN",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO4 B 0-7 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ /* GPIO4 C 0-7 */
+ "AP_I2C_TS_SDA",
+ "AP_I2C_TS_SCL",
+ "GPU_DVS_PWM",
+ "UART_DBG_TX_AP_RX",
+ "UART_AP_TX_DBG_RX",
+ "BL_EN",
+ "BL_PWM",
+ "",
+
+ /* GPIO4 D 0-5 */
+ "",
+ "DISPLAY_RST_L",
+ "",
+ "PPVARP_LCD_EN",
+ "PPVARN_LCD_EN",
+ "SD_SLOT_PWR_EN";
+};
+
&i2c_tunnel {
google,remote-bus = <0>;
};
vpcie0v9-supply = <&pp900_pcie>;
pci_rootport: pcie@0,0 {
- reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
+ reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
- spiflash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
aliases {
mmc0 = &sdmmc;
mmc1 = &sdhci;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi5 = &spi5;
};
avdd_0v9_s0: avdd-0v9-s0 {
vin-supply = <&vcc3v3_sys_s3>;
};
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
status = "okay";
};
+&spi1 {
+ status = "okay";
+
+ spiflash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <25000000>;
+ status = "okay";
+ m25p,fast-read;
+ };
+};
+
+/* UEXT connector */
+&spi2 {
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+};
+
&tcphy1 {
/* phy for &usbdrd_dwc3_1 */
status = "okay";
};
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
&u2phy1 {
status = "okay";
*/
/ {
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
};
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
*/
/ {
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
};
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
};
};
-&cdn_dp {
- status = "okay";
-};
-
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
connector {
compatible = "usb-c-connector";
- data-role = "host";
+ data-role = "dual";
label = "USB-C";
op-sink-microwatt = <1000000>;
power-role = "dual";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3399-roc-pc.dtsi"
+
+/*
+ * Notice:
+ * 1. rk3399-roc-pc-plus is powered by dc_12v directly.
+ * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is coresponding
+ * to vcc_vbus_typec1 in rk3399-roc-pc.
+ * For simplicity, reserve the node name of vcc_vbus_typec1.
+ * 3. vcc5v0_host is actually 2 regulators (host0, 1) controlled by the same gpio.
+ */
+
+/delete-node/ &fusb1;
+/delete-node/ &hub_rst;
+/delete-node/ &mp8859;
+/delete-node/ &vcc_sys_en;
+/delete-node/ &vcc_vbus_typec0;
+/delete-node/ &yellow_led;
+
+/ {
+ model = "Firefly ROC-RK3399-PC-PLUS Board";
+ compatible = "firefly,roc-rk3399-pc-plus", "rockchip,rk3399";
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ es8388-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det_pin>;
+ simple-audio-card,name = "rockchip,es8388-codec";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ simple-audio-card,routing =
+ "LINPUT1", "Mic Jack",
+ "Headphone Amp INL", "LOUT2",
+ "Headphone Amp INR", "ROUT2",
+ "Headphones", "Headphone Amp OUTL",
+ "Headphones", "Headphone Amp OUTR";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,aux-devs = <&headphones_amp>;
+ simple-audio-card,pin-switches = "Headphones";
+
+ simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+ };
+
+ gpio-fan {
+ #cooling-cells = <2>;
+ compatible = "gpio-fan";
+ gpio-fan,speed-map = <0 0 3000 1>;
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ };
+
+ /delete-node/ gpio-keys;
+
+ /* not amplifier, used as switcher only */
+ headphones_amp: headphones-amp {
+ compatible = "simple-audio-amplifier";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ear_ctl_pin>;
+ enable-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Headphone Amp";
+ VCC-supply = <&vcca3v0_codec>;
+ };
+
+ ir-receiver {
+ linux,rc-map-name = "rc-khadas";
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
+ };
+};
+
+&fusb0 {
+ vbus-supply = <&vcc_vbus_typec1>;
+};
+
+&i2c0 {
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA5 IRQ_TYPE_EDGE_FALLING>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ };
+};
+
+&i2c1 {
+ es8388: es8388@11 {
+ compatible = "everest,es8388";
+ reg = <0x11>;
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+/* <4 RK_PA0 1 &pcfg_pull_none> is used as i2s_8ch_mclk_pin */
+&i2s0_8ch_bus {
+ rockchip,pins =
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ <3 RK_PD6 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>;
+};
+
+&i2s1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>;
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+};
+
+&pinctrl {
+ es8388 {
+ ear_ctl_pin: ear-ctl-pin {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
+ hp_det_pin: hp-det-pin {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ i2s1 {
+ i2s_8ch_mclk_pin: i2s-8ch-mclk-pin {
+ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ phy-supply = <&vcc_vbus_typec1>;
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&vcc_sys {
+ /* vcc_sys is fixed, not controlled by any gpio */
+ /delete-property/ gpio;
+ /delete-property/ pinctrl-names;
+ /delete-property/ pinctrl-0;
+};
+
+&vcc5v0_host {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+};
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
+ sound {
+ compatible = "audio-graph-card";
+ label = "Analog";
+ dais = <&i2s0_p0>;
+ };
+
+ sound-dit {
+ compatible = "audio-graph-card";
+ label = "SPDIF";
+ dais = <&spdif_p0>;
+ };
+
+ spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port {
+ dit_p0_0: endpoint {
+ remote-endpoint = <&spdif_p0_0>;
+ };
+ };
+ };
+
vcc12v_dcin: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
+
+ es8316: codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_p0_0>;
+ };
+ };
+ };
};
&i2c3 {
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";
+
+ i2s0_p0: port {
+ i2s0_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
};
&i2s1 {
status = "okay";
};
+&spdif {
+
+ spdif_p0: port {
+ spdif_p0_0: endpoint {
+ remote-endpoint = <&dit_p0_0>;
+ };
+ };
+};
+
&tcphy0 {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
+ */
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-op1-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi 4A+";
+ compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
+ */
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-op1-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi 4B+";
+ compatible = "radxa,rockpi4b-plus", "radxa,rockpi4", "rockchip,rk3399";
+
+ aliases {
+ mmc2 = &sdio0;
+ };
+};
+
+&sdio0 {
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ };
+};
fan: pwm-fan {
compatible = "pwm-fan";
+ cooling-levels = <0 100 150 200 255>;
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
cpu-supply = <&vdd_cpu_b>;
};
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&emmc_phy {
status = "okay";
};
status = "disabled";
};
+ debug@fe430000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe430000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l0>;
+ };
+
+ debug@fe432000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe432000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l1>;
+ };
+
+ debug@fe434000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe434000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l2>;
+ };
+
+ debug@fe436000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe436000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_L>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_l3>;
+ };
+
+ debug@fe610000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe610000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_B>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_b0>;
+ };
+
+ debug@fe710000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfe710000 0 0x1000>;
+ clocks = <&cru PCLK_COREDBG_B>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu_b1>;
+ };
+
usbdrd3_0: usb@fe800000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
compatible = "rockchip,iommu";
reg = <0x0 0xff650800 0x0 0x40>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VDU>;
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
compatible = "rockchip,iommu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPL>;
compatible = "rockchip,iommu";
reg = <0x0 0xff903f00 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPB>;
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp0_mmu";
clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
};
+ isp1: isp1@ff920000 {
+ compatible = "rockchip,rk3399-cif-isp";
+ reg = <0x0 0xff920000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_ISP1>,
+ <&cru ACLK_ISP1_WRAPPER>,
+ <&cru HCLK_ISP1_WRAPPER>;
+ clock-names = "isp", "aclk", "hclk";
+ iommus = <&isp1_mmu>;
+ phys = <&mipi_dsi1>;
+ phy-names = "dphy";
+ power-domains = <&power RK3399_PD_ISP1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp1_mmu";
clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
+ #phy-cells = <0>;
status = "disabled";
ports {
};
};
+ cif {
+ cif_clkin: cif-clkin {
+ rockchip,pins =
+ <2 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ cif_clkouta: cif-clkouta {
+ rockchip,pins =
+ <2 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
edp {
edp_hpd: edp-hpd {
rockchip,pins =
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 Quartz64-A Board";
+ compatible = "pine64,quartz64-a", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ fan: gpio_fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0
+ 4500 1>;
+ #cooling-cells = <2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-work {
+ label = "work-led";
+ default-state = "off";
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_enable_h>;
+ retain-state-suspended;
+ };
+
+ led-diy {
+ label = "diy-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&diy_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ vcc12v_dcin: vcc12v_dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* vbus feeds the rk817 usb input.
+ * With no battery attached, also feeds vcc_bat+
+ * via ON/OFF_BAT jumper
+ */
+ vbus: vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0_usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_sd: vcc3v3_sd {
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_sd_h>;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ /* sourced from vbus and vcc_bat+ via rk817 sw5 */
+ vcc_sys: vcc_sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4400000>;
+ regulator-max-microvolt = <4400000>;
+ vin-supply = <&vbus>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_thermal {
+ trips {
+ cpu_hot: cpu_hot {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_3v3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&dcdc_boost>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_logic";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc2v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ dcdc_boost: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ otg_switch: OTG_SWITCH {
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ work_led_enable_h: work-led-enable-h {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_enable_h: diy-led-enable-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ vcc_sd {
+ vcc_sd_h: vcc-sd-h {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk817 1>;
+ clock-names = "lpo";
+ device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x.dtsi"
+
+/ {
+ compatible = "rockchip,rk3566";
+};
+
+&power {
+ power-domain@RK3568_PD_PIPE {
+ reg = <RK3568_PD_PIPE>;
+ clocks = <&cru PCLK_PIPE>;
+ pm_qos = <&qos_pcie2x1>,
+ <&qos_sata1>,
+ <&qos_sata2>,
+ <&qos_usb3_0>,
+ <&qos_usb3_1>;
+ #power-domain-cells = <0>;
+ };
+};
model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
};
};
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
status = "okay";
};
<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
};
};
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadc_pin: tsadc-pin {
+ rockchip,pins =
+ /* tsadc_pin */
+ <0 RK_PA1 0 &pcfg_pull_none>;
+ };
+ };
};
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
-#include <dt-bindings/clock/rk3568-cru.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/thermal/thermal.h>
+#include "rk356x.dtsi"
/ {
compatible = "rockchip,rk3568";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- serial6 = &uart6;
- serial7 = &uart7;
- serial8 = &uart8;
- serial9 = &uart9;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x0>;
- clocks = <&scmi_clk 0>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu1: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x100>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu2: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x200>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu3: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x300>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
- };
-
- cpu0_opp_table: cpu0-opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000 900000 1150000>;
- clock-latency-ns = <40000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000 900000 1150000>;
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000 900000 1150000>;
- opp-suspend;
- };
-
- opp-1104000000 {
- opp-hz = /bits/ 64 <1104000000>;
- opp-microvolt = <900000 900000 1150000>;
- };
-
- opp-1416000000 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <900000 900000 1150000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <975000 975000 1150000>;
- };
+ qos_pcie3x1: qos@fe190080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190080 0x0 0x20>;
+ };
+
+ qos_pcie3x2: qos@fe190100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190100 0x0 0x20>;
+ };
+
+ qos_sata0: qos@fe190200 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190200 0x0 0x20>;
+ };
+
+ gmac0: ethernet@fe2a0000 {
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
+ <&cru PCLK_XPCS>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_refout",
+ "aclk_mac", "pclk_mac",
+ "clk_mac_speed", "ptp_ref",
+ "pclk_xpcs";
+ resets = <&cru SRST_A_GMAC0>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1050000 1050000 1150000>;
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
};
- opp-1992000000 {
- opp-hz = /bits/ 64 <1992000000>;
- opp-microvolt = <1150000 1150000 1150000>;
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
};
- };
- firmware {
- scmi: scmi {
- compatible = "arm,scmi-smc";
- arm,smc-id = <0x82000010>;
- shmem = <&scmi_shmem>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
};
- };
-
- pmu {
- compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
- arm,no-tick-in-suspend;
- };
-
- xin24m: xin24m {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- xin32k: xin32k {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- pinctrl-0 = <&clk32k_out0>;
- pinctrl-names = "default";
- #clock-cells = <0>;
- };
-
- sram@10f000 {
- compatible = "mmio-sram";
- reg = <0x0 0x0010f000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x0010f000 0x100>;
-
- scmi_shmem: sram@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x100>;
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
};
};
+};
- gic: interrupt-controller@fd400000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
- <0x0 0xfd460000 0 0x80000>; /* GICR */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- mbi-alias = <0x0 0xfd100000>;
- mbi-ranges = <296 24>;
- msi-controller;
- };
-
- pmugrf: syscon@fdc20000 {
- compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfdc20000 0x0 0x10000>;
- };
-
- grf: syscon@fdc60000 {
- compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfdc60000 0x0 0x10000>;
- };
-
- pmucru: clock-controller@fdd00000 {
- compatible = "rockchip,rk3568-pmucru";
- reg = <0x0 0xfdd00000 0x0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- cru: clock-controller@fdd20000 {
- compatible = "rockchip,rk3568-cru";
- reg = <0x0 0xfdd20000 0x0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- i2c0: i2c@fdd40000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfdd40000 0x0 0x1000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart0: serial@fdd50000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfdd50000 0x0 0x100>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 0>, <&dmac0 1>;
- pinctrl-0 = <&uart0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- sdmmc2: mmc@fe000000 {
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe000000 0x0 0x4000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
- <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- resets = <&cru SRST_SDMMC2>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sdmmc0: mmc@fe2b0000 {
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2b0000 0x0 0x4000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
- <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- resets = <&cru SRST_SDMMC0>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sdmmc1: mmc@fe2c0000 {
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
- <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- resets = <&cru SRST_SDMMC1>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sdhci: mmc@fe310000 {
- compatible = "rockchip,rk3568-dwcmshc";
- reg = <0x0 0xfe310000 0x0 0x10000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
- assigned-clock-rates = <200000000>, <24000000>;
- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
- <&cru TCLK_EMMC>;
- clock-names = "core", "bus", "axi", "block", "timer";
- status = "disabled";
- };
-
- dmac0: dmac@fe530000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfe530000 0x0 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_BUS>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- dmac1: dmac@fe550000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfe550000 0x0 0x4000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_BUS>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- i2c1: i2c@fe5a0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c1_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@fe5b0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5b0000 0x0 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c2m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@fe5c0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5c0000 0x0 0x1000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c3m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@fe5d0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5d0000 0x0 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c4m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@fe5e0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5e0000 0x0 0x1000>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c5m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart1: serial@fe650000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe650000 0x0 0x100>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 2>, <&dmac0 3>;
- pinctrl-0 = <&uart1m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart2: serial@fe660000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe660000 0x0 0x100>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 4>, <&dmac0 5>;
- pinctrl-0 = <&uart2m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart3: serial@fe670000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe670000 0x0 0x100>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 6>, <&dmac0 7>;
- pinctrl-0 = <&uart3m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart4: serial@fe680000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe680000 0x0 0x100>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 8>, <&dmac0 9>;
- pinctrl-0 = <&uart4m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart5: serial@fe690000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe690000 0x0 0x100>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 10>, <&dmac0 11>;
- pinctrl-0 = <&uart5m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart6: serial@fe6a0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6a0000 0x0 0x100>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 12>, <&dmac0 13>;
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart7: serial@fe6b0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6b0000 0x0 0x100>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 14>, <&dmac0 15>;
- pinctrl-0 = <&uart7m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart8: serial@fe6c0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6c0000 0x0 0x100>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 16>, <&dmac0 17>;
- pinctrl-0 = <&uart8m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart9: serial@fe6d0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6d0000 0x0 0x100>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 18>, <&dmac0 19>;
- pinctrl-0 = <&uart9m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
+&cpu0_opp_table {
+ opp-1992000000 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1150000 1150000 1150000>;
};
+};
- pinctrl: pinctrl {
- compatible = "rockchip,rk3568-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@fdd60000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfdd60000 0x0 0x100>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru PCLK_GPIO0>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@fe740000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe740000 0x0 0x100>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@fe750000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe750000 0x0 0x100>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@fe760000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe760000 0x0 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@fe770000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe770000 0x0 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+&power {
+ power-domain@RK3568_PD_PIPE {
+ reg = <RK3568_PD_PIPE>;
+ clocks = <&cru PCLK_PIPE>;
+ pm_qos = <&qos_pcie2x1>,
+ <&qos_pcie3x1>,
+ <&qos_pcie3x2>,
+ <&qos_sata0>,
+ <&qos_sata1>,
+ <&qos_sata2>,
+ <&qos_usb3_0>,
+ <&qos_usb3_1>;
+ #power-domain-cells = <0>;
};
};
-
-#include "rk3568-pinctrl.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3568-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3568-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ clocks = <&scmi_clk 0>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ opp-suspend;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <975000 975000 1150000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1050000 1050000 1150000>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ arm,no-tick-in-suspend;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ pinctrl-0 = <&clk32k_out0>;
+ pinctrl-names = "default";
+ #clock-cells = <0>;
+ };
+
+ sram@10f000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x0010f000 0x100>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ gic: interrupt-controller@fd400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+ <0x0 0xfd460000 0 0x80000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ mbi-alias = <0x0 0xfd410000>;
+ mbi-ranges = <296 24>;
+ msi-controller;
+ };
+
+ pmugrf: syscon@fdc20000 {
+ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
+ reg = <0x0 0xfdc20000 0x0 0x10000>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rk3568-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ grf: syscon@fdc60000 {
+ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfdc60000 0x0 0x10000>;
+ };
+
+ pmucru: clock-controller@fdd00000 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0x0 0xfdd00000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@fdd20000 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0x0 0xfdd20000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+ assigned-clock-rates = <1200000000>, <200000000>;
+ rockchip,grf = <&grf>;
+ };
+
+ i2c0: i2c@fdd40000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfdd40000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@fdd50000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfdd50000 0x0 0x100>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 0>, <&dmac0 1>;
+ pinctrl-0 = <&uart0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ pmu: power-management@fdd90000 {
+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xfdd90000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3568-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_GPU */
+ power-domain@RK3568_PD_GPU {
+ reg = <RK3568_PD_GPU>;
+ clocks = <&cru ACLK_GPU_PRE>,
+ <&cru PCLK_GPU_PRE>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@RK3568_PD_VI {
+ reg = <RK3568_PD_VI>;
+ clocks = <&cru HCLK_VI>,
+ <&cru PCLK_VI>;
+ pm_qos = <&qos_isp>,
+ <&qos_vicap0>,
+ <&qos_vicap1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_VO {
+ reg = <RK3568_PD_VO>;
+ clocks = <&cru HCLK_VO>,
+ <&cru PCLK_VO>,
+ <&cru ACLK_VOP_PRE>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_vop_m0>,
+ <&qos_vop_m1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RGA {
+ reg = <RK3568_PD_RGA>;
+ clocks = <&cru HCLK_RGA_PRE>,
+ <&cru PCLK_RGA_PRE>;
+ pm_qos = <&qos_ebc>,
+ <&qos_iep>,
+ <&qos_jpeg_dec>,
+ <&qos_jpeg_enc>,
+ <&qos_rga_rd>,
+ <&qos_rga_wr>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_VPU {
+ reg = <RK3568_PD_VPU>;
+ clocks = <&cru HCLK_VPU_PRE>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RKVDEC {
+ clocks = <&cru HCLK_RKVDEC_PRE>;
+ reg = <RK3568_PD_RKVDEC>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3568_PD_RKVENC {
+ reg = <RK3568_PD_RKVENC>;
+ clocks = <&cru HCLK_RKVENC_PRE>;
+ pm_qos = <&qos_rkvenc_rd_m0>,
+ <&qos_rkvenc_rd_m1>,
+ <&qos_rkvenc_wr_m0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ sdmmc2: mmc@fe000000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
+ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC2>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@fe010000 {
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
+ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_refout",
+ "aclk_mac", "pclk_mac",
+ "clk_mac_speed", "ptp_ref";
+ resets = <&cru SRST_A_GMAC1>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ qos_gpu: qos@fe128000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe128000 0x0 0x20>;
+ };
+
+ qos_rkvenc_rd_m0: qos@fe138080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138080 0x0 0x20>;
+ };
+
+ qos_rkvenc_rd_m1: qos@fe138100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138100 0x0 0x20>;
+ };
+
+ qos_rkvenc_wr_m0: qos@fe138180 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe138180 0x0 0x20>;
+ };
+
+ qos_isp: qos@fe148000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148000 0x0 0x20>;
+ };
+
+ qos_vicap0: qos@fe148080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148080 0x0 0x20>;
+ };
+
+ qos_vicap1: qos@fe148100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe148100 0x0 0x20>;
+ };
+
+ qos_vpu: qos@fe150000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe150000 0x0 0x20>;
+ };
+
+ qos_ebc: qos@fe158000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158000 0x0 0x20>;
+ };
+
+ qos_iep: qos@fe158100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158100 0x0 0x20>;
+ };
+
+ qos_jpeg_dec: qos@fe158180 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158180 0x0 0x20>;
+ };
+
+ qos_jpeg_enc: qos@fe158200 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158200 0x0 0x20>;
+ };
+
+ qos_rga_rd: qos@fe158280 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158280 0x0 0x20>;
+ };
+
+ qos_rga_wr: qos@fe158300 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe158300 0x0 0x20>;
+ };
+
+ qos_npu: qos@fe180000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe180000 0x0 0x20>;
+ };
+
+ qos_pcie2x1: qos@fe190000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190000 0x0 0x20>;
+ };
+
+ qos_sata1: qos@fe190280 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190280 0x0 0x20>;
+ };
+
+ qos_sata2: qos@fe190300 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190300 0x0 0x20>;
+ };
+
+ qos_usb3_0: qos@fe190380 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190380 0x0 0x20>;
+ };
+
+ qos_usb3_1: qos@fe190400 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe190400 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@fe198000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe198000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@fe1a8000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8000 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@fe1a8080 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8080 0x0 0x20>;
+ };
+
+ qos_vop_m1: qos@fe1a8100 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
+ };
+
+ sdmmc0: mmc@fe2b0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC0>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@fe2c0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC1>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdhci: mmc@fe310000 {
+ compatible = "rockchip,rk3568-dwcmshc";
+ reg = <0x0 0xfe310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
+ dmac0: dmac@fe530000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfe530000 0x0 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_BUS>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ dmac1: dmac@fe550000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfe550000 0x0 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_BUS>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ i2c1: i2c@fe5a0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe5b0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe5c0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe5d0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5d0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@fe5e0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5e0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@fe600000 {
+ compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
+ reg = <0x0 0xfe600000 0x0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+ clock-names = "tclk", "pclk";
+ };
+
+ uart1: serial@fe650000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe650000 0x0 0x100>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 2>, <&dmac0 3>;
+ pinctrl-0 = <&uart1m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@fe660000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe660000 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 4>, <&dmac0 5>;
+ pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@fe670000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe670000 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 6>, <&dmac0 7>;
+ pinctrl-0 = <&uart3m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@fe680000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe680000 0x0 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 8>, <&dmac0 9>;
+ pinctrl-0 = <&uart4m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@fe690000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe690000 0x0 0x100>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 10>, <&dmac0 11>;
+ pinctrl-0 = <&uart5m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart6: serial@fe6a0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 12>, <&dmac0 13>;
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart7: serial@fe6b0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 14>, <&dmac0 15>;
+ pinctrl-0 = <&uart7m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart8: serial@fe6c0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 16>, <&dmac0 17>;
+ pinctrl-0 = <&uart8m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart9: serial@fe6d0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6d0000 0x0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 18>, <&dmac0 19>;
+ pinctrl-0 = <&uart9m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ thermal_zones: thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+ };
+ };
+
+ tsadc: tsadc@fe710000 {
+ compatible = "rockchip,rk3568-tsadc";
+ reg = <0x0 0xfe710000 0x0 0x100>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
+ assigned-clock-rates = <17000000>, <700000>;
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
+ <&cru SRST_TSADCPHY>;
+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <95000>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&tsadc_pin>;
+ pinctrl-1 = <&tsadc_shutorg>;
+ pinctrl-2 = <&tsadc_pin>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ saradc: saradc@fe720000 {
+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
+ reg = <0x0 0xfe720000 0x0 0x100>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3568-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@fdd60000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfdd60000 0x0 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@fe740000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe740000 0x0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@fe750000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe750000 0x0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@fe760000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe760000 0x0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@fe770000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe770000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3568-pinctrl.dtsi"
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
-
dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
clocks = <&k3_clks 53 0>;
clock-names = "fck";
};
+
+ icssg0: icssg@30000000 {
+ compatible = "ti,am642-icssg";
+ reg = <0x00 0x30000000 0x00 0x80000>;
+ power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x30000000 0x80000>;
+
+ icssg0_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1", "shrdram2";
+ };
+
+ icssg0_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg0_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
+ <&k3_clks 81 20>; /* icssg0_iclk */
+ assigned-clocks = <&icssg0_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 81 20>;
+ };
+
+ icssg0_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */
+ <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
+ assigned-clocks = <&icssg0_iepclk_mux>;
+ assigned-clock-parents = <&icssg0_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg0_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg0_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg0_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru0_0: pru@34000 {
+ compatible = "ti,am642-pru";
+ reg = <0x34000 0x3000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-pru0_0-fw";
+ };
+
+ rtu0_0: rtu@4000 {
+ compatible = "ti,am642-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-rtu0_0-fw";
+ };
+
+ tx_pru0_0: txpru@a000 {
+ compatible = "ti,am642-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-txpru0_0-fw";
+ };
+
+ pru0_1: pru@38000 {
+ compatible = "ti,am642-pru";
+ reg = <0x38000 0x3000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-pru0_1-fw";
+ };
+
+ rtu0_1: rtu@6000 {
+ compatible = "ti,am642-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-rtu0_1-fw";
+ };
+
+ tx_pru0_1: txpru@c000 {
+ compatible = "ti,am642-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-txpru0_1-fw";
+ };
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
+ };
+
+ icssg1: icssg@30080000 {
+ compatible = "ti,am642-icssg";
+ reg = <0x00 0x30080000 0x00 0x80000>;
+ power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x30080000 0x80000>;
+
+ icssg1_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1", "shrdram2";
+ };
+
+ icssg1_cfg: cfg@26000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x26000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_coreclk_mux: coreclk-mux@3c {
+ reg = <0x3c>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
+ <&k3_clks 82 20>; /* icssg1_iclk */
+ assigned-clocks = <&icssg1_coreclk_mux>;
+ assigned-clock-parents = <&k3_clks 82 20>;
+ };
+
+ icssg1_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */
+ <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */
+ assigned-clocks = <&icssg1_iepclk_mux>;
+ assigned-clock-parents = <&icssg1_coreclk_mux>;
+ };
+ };
+ };
+
+ icssg1_mii_rt: mii-rt@32000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x32000 0x100>;
+ };
+
+ icssg1_mii_g_rt: mii-g-rt@33000 {
+ compatible = "ti,pruss-mii-g", "syscon";
+ reg = <0x33000 0x1000>;
+ };
+
+ icssg1_intc: interrupt-controller@20000 {
+ compatible = "ti,icssg-intc";
+ reg = <0x20000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ };
+
+ pru1_0: pru@34000 {
+ compatible = "ti,am642-pru";
+ reg = <0x34000 0x4000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-pru1_0-fw";
+ };
+
+ rtu1_0: rtu@4000 {
+ compatible = "ti,am642-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-rtu1_0-fw";
+ };
+
+ tx_pru1_0: txpru@a000 {
+ compatible = "ti,am642-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-txpru1_0-fw";
+ };
+
+ pru1_1: pru@38000 {
+ compatible = "ti,am642-pru";
+ reg = <0x38000 0x4000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-pru1_1-fw";
+ };
+
+ rtu1_1: rtu@6000 {
+ compatible = "ti,am642-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-rtu1_1-fw";
+ };
+
+ tx_pru1_1: txpru@c000 {
+ compatible = "ti,am642-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am64x-txpru1_1-fw";
+ };
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 82 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+ };
};
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
+
+ mcu_pmx0: pinctrl@4084000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x4084000 0x00 0x84>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
};
serial8 = &main_uart6;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
};
chosen { };
&epwm8 {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
&epwm8 {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2021
+ *
+ * Authors:
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic and Advanced variants, PG1
+ */
+
+&dss {
+ assigned-clocks = <&k3_clks 67 2>;
+ assigned-clock-parents = <&k3_clks 67 5>;
+};
+
+&serdes0 {
+ status = "disabled";
+};
+
+&sdhci1 {
+ no-1-8-v;
+};
+
+&tx_pru0_0 {
+ status = "disabled";
+};
+
+&tx_pru0_1 {
+ status = "disabled";
+};
+
+&tx_pru1_0 {
+ status = "disabled";
+};
+
+&tx_pru1_1 {
+ status = "disabled";
+};
+
+&tx_pru2_0 {
+ status = "disabled";
+};
+
+&tx_pru2_1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2021
+ *
+ * Authors:
+ * Chao Zeng <chao.zeng@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic and Advanced variants, PG2
+ */
+
+&main_pmx0 {
+ cp2102n_reset_pin_default: cp2102n-reset-pin-default {
+ pinctrl-single,pins = <
+ /* (AF12) GPIO1_24, used as cp2102 reset */
+ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
+ >;
+ };
+};
+
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2102n_reset_pin_default>;
+ gpio-line-names =
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "CP2102N-RESET";
+};
+
+&dss {
+ /* Workaround needed to get DP clock of 154Mhz */
+ assigned-clocks = <&k3_clks 67 0>;
+};
+
+&serdes0 {
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+ phys = <&serdes0 PHY_TYPE_USB3 0>;
+ phy-names = "usb3-phy";
+};
+
+&usb0 {
+ maximum-speed = "super-speed";
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+};
*
* Authors:
* Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszk@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
*
- * Common bits of the IOT2050 Basic and Advanced variants
+ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
*/
-/dts-v1/;
-
#include "k3-am654.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
aliases {
spi0 = &mcu_spi0;
+ mmc0 = &sdhci1;
+ mmc1 = &sdhci0;
};
chosen {
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
- no-1-8-v;
};
&usb0 {
};
};
-&serdes0 {
- status = "disabled";
-};
-
&pcie0_rc {
status = "disabled";
};
};
&mailbox0_cluster0 {
- status = "disabled";
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
};
&mailbox0_cluster1 {
- status = "disabled";
+ interrupts = <432>;
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
};
&mailbox0_cluster2 {
status = "disabled";
};
+&mcu_r5fss0_core0 {
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+};
+
+&mcu_r5fss0_core1 {
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+};
+
&icssg0_mdio {
status = "disabled";
};
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
- 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie0_mode>;
bus-range = <0x0 0xff>;
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
- 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
+ ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
+ <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie1_mode>;
bus-range = <0x0 0xff>;
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
-
- thermal_zones: thermal-zones {
- #include "k3-am654-industrial-thermal.dtsi"
- };
};
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
ethernet0 = &cpsw_port1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
};
chosen { };
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Basic variant, PG1 and PG2
+ */
+
+#include "k3-am65-iot2050-common.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 1G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+ };
+
+ cpus {
+ cpu-map {
+ /delete-node/ cluster1;
+ };
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+ };
+
+ /delete-node/ l2-cache1;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "disabled";
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
+ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
+ AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
+ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
+ AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
+ AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
+ AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
+ AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
+ >;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on Basic boards */
+ ti,cluster-mode = <0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2
+ * 1 GB RAM, no eMMC, main_uart0 on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6528-iot2050-basic-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-basic-pg2", "ti,am654";
+ model = "SIMATIC IOT2050 Basic PG2";
+};
*
* Authors:
* Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszk@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
*
- * AM6528-based (dual-core) IOT2050 Basic variant
+ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1
* 1 GB RAM, no eMMC, main_uart0 on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
-#include "k3-am65-iot2050-common.dtsi"
+#include "k3-am6528-iot2050-basic-common.dtsi"
+#include "k3-am65-iot2050-common-pg1.dtsi"
/ {
compatible = "siemens,iot2050-basic", "ti,am654";
model = "SIMATIC IOT2050 Basic";
-
- memory@80000000 {
- device_type = "memory";
- /* 1G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
- };
-
- cpus {
- cpu-map {
- /delete-node/ cluster1;
- };
- /delete-node/ cpu@100;
- /delete-node/ cpu@101;
- };
-
- /delete-node/ l2-cache1;
-};
-
-/* eMMC */
-&sdhci0 {
- status = "disabled";
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
- AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
- AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
- AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
- >;
- };
-};
-
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
};
compatible = "cache";
cache-level = <3>;
};
+
+ thermal_zones: thermal-zones {
+ #include "k3-am654-industrial-thermal.dtsi"
+ };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits of the IOT2050 Advanced variant, PG1 and PG2
+ */
+
+/dts-v1/;
+
+#include "k3-am65-iot2050-common.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ };
+};
+
+&main_pmx0 {
+ main_mmc0_pins_default: main-mmc0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
+ AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
+};
+
+/* eMMC */
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_uart0 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2
+ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
+ model = "SIMATIC IOT2050 Advanced PG2";
+};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on this board */
+ ti,cluster-mode = <0>;
+};
*
* Authors:
* Le Jin <le.jin@siemens.com>
- * Jan Kiszka <jan.kiszk@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
*
- * AM6548-based (quad-core) IOT2050 Advanced variant
+ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1
* 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
/dts-v1/;
-#include "k3-am65-iot2050-common.dtsi"
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg1.dtsi"
/ {
compatible = "siemens,iot2050-advanced", "ti,am654";
model = "SIMATIC IOT2050 Advanced";
-
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-};
-
-&main_pmx0 {
- main_mmc0_pins_default: main-mmc0-pins-default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-};
-
-/* eMMC */
-&sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- bus-width = <8>;
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&main_uart0 {
- status = "disabled";
};
#include <dt-bindings/phy/phy.h>
/ {
+ compatible = "ti,j7200-evm", "ti,j7200";
+ model = "Texas Instruments J7200 EVM";
+
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
- vendor-id = /bits/ 16 <0x104c>;
- device-id = /bits/ 16 <0xb00f>;
+ vendor-id = <0x104c>;
+ device-id = <0xb00f>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
clocks = <&k3_clks 240 6>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
};
chosen { };
#include <dt-bindings/phy/phy-cadence.h>
/ {
+ compatible = "ti,j721e-evm", "ti,j721e";
+ model = "Texas Instruments J721e EVM";
+
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x20000 0x10000>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x30000 0x10000>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
#address-cells = <2>;
#size-cells = <2>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,j721e-sk", "ti,j721e";
+ model = "Texas Instruments J721E SK";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ vusb_main: fixedregulator-vusb-main5v0 {
+ /* USB MAIN INPUT 5V DC */
+ compatible = "regulator-fixed";
+ regulator-name = "vusb-main5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of LM5141 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vusb_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_mmc1_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: gpio-regulator-tps659411 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tps659411";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_3v3>;
+ gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ dp_pwr_3v3: fixedregulator-dp-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_pwr_en_pins_default>;
+ gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
+ enable-active-high;
+ };
+
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
+ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+ >;
+ };
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ dp_pwr_en_pins_default: dp-pwr-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
+ >;
+ };
+
+ dss_vout0_pins_default: dss-vout0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
+ J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
+ J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
+ J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
+ J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
+ J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
+ J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
+ J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
+ J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
+ J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
+ J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
+ J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
+ J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
+ J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
+ J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
+ J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
+ J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
+ J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
+ J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
+ J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
+ J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
+ J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
+ J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
+ J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
+ J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
+ J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
+ J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
+ J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
+ >;
+ };
+
+ /* Reset for M.2 E Key slot on PCIe0 */
+ ekey_reset_pins_default: ekey-reset-pns-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
+ >;
+ };
+
+ vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ /* Reset for M.2 M Key slot on PCIe1 */
+ mkey_reset_pins_default: mkey-reset-pns-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "reserved";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart2 {
+ /* Brought out on RPi header */
+ status = "disabled";
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart5 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* Brought out on M.2 E Key */
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&ospi1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ /* PCIe1 M.2 M Key I2C */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ /* PCIe0 M.2 E Key I2C */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ /* i2c1 is used for DVI DDC, so we need to use 100kHz */
+ clock-frequency = <100000>;
+};
+
+&main_i2c2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ /* CSI0 I2C */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ /* CSI1 I2C */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+};
+
+&main_i2c4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c5 {
+ /* Brought out on RPi Header */
+ status = "disabled";
+};
+
+&main_i2c6 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio3 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio5 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&main_gpio7 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&main_r5fss0_core0{
+ firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&tscadc1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout0_pins_default>;
+
+ assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
+ <&k3_clks 152 4>, /* VP 2 pixel clock */
+ <&k3_clks 152 9>, /* VP 3 pixel clock */
+ <&k3_clks 152 13>; /* VP 4 pixel clock */
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
+};
+
+&mcasp0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp3 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp5 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp6 {
+ /* Brought out on RPi header */
+ status = "disabled";
+};
+
+&mcasp7 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp8 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp9 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp10 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp11 {
+ /* Brought out on M.2 E Key */
+ status = "disabled";
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ekey_reset_pins_default>;
+ reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
+
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mkey_reset_pins_default>;
+ reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
+
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_ep {
+ status = "disabled";
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&dss {
+ status = "disabled";
+};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&ufs_wrapper {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
serial10 = &main_uart8;
serial11 = &main_uart9;
ethernet0 = &cpsw_port1;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ mmc2 = &main_sdhci2;
};
chosen { };
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
+
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb
+
+sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
+sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+smk-k26-revA-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
+smk-k26-revA-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+
+dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revB.dtb
/*
* Clock specification for Xilinx ZynqMP
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
};
};
+&zynqmp_firmware {
+ zynqmp_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
+ <&aux_ref_clk>, <>_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
+ "aux_ref_clk", "gt_crx_ref_clk";
+ };
+};
+
&can0 {
clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ *
+ * SD level shifter:
+ * "A" – A01 board un-modified (NXP)
+ * "Y" – A01 board modified with legacy interposer (Nexperia)
+ * "Z" – A01 board modified with Diode interposer
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ /* u14 - 0x40 - ina260 */
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};
+
+&amba {
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+/* DP/USB 3.0 and SATA */
+&psgtr {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
+};
+
+&zynqmp_dpsub {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ /* missing usb5744 - u43 */
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+&sdhci1 { /* on CC with tuned parameters */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+};
+
+&gem3 { /* required by spec */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+ };
+};
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ /* u14 - 0x40 - ina260 */
+ /* u43 - 0x2d - usb5744 */
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};
+
+&amba {
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+/* DP/USB 3.0 */
+&psgtr {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+};
+
+&zynqmp_dpsub {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+&sdhci1 { /* on CC with tuned parameters */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+ clk-phase-sd-hs = <126>, <60>;
+ clk-phase-uhs-sdr25 = <120>, <60>;
+ clk-phase-uhs-ddr50 = <126>, <48>;
+};
+
+&gem3 { /* required by spec */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+ };
+};
+
+&pinctrl0 { /* required by spec */
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP SM-K26 Rev1/B/A";
+ compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
+ "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
+ "xlnx,zynqmp";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ nvmem0 = &eeprom;
+ nvmem1 = &eeprom_cc;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory"; /* 4GB */
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ fwuen {
+ label = "fwuen";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds35-led {
+ label = "heartbeat";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds36-led {
+ label = "vbus_det";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&uart1 { /* MIO36/MIO37 */
+ status = "okay";
+};
+
+&qspi { /* MIO 0-5 - U143 */
+ status = "okay";
+ flash@0 { /* MT25QU512A */
+ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>; /* 40MHz */
+ partition@0 {
+ label = "Image Selector";
+ reg = <0x0 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@80000 {
+ label = "Image Selector Golden";
+ reg = <0x80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@100000 {
+ label = "Persistent Register";
+ reg = <0x100000 0x20000>; /* 128KB */
+ };
+ partition@120000 {
+ label = "Persistent Register Backup";
+ reg = <0x120000 0x20000>; /* 128KB */
+ };
+ partition@140000 {
+ label = "Open_1";
+ reg = <0x140000 0xC0000>; /* 768KB */
+ };
+ partition@200000 {
+ label = "Image A (FSBL, PMU, ATF, U-Boot)";
+ reg = <0x200000 0xD00000>; /* 13MB */
+ };
+ partition@f00000 {
+ label = "ImgSel Image A Catch";
+ reg = <0xF00000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@f80000 {
+ label = "Image B (FSBL, PMU, ATF, U-Boot)";
+ reg = <0xF80000 0xD00000>; /* 13MB */
+ };
+ partition@1c80000 {
+ label = "ImgSel Image B Catch";
+ reg = <0x1C80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@1d00000 {
+ label = "Open_2";
+ reg = <0x1D00000 0x100000>; /* 1MB */
+ };
+ partition@1e00000 {
+ label = "Recovery Image";
+ reg = <0x1E00000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2000000 {
+ label = "Recovery Image Backup";
+ reg = <0x2000000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2200000 {
+ label = "U-Boot storage variables";
+ reg = <0x2200000 0x20000>; /* 128KB */
+ };
+ partition@2220000 {
+ label = "U-Boot storage variables backup";
+ reg = <0x2220000 0x20000>; /* 128KB */
+ };
+ partition@2240000 {
+ label = "SHA256";
+ reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
+ read-only;
+ lock;
+ };
+ partition@2250000 {
+ label = "User";
+ reg = <0x2250000 0x1db0000>; /* 29.5 MB */
+ };
+ };
+};
+
+&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&spi1 { /* MIO6, 9-11 */
+ status = "okay";
+ label = "TPM";
+ num-cs = <1>;
+ tpm@0 { /* slm9670 - U144 */
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ eeprom: eeprom@50 { /* u46 - also at address 0x58 */
+ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
+ reg = <0x50>;
+ /* WP pin EE_WP_EN connected to slg7x644092@68 */
+ };
+
+ eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
+ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
+ reg = <0x51>;
+ };
+
+ /* da9062@30 - u170 - also at address 0x31 */
+ /* da9131@33 - u167 */
+ da9131: pmic@33 {
+ compatible = "dlg,da9131";
+ reg = <0x33>;
+ regulators {
+ da9131_buck1: buck1 {
+ regulator-name = "da9131_buck1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ da9131_buck2: buck2 {
+ regulator-name = "da9131_buck2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* da9130@32 - u166 */
+ da9130: pmic@32 {
+ compatible = "dlg,da9130";
+ reg = <0x32>;
+ regulators {
+ da9130_buck1: buck1 {
+ regulator-name = "da9130_buck1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
+ /*
+ * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
+ * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
+ * Address conflict with slg7x644091@70 making both the devices NOT accessible.
+ * With the FW fix, stdp4320 should respond to address 0x73 only.
+ */
+ /* slg7x644092@68 - u169 */
+ /* Also connected via JA1C as C23/C24 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
+ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
+ "I2C1_SDA", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "", /* 30 - 34 */
+ "", "", "", "", "", /* 35 - 39 */
+ "", "", "", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "", "", "", /* 50 - 54 */
+ "", "", "", "", "", /* 55 - 59 */
+ "", "", "", "", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "", "", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-sm-k26-revA.dts"
+
+/ {
+ model = "ZynqMP SMK-K26 Rev1/B/A";
+ compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+ "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
+ "xlnx,zynqmp";
+};
+
+&sdhci0 {
+ status = "disabled";
+};
/*
* dts file for Xilinx ZynqMP ZC1232
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
aliases {
serial0 = &uart0;
serial1 = &dcc;
+ spi0 = &qspi;
};
chosen {
status = "okay";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&sata {
status = "okay";
/* SATA OOB timing settings */
/*
* dts file for Xilinx ZynqMP ZC1254
*
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
aliases {
serial0 = &uart0;
serial1 = &dcc;
+ spi0 = &qspi;
};
chosen {
status = "okay";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&uart0 {
status = "okay";
};
/*
* dts file for Xilinx ZynqMP ZC1275
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
aliases {
serial0 = &uart0;
serial1 = &dcc;
+ spi0 = &qspi;
};
chosen {
status = "okay";
};
+&gpio {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+};
+
&uart0 {
status = "okay";
};
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
+ spi0 = &qspi;
+ usb0 = &usb0;
};
chosen {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ clock_si5338_0: clk27 { /* u55 SI5338-GM */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clock_si5338_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clock_si5338_3: clk150 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <150000000>;
+ };
};
&fpd_dma_chan1 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 {
reg = <0>;
};
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_8_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_8_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO34";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO35";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_0_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio0_wp_0_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "sdio0_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_38_grp";
+ };
+
+ conf {
+ groups = "gpio0_38_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
+&psgtr {
+ status = "okay";
+ /* dp, usb3, sata */
+ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&rtc {
status = "okay";
};
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* eMMC */
&sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
bus-width = <8>;
+ xlnx,mio-bank = <0>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ /*
+ * This property should be removed for supporting UHS mode
+ */
+ no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
+ <&psgtr 0 PHY_TYPE_DP 1 1>;
};
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
- can0 = &can0;
- can1 = &can1;
ethernet0 = &gem2;
i2c0 = &i2c0;
rtc0 = &rtc;
serial1 = &uart1;
spi0 = &spi0;
spi1 = &spi1;
+ usb0 = &usb1;
};
chosen {
&can0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
};
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&fpd_dma_chan1 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
};
};
+&nand0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand0_default>;
+ arasan,has-mdma;
+
+ nand@0 {
+ reg = <0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-0";
+ };
+ nand@1 {
+ reg = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-1";
+ };
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+ groups = "can0_9_grp";
+ };
+
+ conf {
+ groups = "can0_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO38";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO39";
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_8_grp";
+ };
+
+ conf {
+ groups = "can1_8_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO33";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO32";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_1_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_1_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_6_grp", "gpio0_7_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_6_grp", "gpio0_7_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_10_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_10_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO42";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO43";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_10_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_10_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO41";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO40";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem2_default: gem2-default {
+ mux {
+ function = "ethernet2";
+ groups = "ethernet2_0_grp";
+ };
+
+ conf {
+ groups = "ethernet2_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
+ "MIO63";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
+ "MIO57";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio2";
+ groups = "mdio2_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio2_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_nand0_default: nand0-default {
+ mux {
+ groups = "nand0_0_grp";
+ function = "nand0";
+ };
+
+ conf {
+ groups = "nand0_0_grp";
+ bias-pull-up;
+ };
+
+ mux-ce {
+ groups = "nand0_ce_0_grp";
+ function = "nand0_ce";
+ };
+
+ conf-ce {
+ groups = "nand0_ce_0_grp";
+ bias-pull-up;
+ };
+
+ mux-rb {
+ groups = "nand0_rb_0_grp";
+ function = "nand0_rb";
+ };
+
+ conf-rb {
+ groups = "nand0_rb_0_grp";
+ bias-pull-up;
+ };
+
+ mux-dqs {
+ groups = "nand0_dqs_0_grp";
+ function = "nand0_dqs";
+ };
+
+ conf-dqs {
+ groups = "nand0_dqs_0_grp";
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ mux {
+ groups = "spi0_0_grp";
+ function = "spi0";
+ };
+
+ conf {
+ groups = "spi0_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
+ "spi0_ss_2_grp";
+ function = "spi0_ss";
+ };
+
+ conf-cs {
+ groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
+ "spi0_ss_2_grp";
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ mux {
+ groups = "spi1_3_grp";
+ function = "spi1";
+ };
+
+ conf {
+ groups = "spi1_3_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
+ "spi1_ss_11_grp";
+ function = "spi1_ss";
+ };
+
+ conf-cs {
+ groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
+ "spi1_ss_11_grp";
+ bias-disable;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
spi0_flash0: flash@0 {
#address-cells = <1>;
reg = <0>;
partition@0 {
- label = "data";
+ label = "spi0-data";
reg = <0x0 0x100000>;
};
};
&spi1 {
status = "okay";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
spi1_flash0: flash@0 {
#address-cells = <1>;
reg = <0>;
partition@0 {
- label = "data";
+ label = "spi1-data";
reg = <0x0 0x84000>;
};
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
+};
+
+&dwc3_1 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
- * (C) Copyright 2016 - 2019, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
+ usb0 = &usb0;
+ usb1 = &usb1;
};
chosen {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ clock_si5338_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clock_si5338_3: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
};
&fpd_dma_chan1 {
clock-frequency = <400000>;
};
+/* MT29F64G08AECDBJ4-6 */
+&nand0 {
+ status = "okay";
+ arasan,has-mdma;
+ num-cs = <2>;
+};
+
+&psgtr {
+ status = "okay";
+ /* usb3, sata */
+ clocks = <&clock_si5338_2>, <&clock_si5338_3>;
+ clock-names = "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
};
&sdhci1 { /* emmc with some settings */
&usb0 {
status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
+};
+
+&dwc3_1 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
+ spi0 = &qspi;
};
chosen {
status = "okay";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&rtc {
status = "okay";
};
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+};
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy@0 {
reg = <0>;
};
&i2c0 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
};
&i2c1 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
+
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_18_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_18_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_74_grp", "gpio0_75_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_74_grp", "gpio0_75_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_19_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_19_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_76_grp", "gpio0_77_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_76_grp", "gpio0_77_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_17_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO71";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_18_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_18_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO73";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO72";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
+ "MIO49";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
+ "MIO43";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_0_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio0_wp_0_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "sdio0_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_watchdog0_default: watchdog0-default {
+ mux-clk {
+ groups = "swdt0_clk_1_grp";
+ function = "swdt0_clk";
+ };
+
+ conf-clk {
+ groups = "swdt0_clk_1_grp";
+ bias-pull-up;
+ };
+
+ mux-rst {
+ groups = "swdt0_rst_1_grp";
+ function = "swdt0_rst";
+ };
+
+ conf-rst {
+ groups = "swdt0_rst_1_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc0_default: ttc0-default {
+ mux-clk {
+ groups = "ttc0_clk_0_grp";
+ function = "ttc0_clk";
+ };
+
+ conf-clk {
+ groups = "ttc0_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc0_wav_0_grp";
+ function = "ttc0_wav";
+ };
+
+ conf-wav {
+ groups = "ttc0_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc1_default: ttc1-default {
+ mux-clk {
+ groups = "ttc1_clk_0_grp";
+ function = "ttc1_clk";
+ };
+
+ conf-clk {
+ groups = "ttc1_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc1_wav_0_grp";
+ function = "ttc1_wav";
+ };
+
+ conf-wav {
+ groups = "ttc1_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc2_default: ttc2-default {
+ mux-clk {
+ groups = "ttc2_clk_0_grp";
+ function = "ttc2_clk";
+ };
+
+ conf-clk {
+ groups = "ttc2_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc2_wav_0_grp";
+ function = "ttc2_wav";
+ };
+
+ conf-wav {
+ groups = "ttc2_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc3_default: ttc3-default {
+ mux-clk {
+ groups = "ttc3_clk_0_grp";
+ function = "ttc3_clk";
+ };
+
+ conf-clk {
+ groups = "ttc3_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc3_wav_0_grp";
+ function = "ttc3_wav";
+ };
+
+ conf-wav {
+ groups = "ttc3_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
};
&sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
no-1-8-v;
+ xlnx,mio-bank = <0>;
};
&ttc0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc0_default>;
};
&ttc1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc1_default>;
};
&ttc2 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc2_default>;
};
&ttc3 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc3_default>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
&watchdog0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_watchdog0_default>;
};
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
- * (C) Copyright 2016 - 2019, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Nathalie Chan King Choy
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
serial2 = &dcc;
spi0 = &spi0;
spi1 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
- si5335a_0: clk26 {
+ si5335_0: si5335_0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
- si5335a_1: clk27 {
+ si5335_1: si5335_1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
&i2c1 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
clock-frequency = <100000>;
i2c-mux@75 { /* u11 */
compatible = "nxp,pca9548";
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_1_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_1_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_4_grp", "gpio0_5_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_4_grp", "gpio0_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_3_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_3_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_2_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_2_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ mux {
+ groups = "spi0_3_grp";
+ function = "spi0";
+ };
+
+ conf {
+ groups = "spi0_3_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi0_ss_9_grp";
+ function = "spi0_ss";
+ };
+
+ conf-cs {
+ groups = "spi0_ss_9_grp";
+ bias-disable;
+ };
+
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ mux {
+ groups = "spi1_0_grp";
+ function = "spi1";
+ };
+
+ conf {
+ groups = "spi1_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi1_ss_0_grp";
+ function = "spi1_ss";
+ };
+
+ conf-cs {
+ groups = "spi1_ss_0_grp";
+ bias-disable;
+ };
+
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_0_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO3";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO2";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_0_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO1";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO0";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
- /* usb3, dps */
- clocks = <&si5335a_0>, <&si5335a_1>;
+ /* usb3, dp */
+ clocks = <&si5335_0>, <&si5335_1>;
clock-names = "ref0", "ref1";
};
status = "okay";
no-1-8-v;
disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
xlnx,mio-bank = <0>;
};
&sdhci1 {
status = "okay";
bus-width = <0x4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <0>;
non-removable;
disable-wp;
status = "okay";
label = "LS-SPI0";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
};
&spi1 { /* High Speed connector */
status = "okay";
label = "HS-SPI1";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
bluetooth {
compatible = "ti,wl1831-st";
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
&uart1 {
status = "okay";
-
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "peripheral";
+ maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
+};
+
+&dwc3_1 {
+ status = "okay";
dr_mode = "host";
+ maximum-speed = "super-speed";
};
&watchdog0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.1
+ *
+ * (C) Copyright 2016 - 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-rev1.0.dts"
+
+/ {
+ model = "ZynqMP ZCU102 Rev1.1";
+ compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015 - 2019, Xilinx, Inc.
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
};
chosen {
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
+ /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
};
};
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
status = "disabled"; /* unreachable */
reg = <0x20>;
};
-
max20751@72 { /* u95 */
compatible = "maxim,max20751";
reg = <0x72>;
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux-sw {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf-sw {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22", "MIO23";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&pcie {
status = "okay";
};
clock-names = "ref0", "ref1", "ref2", "ref3";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&rtc {
status = "okay";
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ /*
+ * 1.0 revision has level shifter and this property should be
+ * removed for supporting UHS mode
+ */
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&watchdog0 {
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
- * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
+ /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
};
/* Cleanup from RevA */
/delete-node/ ethernet-phy@21;
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
ethernet0 = &gem3;
i2c0 = &i2c1;
mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
};
chosen {
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
};
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
&gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
- eeprom@54 { /* u23 */
+ eeprom: eeprom@54 { /* u23 */
compatible = "atmel,24c08";
reg = <0x54>;
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
- reg = <0x6c>;
- };
+ /* 8T49N287 - u182 */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
- reg = <0x43>;
+ irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x43>; /* pmbus / i2c 0x13 */
};
- irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
- reg = <0x4d>;
+ irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
+ compatible = "infineon,irps5401";
+ reg = <0x44>; /* pmbus / i2c 0x14 */
};
};
};
};
-&rtc {
+&pinctrl0 {
status = "okay";
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
};
&psgtr {
clock-names = "ref1", "ref2", "ref3";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
&sata {
status = "okay";
/* SATA OOB timing settings */
&sdhci1 {
status = "okay";
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&watchdog0 {
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
ethernet0 = &gem3;
i2c0 = &i2c1;
mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
};
chosen {
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
- reg = <0x6c>;
- };
+ /* 8T49N287 - u182 */
};
i2c@2 {
};
};
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+};
+
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&qspi {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
};
};
status = "okay";
};
-&psgtr {
- status = "okay";
- /* nc, sata, usb3, dp */
- clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
- clock-names = "ref1", "ref2", "ref3";
-};
-
&sata {
status = "okay";
/* SATA OOB timing settings */
&sdhci1 {
status = "okay";
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&watchdog0 {
/*
* dts file for Xilinx ZynqMP ZCU106
*
- * (C) Copyright 2016 - 2019, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
};
chosen {
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
status = "okay";
};
-&zynqmp_dpdma {
- status = "okay";
-};
-
-&zynqmp_dpsub {
- status = "okay";
- phy-names = "dp-phy0", "dp-phy1";
- phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
- <&psgtr 0 PHY_TYPE_DP 1 3>;
-};
-
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO23", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clock-names = "ref1", "ref2", "ref3";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&rtc {
status = "okay";
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ /*
+ * This property should be removed for supporting UHS mode
+ */
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+ <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
/*
* dts file for Xilinx ZynqMP ZCU111
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
};
chosen {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u22: gpio@20 {
compatible = "ti,tca6416";
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
+ irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
+ compatible = "infineon,irps5401";
reg = <0x43>;
};
- irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
+ irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
+ compatible = "infineon,irps5401";
reg = <0x44>;
};
- irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
+ irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
+ compatible = "infineon,irps5401";
reg = <0x45>;
};
/* u68 IR38064 +0 */
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux@74 { /* u26 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- si5382: clock-generator@69 { /* SI5382 - u48 */
- reg = <0x69>;
- };
+ /* SI5382 - u48 */
};
i2c@5 {
#address-cells = <1>;
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO23", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
- /* nc, sata, usb3, dp */
- clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ /* nc, dp, usb3, sata */
+ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
clock-names = "ref1", "ref2", "ref3";
};
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
&rtc {
status = "okay";
};
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ disable-wp;
+ /*
+ * This property should be removed for supporting UHS mode
+ */
no-1-8-v;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
};
&zynqmp_dpdma {
/*
* dts file for Xilinx ZynqMP
*
- * (C) Copyright 2014 - 2019, Xilinx, Inc.
+ * (C) Copyright 2014 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
mbox-names = "tx", "rx";
};
- zynqmp_clk: clock-controller {
- #clock-cells = <1>;
- compatible = "xlnx,zynqmp-clk";
- clocks = <&pss_ref_clk>,
- <&video_clk>,
- <&pss_alt_ref_clk>,
- <&aux_ref_clk>,
- <>_crx_ref_clk>;
- clock-names = "pss_ref_clk",
- "video_clk",
- "pss_alt_ref_clk",
- "aux_ref_clk",
- "gt_crx_ref_clk";
- };
-
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
+
+ pinctrl0: pinctrl {
+ compatible = "xlnx,zynqmp-pinctrl";
+ status = "disabled";
+ };
};
};
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
+ status = "disabled";
reg = <0x0 0xfd6e0000 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x4d0>;
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
- calibration = <0x8000>;
+ calibration = <0x7FFF>;
};
sata: ahci@fd0c0000 {
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&zynqmp_firmware PD_SATA>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
#stream-id-cells = <4>;
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
<&smmu 0x4c2>, <&smmu 0x4c3>;
};
uart0: serial@ff000000 {
- compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
};
uart1: serial@ff010000 {
- compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
power-domains = <&zynqmp_firmware PD_UART_1>;
};
- usb0: usb@fe200000 {
- compatible = "snps,dwc3";
+ usb0: usb@ff9d0000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
status = "disabled";
- interrupt-parent = <&gic>;
- interrupts = <0 65 4>;
- reg = <0x0 0xfe200000 0x0 0x40000>;
- clock-names = "clk_xin", "clk_ahb";
+ compatible = "xlnx,zynqmp-dwc3";
+ reg = <0x0 0xff9d0000 0x0 0x100>;
+ clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
+ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+ ranges;
+
+ dwc3_0: usb@fe200000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe200000 0x0 0x40000>;
+ interrupt-parent = <&gic>;
+ interrupt-names = "dwc_usb3", "otg";
+ interrupts = <0 65 4>, <0 69 4>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x860>;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ /* dma-coherent; */
+ };
};
- usb1: usb@fe300000 {
- compatible = "snps,dwc3";
+ usb1: usb@ff9e0000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
status = "disabled";
- interrupt-parent = <&gic>;
- interrupts = <0 70 4>;
- reg = <0x0 0xfe300000 0x0 0x40000>;
- clock-names = "clk_xin", "clk_ahb";
+ compatible = "xlnx,zynqmp-dwc3";
+ reg = <0x0 0xff9e0000 0x0 0x100>;
+ clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
+ <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
+ reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+ ranges;
+
+ dwc3_1: usb@fe300000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe300000 0x0 0x40000>;
+ interrupt-parent = <&gic>;
+ interrupt-names = "dwc_usb3", "otg";
+ interrupts = <0 70 4>, <0 74 4>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x861>;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ /* dma-coherent; */
+ };
};
watchdog0: watchdog@fd4d0000 {
interrupt-parent = <&gic>;
interrupts = <0 113 1>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
- timeout-sec = <10>;
+ timeout-sec = <60>;
+ reset-on-timeout;
};
lpd_watchdog: watchdog@ff150000 {
void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
#define acpi_os_ioremap acpi_os_ioremap
-void __iomem *acpi_os_memmap(acpi_physical_address phys, acpi_size size);
-#define acpi_os_memmap acpi_os_memmap
-
typedef u64 phys_cpuid_t;
#define PHYS_CPUID_INVALID INVALID_HWID
#define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
#endif
+#ifdef CONFIG_KASAN_HW_TAGS
+#define EXPORT_SYMBOL_NOHWKASAN(name)
+#else
+#define EXPORT_SYMBOL_NOHWKASAN(name) EXPORT_SYMBOL_NOKASAN(name)
+#endif
/*
* Emit a 64-bit absolute little endian symbol reference in a way that
* ensures that it will be resolved at build time, even when building a
static inline void mte_check_tfsr_entry(void)
{
+ if (!system_supports_mte())
+ return;
+
mte_check_tfsr_el1();
}
static inline void mte_check_tfsr_exit(void)
{
+ if (!system_supports_mte())
+ return;
+
/*
* The asynchronous faults are sync'ed automatically with
* TFSR_EL1 on kernel entry but for exit an explicit dsb()
#define __HAVE_ARCH_STRCHR
extern char *strchr(const char *, int c);
+#ifndef CONFIG_KASAN_HW_TAGS
#define __HAVE_ARCH_STRCMP
extern int strcmp(const char *, const char *);
#define __HAVE_ARCH_STRNCMP
extern int strncmp(const char *, const char *, __kernel_size_t);
+#endif
#define __HAVE_ARCH_STRLEN
extern __kernel_size_t strlen(const char *);
return __pgprot(PROT_DEVICE_nGnRnE);
}
-static void __iomem *__acpi_os_ioremap(acpi_physical_address phys,
- acpi_size size, bool memory)
+void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
{
efi_memory_desc_t *md, *region = NULL;
pgprot_t prot;
* It is fine for AML to remap regions that are not represented in the
* EFI memory map at all, as it only describes normal memory, and MMIO
* regions that require a virtual mapping to make them accessible to
- * the EFI runtime services. Determine the region default
- * attributes by checking the requested memory semantics.
+ * the EFI runtime services.
*/
- prot = memory ? __pgprot(PROT_NORMAL_NC) :
- __pgprot(PROT_DEVICE_nGnRnE);
+ prot = __pgprot(PROT_DEVICE_nGnRnE);
if (region) {
switch (region->type) {
case EFI_LOADER_CODE:
return __ioremap(phys, size, prot);
}
-void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
-{
- return __acpi_os_ioremap(phys, size, false);
-}
-
-void __iomem *acpi_os_memmap(acpi_physical_address phys, acpi_size size)
-{
- return __acpi_os_ioremap(phys, size, true);
-}
-
/*
* Claim Synchronous External Aborts as a firmware first notification.
*
/*
* For reasons that aren't entirely clear, enabling KPTI on Cavium
* ThunderX leads to apparent I-cache corruption of kernel text, which
- * ends as well as you might imagine. Don't even try.
+ * ends as well as you might imagine. Don't even try. We cannot rely
+ * on the cpus_have_*cap() helpers here to detect the CPU erratum
+ * because cpucap detection order may change. However, since we know
+ * affected CPUs are always in a homogeneous configuration, it is
+ * safe to rely on this_cpu_has_cap() here.
*/
- if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
+ if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
str = "ARM64_WORKAROUND_CAVIUM_27456";
__kpti_forced = -1;
}
void sve_alloc(struct task_struct *task)
{
if (task->thread.sve_state) {
- memset(task->thread.sve_state, 0, sve_state_size(current));
+ memset(task->thread.sve_state, 0, sve_state_size(task));
return;
}
#ifdef CONFIG_KASAN_HW_TAGS
void mte_check_tfsr_el1(void)
{
- u64 tfsr_el1;
-
- if (!system_supports_mte())
- return;
-
- tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
+ u64 tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) {
/*
void mte_thread_switch(struct task_struct *next)
{
+ if (!system_supports_mte())
+ return;
+
mte_update_sctlr_user(next);
/*
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/nospec.h>
-#include <linux/sched.h>
#include <linux/stddef.h>
#include <linux/sysctl.h>
#include <linux/unistd.h>
#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
#include <linux/stackprotector.h>
-unsigned long __stack_chk_guard __read_mostly;
+unsigned long __stack_chk_guard __ro_after_init;
EXPORT_SYMBOL(__stack_chk_guard);
#endif
if (thread_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
do_signal(regs);
- if (thread_flags & _TIF_NOTIFY_RESUME) {
+ if (thread_flags & _TIF_NOTIFY_RESUME)
tracehook_notify_resume(regs);
- rseq_handle_notify_resume(NULL, regs);
- }
if (thread_flags & _TIF_FOREIGN_FPSTATE)
fpsimd_restore_current_state();
ret
SYM_FUNC_END_PI(strcmp)
-EXPORT_SYMBOL_NOKASAN(strcmp)
+EXPORT_SYMBOL_NOHWKASAN(strcmp)
ret
SYM_FUNC_END_PI(strncmp)
-EXPORT_SYMBOL_NOKASAN(strncmp)
+EXPORT_SYMBOL_NOHWKASAN(strncmp)
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
do_signal(regs);
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+ if (thread_info_flags & _TIF_NOTIFY_RESUME)
tracehook_notify_resume(regs);
- rseq_handle_notify_resume(NULL, regs);
- }
}
* two accesses to memory, which may be undesirable for some devices.
*/
#define in_8(addr) \
- ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; })
+ ({ u8 __v = (*(__force volatile u8 *) (unsigned long)(addr)); __v; })
#define in_be16(addr) \
- ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
+ ({ u16 __v = (*(__force volatile u16 *) (unsigned long)(addr)); __v; })
#define in_be32(addr) \
- ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
+ ({ u32 __v = (*(__force volatile u32 *) (unsigned long)(addr)); __v; })
#define in_le16(addr) \
- ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; })
+ ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (unsigned long)(addr)); __v; })
#define in_le32(addr) \
- ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; })
+ ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (unsigned long)(addr)); __v; })
-#define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b))
-#define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w))
-#define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l))
-#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w))
-#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l))
+#define out_8(addr,b) (void)((*(__force volatile u8 *) (unsigned long)(addr)) = (b))
+#define out_be16(addr,w) (void)((*(__force volatile u16 *) (unsigned long)(addr)) = (w))
+#define out_be32(addr,l) (void)((*(__force volatile u32 *) (unsigned long)(addr)) = (l))
+#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (unsigned long)(addr)) = cpu_to_le16(w))
+#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (unsigned long)(addr)) = cpu_to_le32(l))
#define raw_inb in_8
#define raw_inw in_be16
int mvme147_hwclk(int op, struct rtc_time *t)
{
-#warning check me!
if (!op) {
m147_rtc->ctrl = RTC_READ;
t->tm_year = bcd2int (m147_rtc->bcd_year);
m147_rtc->ctrl = 0;
if (t->tm_year < 70)
t->tm_year += 100;
+ } else {
+ /* FIXME Setting the time is not yet supported */
+ return -EOPNOTSUPP;
}
return 0;
}
int mvme16x_hwclk(int op, struct rtc_time *t)
{
-#warning check me!
if (!op) {
rtc->ctrl = RTC_READ;
t->tm_year = bcd2int (rtc->bcd_year);
rtc->ctrl = 0;
if (t->tm_year < 70)
t->tm_year += 100;
+ } else {
+ /* FIXME Setting the time is not yet supported */
+ return -EOPNOTSUPP;
}
return 0;
}
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
do_signal(regs);
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+ if (thread_info_flags & _TIF_NOTIFY_RESUME)
tracehook_notify_resume(regs);
- rseq_handle_notify_resume(NULL, regs);
- }
user_enter();
}
#include <asm-generic/getorder.h>
#include <asm/pdc.h>
-#define PAGE0 ((struct zeropage *)__PAGE_OFFSET)
+#define PAGE0 ((struct zeropage *)absolute_pointer(__PAGE_OFFSET))
/* DEFINITION OF THE ZERO-PAGE (PAG0) */
/* based on work by Jason Eckhardt (jason@equator.com) */
}
}
+#ifdef CONFIG_PCI
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
if (!INDIRECT_ADDR(addr)) {
iounmap(addr);
}
}
+EXPORT_SYMBOL(pci_iounmap);
+#endif
EXPORT_SYMBOL(ioread8);
EXPORT_SYMBOL(ioread16);
EXPORT_SYMBOL(iowrite32_rep);
EXPORT_SYMBOL(ioport_map);
EXPORT_SYMBOL(ioport_unmap);
-EXPORT_SYMBOL(pci_iounmap);
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \
-pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
- -include $(srctree)/include/linux/compiler_attributes.h \
$(LINUXINCLUDE)
ifdef CONFIG_PPC64_BOOT_WRAPPER
BOOTCFLAGS += -fno-stack-protector
endif
+BOOTCFLAGS += -include $(srctree)/include/linux/compiler_attributes.h
BOOTCFLAGS += -I$(objtree)/$(obj) -I$(srctree)/$(obj)
DTC_FLAGS ?= -p 1024
# define ASM_CONST(x) __ASM_CONST(x)
#endif
-/*
- * Inline assembly memory constraint
- *
- * GCC 4.9 doesn't properly handle pre update memory constraint "m<>"
- *
- */
-#if defined(GCC_VERSION) && GCC_VERSION < 50000
-#define UPD_CONSTR ""
-#else
#define UPD_CONSTR "<>"
-#endif
#endif /* _ASM_POWERPC_ASM_CONST_H */
#include <asm/switch_to.h>
#include <asm/syscall.h>
#include <asm/time.h>
+#include <asm/tm.h>
#include <asm/unistd.h>
#if defined(CONFIG_PPC_ADV_DEBUG_REGS) && defined(CONFIG_PPC32)
*/
irq_soft_mask_regs_set_state(regs, IRQS_ENABLED);
+ /*
+ * If system call is called with TM active, set _TIF_RESTOREALL to
+ * prevent RFSCV being used to return to userspace, because POWER9
+ * TM implementation has problems with this instruction returning to
+ * transactional state. Final register values are not relevant because
+ * the transaction will be aborted upon return anyway. Or in the case
+ * of unsupported_scv SIGILL fault, the return state does not much
+ * matter because it's an edge case.
+ */
+ if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
+ unlikely(MSR_TM_TRANSACTIONAL(regs->msr)))
+ current_thread_info()->flags |= _TIF_RESTOREALL;
+
+ /*
+ * If the system call was made with a transaction active, doom it and
+ * return without performing the system call. Unless it was an
+ * unsupported scv vector, in which case it's treated like an illegal
+ * instruction.
+ */
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) &&
+ !trap_is_unsupported_scv(regs)) {
+ /* Enable TM in the kernel, and disable EE (for scv) */
+ hard_irq_disable();
+ mtmsr(mfmsr() | MSR_TM);
+
+ /* tabort, this dooms the transaction, nothing else */
+ asm volatile(".long 0x7c00071d | ((%0) << 16)"
+ :: "r"(TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT));
+
+ /*
+ * Userspace will never see the return value. Execution will
+ * resume after the tbegin. of the aborted transaction with the
+ * checkpointed register state. A context switch could occur
+ * or signal delivered to the process before resuming the
+ * doomed transaction context, but that should all be handled
+ * as expected.
+ */
+ return -ENOSYS;
+ }
+#endif // CONFIG_PPC_TRANSACTIONAL_MEM
+
local_irq_enable();
if (unlikely(current_thread_info()->flags & _TIF_SYSCALL_DOTRACE)) {
#include <asm/mmu.h>
#include <asm/ppc_asm.h>
#include <asm/ptrace.h>
-#include <asm/tm.h>
.section ".toc","aw"
SYS_CALL_TABLE:
.globl system_call_vectored_\name
system_call_vectored_\name:
_ASM_NOKPROBE_SYMBOL(system_call_vectored_\name)
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-BEGIN_FTR_SECTION
- extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
- bne tabort_syscall
-END_FTR_SECTION_IFSET(CPU_FTR_TM)
-#endif
SCV_INTERRUPT_TO_KERNEL
mr r10,r1
ld r1,PACAKSAVE(r13)
.globl system_call_common
system_call_common:
_ASM_NOKPROBE_SYMBOL(system_call_common)
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-BEGIN_FTR_SECTION
- extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
- bne tabort_syscall
-END_FTR_SECTION_IFSET(CPU_FTR_TM)
-#endif
mr r10,r1
ld r1,PACAKSAVE(r13)
std r10,0(r1)
RESTART_TABLE(.Lsyscall_rst_start, .Lsyscall_rst_end, syscall_restart)
#endif
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-tabort_syscall:
-_ASM_NOKPROBE_SYMBOL(tabort_syscall)
- /* Firstly we need to enable TM in the kernel */
- mfmsr r10
- li r9, 1
- rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
- mtmsrd r10, 0
-
- /* tabort, this dooms the transaction, nothing else */
- li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
- TABORT(R9)
-
- /*
- * Return directly to userspace. We have corrupted user register state,
- * but userspace will never see that register state. Execution will
- * resume after the tbegin of the aborted transaction with the
- * checkpointed register state.
- */
- li r9, MSR_RI
- andc r10, r10, r9
- mtmsrd r10, 1
- mtspr SPRN_SRR0, r11
- mtspr SPRN_SRR1, r12
- RFI_TO_USER
- b . /* prevent speculative execution */
-#endif
-
/*
* If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not
* touched, no exit work created, then this can be used.
{
int index;
struct machine_check_event evt;
+ unsigned long msr;
if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
return;
memcpy(&local_paca->mce_info->mce_event_queue[index],
&evt, sizeof(evt));
- /* Queue irq work to process this event later. */
- irq_work_queue(&mce_event_process_work);
+ /*
+ * Queue irq work to process this event later. Before
+ * queuing the work enable translation for non radix LPAR,
+ * as irq_work_queue may try to access memory outside RMO
+ * region.
+ */
+ if (!radix_enabled() && firmware_has_feature(FW_FEATURE_LPAR)) {
+ msr = mfmsr();
+ mtmsr(msr | MSR_IR | MSR_DR);
+ irq_work_queue(&mce_event_process_work);
+ mtmsr(msr);
+ } else {
+ irq_work_queue(&mce_event_process_work);
+ }
}
void mce_common_process_ue(struct pt_regs *regs,
do_signal(current);
}
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+ if (thread_info_flags & _TIF_NOTIFY_RESUME)
tracehook_notify_resume(regs);
- rseq_handle_notify_resume(NULL, regs);
- }
}
static unsigned long get_tm_stackpointer(struct task_struct *tsk)
/* The following code handles the fake_suspend = 1 case */
mflr r0
std r0, PPC_LR_STKOFF(r1)
- stdu r1, -PPC_MIN_STKFRM(r1)
+ stdu r1, -TM_FRAME_SIZE(r1)
/* Turn on TM. */
mfmsr r8
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
nop
+ /*
+ * It's possible that treclaim. may modify registers, if we have lost
+ * track of fake-suspend state in the guest due to it using rfscv.
+ * Save and restore registers in case this occurs.
+ */
+ mfspr r3, SPRN_DSCR
+ mfspr r4, SPRN_XER
+ mfspr r5, SPRN_AMR
+ /* SPRN_TAR would need to be saved here if the kernel ever used it */
+ mfcr r12
+ SAVE_NVGPRS(r1)
+ SAVE_GPR(2, r1)
+ SAVE_GPR(3, r1)
+ SAVE_GPR(4, r1)
+ SAVE_GPR(5, r1)
+ stw r12, 8(r1)
+ std r1, HSTATE_HOST_R1(r13)
+
/* We have to treclaim here because that's the only way to do S->N */
li r3, TM_CAUSE_KVM_RESCHED
TRECLAIM(R3)
+ GET_PACA(r13)
+ ld r1, HSTATE_HOST_R1(r13)
+ REST_GPR(2, r1)
+ REST_GPR(3, r1)
+ REST_GPR(4, r1)
+ REST_GPR(5, r1)
+ lwz r12, 8(r1)
+ REST_NVGPRS(r1)
+ mtspr SPRN_DSCR, r3
+ mtspr SPRN_XER, r4
+ mtspr SPRN_AMR, r5
+ mtcr r12
+ HMT_MEDIUM
+
/*
* We were in fake suspend, so we are not going to save the
* register state as the guest checkpointed state (since
std r5, VCPU_TFHAR(r9)
std r6, VCPU_TFIAR(r9)
- addi r1, r1, PPC_MIN_STKFRM
+ addi r1, r1, TM_FRAME_SIZE
ld r0, PPC_LR_STKOFF(r1)
mtlr r0
blr
if (xics_ics->check(xics_ics, hwirq))
return -EINVAL;
- /* No chip data for the XICS domain */
+ /* Let the ICS be the chip data for the XICS domain. For ICS native */
irq_domain_set_info(domain, virq, hwirq, xics_ics->chip,
- NULL, handle_fasteoi_irq, NULL, NULL);
+ xics_ics, handle_fasteoi_irq, NULL, NULL);
return 0;
}
config ARCH_RV64I
bool "RV64I"
select 64BIT
- select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && GCC_VERSION >= 50000
+ select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && MMU && $(cc-option,-fpatchable-function-entry=8)
select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
The minimum size for the stack guard should be 256 for 31 bit and
512 for 64 bit.
-config WARN_DYNAMIC_STACK
- def_bool n
- prompt "Emit compiler warnings for function with dynamic stack usage"
- help
- This option enables the compiler option -mwarn-dynamicstack. If the
- compiler supports this options generates warnings for functions
- that dynamically allocate stack space using alloca.
-
- Say N if you are unsure.
-
endmenu
menu "I/O subsystem"
endif
endif
-ifdef CONFIG_WARN_DYNAMIC_STACK
- ifneq ($(call cc-option,-mwarn-dynamicstack),)
- KBUILD_CFLAGS += -mwarn-dynamicstack
- KBUILD_CFLAGS_DECOMPRESSOR += -mwarn-dynamicstack
- endif
-endif
-
ifdef CONFIG_EXPOLINE
ifneq ($(call cc-option,$(CC_FLAGS_MARCH) -mindirect-branch=thunk),)
CC_FLAGS_EXPOLINE := -mindirect-branch=thunk
CONFIG_BPF_JIT_ALWAYS_ON=y
CONFIG_BPF_LSM=y
CONFIG_PREEMPT=y
+CONFIG_SCHED_CORE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_LITEX is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_NFSD_V4=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_CIFS=m
-CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_CRC32=m
CONFIG_CRYPTO_BLAKE2S=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA3=m
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=0
CONFIG_DMA_API_DEBUG=y
-CONFIG_STRING_SELFTEST=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_LKDTM=m
CONFIG_TEST_MIN_HEAP=y
-CONFIG_TEST_SORT=y
CONFIG_KPROBES_SANITY_TEST=y
CONFIG_RBTREE_TEST=y
CONFIG_INTERVAL_TREE_TEST=m
CONFIG_PERCPU_TEST=m
CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_STRING_SELFTEST=y
CONFIG_TEST_BITOPS=m
CONFIG_TEST_BPF=m
CONFIG_TEST_LIVEPATCH=m
CONFIG_BPF_JIT=y
CONFIG_BPF_JIT_ALWAYS_ON=y
CONFIG_BPF_LSM=y
+CONFIG_SCHED_CORE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_LITEX is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_NFSD_V4=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_CIFS=m
-CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_CRC32=m
CONFIG_CRYPTO_BLAKE2S=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA3=m
int num_devices, const char *buf);
extern int ccwgroup_set_online(struct ccwgroup_device *gdev);
-extern int ccwgroup_set_offline(struct ccwgroup_device *gdev);
+int ccwgroup_set_offline(struct ccwgroup_device *gdev, bool call_gdrv);
extern int ccwgroup_probe_ccwdev(struct ccw_device *cdev);
extern void ccwgroup_remove_ccwdev(struct ccw_device *cdev);
#define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
({ \
- /* Branch instruction needs 6 bytes */ \
- int rel = (addrs[(i) + (off) + 1] - (addrs[(i) + 1] - 6)) / 2;\
+ int rel = (addrs[(i) + (off) + 1] - jit->prg) / 2; \
_EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\
REG_SET_SEEN(b1); \
REG_SET_SEEN(b2); \
EMIT4(0xb9080000, dst_reg, src_reg);
break;
case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
- if (!imm)
- break;
- /* alfi %dst,imm */
- EMIT6_IMM(0xc20b0000, dst_reg, imm);
+ if (imm != 0) {
+ /* alfi %dst,imm */
+ EMIT6_IMM(0xc20b0000, dst_reg, imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
EMIT4(0xb9090000, dst_reg, src_reg);
break;
case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
- if (!imm)
- break;
- /* alfi %dst,-imm */
- EMIT6_IMM(0xc20b0000, dst_reg, -imm);
+ if (imm != 0) {
+ /* alfi %dst,-imm */
+ EMIT6_IMM(0xc20b0000, dst_reg, -imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
if (!imm)
break;
- /* agfi %dst,-imm */
- EMIT6_IMM(0xc2080000, dst_reg, -imm);
+ if (imm == -0x80000000) {
+ /* algfi %dst,0x80000000 */
+ EMIT6_IMM(0xc20a0000, dst_reg, 0x80000000);
+ } else {
+ /* agfi %dst,-imm */
+ EMIT6_IMM(0xc2080000, dst_reg, -imm);
+ }
break;
/*
* BPF_MUL
EMIT4(0xb90c0000, dst_reg, src_reg);
break;
case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
- if (imm == 1)
- break;
- /* msfi %r5,imm */
- EMIT6_IMM(0xc2010000, dst_reg, imm);
+ if (imm != 1) {
+ /* msfi %r5,imm */
+ EMIT6_IMM(0xc2010000, dst_reg, imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
if (BPF_OP(insn->code) == BPF_MOD)
/* lhgi %dst,0 */
EMIT4_IMM(0xa7090000, dst_reg, 0);
+ else
+ EMIT_ZERO(dst_reg);
break;
}
/* lhi %w0,0 */
EMIT4(0xb9820000, dst_reg, src_reg);
break;
case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
- if (!imm)
- break;
- /* xilf %dst,imm */
- EMIT6_IMM(0xc0070000, dst_reg, imm);
+ if (imm != 0) {
+ /* xilf %dst,imm */
+ EMIT6_IMM(0xc0070000, dst_reg, imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
break;
case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
- if (imm == 0)
- break;
- /* sll %dst,imm(%r0) */
- EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
+ if (imm != 0) {
+ /* sll %dst,imm(%r0) */
+ EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
break;
case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
- if (imm == 0)
- break;
- /* srl %dst,imm(%r0) */
- EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
+ if (imm != 0) {
+ /* srl %dst,imm(%r0) */
+ EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
break;
case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
- if (imm == 0)
- break;
- /* sra %dst,imm(%r0) */
- EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
+ if (imm != 0) {
+ /* sra %dst,imm(%r0) */
+ EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
+ }
EMIT_ZERO(dst_reg);
break;
case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
mmap_read_lock(current->mm);
ret = -EINVAL;
- vma = find_vma(current->mm, mmio_addr);
+ vma = vma_lookup(current->mm, mmio_addr);
if (!vma)
goto out_unlock_mmap;
if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
mmap_read_lock(current->mm);
ret = -EINVAL;
- vma = find_vma(current->mm, mmio_addr);
+ vma = vma_lookup(current->mm, mmio_addr);
if (!vma)
goto out_unlock_mmap;
if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzo)
-$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
+$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 FORCE
$(call if_changed,uimage,bzip2)
-$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
+$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
$(call if_changed,uimage,gzip)
-$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
+$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE
$(call if_changed,uimage,lzma)
-$(obj)/uImage.xz: $(obj)/vmlinux.bin.xz
+$(obj)/uImage.xz: $(obj)/vmlinux.bin.xz FORCE
$(call if_changed,uimage,xz)
-$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
+$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
$(call if_changed,uimage,lzo)
-$(obj)/uImage.bin: $(obj)/vmlinux.bin
+$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
$(call if_changed,uimage,none)
OBJCOPYFLAGS_vmlinux.srec := -I binary -O srec
-$(obj)/vmlinux.srec: $(obj)/compressed/vmlinux
+$(obj)/vmlinux.srec: $(obj)/compressed/vmlinux FORCE
$(call if_changed,objcopy)
OBJCOPYFLAGS_uImage.srec := -I binary -O srec
-$(obj)/uImage.srec: $(obj)/uImage
+$(obj)/uImage.srec: $(obj)/uImage FORCE
$(call if_changed,objcopy)
$(obj)/uImage: $(obj)/uImage.$(suffix-y)
static inline pmd_t *pud_pgtable(pud_t pud)
{
- return (pmd_t *)pud_val(pud);
+ return (pmd_t *)(unsigned long)pud_val(pud);
}
/* only used by the stubbed out hugetlb gup code, should never be called */
void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
dma_addr_t dma_addr, unsigned long attrs)
{
- if (!sparc_dma_free_resource(cpu_addr, PAGE_ALIGN(size)))
+ size = PAGE_ALIGN(size);
+
+ if (!sparc_dma_free_resource(cpu_addr, size))
return;
dma_make_coherent(dma_addr, size);
u32 node_sz; /* node block size */
u32 name_sz; /* name block size */
u32 data_sz; /* data block size */
+ char data[];
} __attribute__((aligned(16)));
struct mdesc_elem {
static struct mdesc_elem *node_block(struct mdesc_hdr *mdesc)
{
- return (struct mdesc_elem *) (mdesc + 1);
+ return (struct mdesc_elem *) mdesc->data;
}
static void *name_block(struct mdesc_hdr *mdesc)
EXPORT_SYMBOL(ioport_map);
EXPORT_SYMBOL(ioport_unmap);
+#ifdef CONFIG_PCI
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
/* nothing to do */
}
EXPORT_SYMBOL(pci_iounmap);
+#endif
config ARCH_HIBERNATION_POSSIBLE
def_bool y
+config ARCH_NR_GPIO
+ int
+ default 1024 if X86_64
+ default 512
+
config ARCH_SUSPEND_POSSIBLE
def_bool y
config PCI_XEN
def_bool y
depends on PCI && XEN
- select SWIOTLB_XEN
config MMCONF_FAM10H
def_bool y
tune = $(call cc-option,-mtune=$(1),$(2))
+ifdef CONFIG_CC_IS_CLANG
+align := -falign-functions=0 $(call cc-option,-falign-jumps=0) $(call cc-option,-falign-loops=0)
+else
+align := -falign-functions=0 -falign-jumps=0 -falign-loops=0
+endif
+
cflags-$(CONFIG_M486SX) += -march=i486
cflags-$(CONFIG_M486) += -march=i486
cflags-$(CONFIG_M586) += -march=i586
# They make zero difference whatsosever to performance at this time.
cflags-$(CONFIG_MK7) += -march=athlon
cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon)
-cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0
-cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0
+cflags-$(CONFIG_MCRUSOE) += -march=i686 $(align)
+cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) $(align)
cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586)
cflags-$(CONFIG_MWINCHIP3D) += $(call cc-option,-march=winchip2,-march=i586)
-cflags-$(CONFIG_MCYRIXIII) += $(call cc-option,-march=c3,-march=i486) -falign-functions=0 -falign-jumps=0 -falign-loops=0
+cflags-$(CONFIG_MCYRIXIII) += $(call cc-option,-march=c3,-march=i486) $(align)
cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686)
cflags-$(CONFIG_MVIAC7) += -march=i686
cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2)
/*
* IPI implementation on Hyper-V.
*/
-static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
+static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector,
+ bool exclude_self)
{
struct hv_send_ipi_ex **arg;
struct hv_send_ipi_ex *ipi_arg;
if (!cpumask_equal(mask, cpu_present_mask)) {
ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
- nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
+ if (exclude_self)
+ nr_bank = cpumask_to_vpset_noself(&(ipi_arg->vp_set), mask);
+ else
+ nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
}
if (nr_bank < 0)
goto ipi_mask_ex_done;
return hv_result_success(status);
}
-static bool __send_ipi_mask(const struct cpumask *mask, int vector)
+static bool __send_ipi_mask(const struct cpumask *mask, int vector,
+ bool exclude_self)
{
- int cur_cpu, vcpu;
+ int cur_cpu, vcpu, this_cpu = smp_processor_id();
struct hv_send_ipi ipi_arg;
u64 status;
+ unsigned int weight;
trace_hyperv_send_ipi_mask(mask, vector);
- if (cpumask_empty(mask))
+ weight = cpumask_weight(mask);
+
+ /*
+ * Do nothing if
+ * 1. the mask is empty
+ * 2. the mask only contains self when exclude_self is true
+ */
+ if (weight == 0 ||
+ (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask)))
return true;
if (!hv_hypercall_pg)
ipi_arg.cpu_mask = 0;
for_each_cpu(cur_cpu, mask) {
+ if (exclude_self && cur_cpu == this_cpu)
+ continue;
vcpu = hv_cpu_number_to_vp_number(cur_cpu);
if (vcpu == VP_INVAL)
return false;
return hv_result_success(status);
do_ex_hypercall:
- return __send_ipi_mask_ex(mask, vector);
+ return __send_ipi_mask_ex(mask, vector, exclude_self);
}
static bool __send_ipi_one(int cpu, int vector)
return false;
if (vp >= 64)
- return __send_ipi_mask_ex(cpumask_of(cpu), vector);
+ return __send_ipi_mask_ex(cpumask_of(cpu), vector, false);
status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
return hv_result_success(status);
static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
{
- if (!__send_ipi_mask(mask, vector))
+ if (!__send_ipi_mask(mask, vector, false))
orig_apic.send_IPI_mask(mask, vector);
}
static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
{
- unsigned int this_cpu = smp_processor_id();
- struct cpumask new_mask;
- const struct cpumask *local_mask;
-
- cpumask_copy(&new_mask, mask);
- cpumask_clear_cpu(this_cpu, &new_mask);
- local_mask = &new_mask;
- if (!__send_ipi_mask(local_mask, vector))
+ if (!__send_ipi_mask(mask, vector, true))
orig_apic.send_IPI_mask_allbutself(mask, vector);
}
static void hv_send_ipi_all(int vector)
{
- if (!__send_ipi_mask(cpu_online_mask, vector))
+ if (!__send_ipi_mask(cpu_online_mask, vector, false))
orig_apic.send_IPI_all(vector);
}
#ifndef _ASM_X86_PKEYS_H
#define _ASM_X86_PKEYS_H
-#define ARCH_DEFAULT_PKEY 0
-
/*
* If more than 16 keys are ever supported, a thorough audit
* will be necessary to ensure that the types that store key
{
const struct { char _[64]; } *__src = src;
struct { char _[64]; } __iomem *__dst = dst;
- int zf;
+ bool zf;
/*
* ENQCMDS %(rdx), rax
unsigned int __gu_low, __gu_high; \
const unsigned int __user *__gu_ptr; \
__gu_ptr = (const void __user *)(ptr); \
- __get_user_asm(__gu_low, ptr, "l", "=r", label); \
- __get_user_asm(__gu_high, ptr+1, "l", "=r", label); \
+ __get_user_asm(__gu_low, __gu_ptr, "l", "=r", label); \
+ __get_user_asm(__gu_high, __gu_ptr+1, "l", "=r", label); \
(x) = ((unsigned long long)__gu_high << 32) | __gu_low; \
} while (0)
#else
#define _ASM_X86_SWIOTLB_XEN_H
#ifdef CONFIG_SWIOTLB_XEN
-extern int xen_swiotlb;
extern int __init pci_xen_swiotlb_detect(void);
-extern void __init pci_xen_swiotlb_init(void);
extern int pci_xen_swiotlb_init_late(void);
#else
-#define xen_swiotlb (0)
-static inline int __init pci_xen_swiotlb_detect(void) { return 0; }
-static inline void __init pci_xen_swiotlb_init(void) { }
+#define pci_xen_swiotlb_detect NULL
static inline int pci_xen_swiotlb_init_late(void) { return -ENXIO; }
#endif
static void kill_me_now(struct callback_head *ch)
{
+ struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me);
+
+ p->mce_count = 0;
force_sig(SIGBUS);
}
int flags = MF_ACTION_REQUIRED;
int ret;
+ p->mce_count = 0;
pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
if (!p->mce_ripv)
}
}
-static void queue_task_work(struct mce *m, int kill_current_task)
+static void queue_task_work(struct mce *m, char *msg, int kill_current_task)
{
- current->mce_addr = m->addr;
- current->mce_kflags = m->kflags;
- current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
- current->mce_whole_page = whole_page(m);
+ int count = ++current->mce_count;
- if (kill_current_task)
- current->mce_kill_me.func = kill_me_now;
- else
- current->mce_kill_me.func = kill_me_maybe;
+ /* First call, save all the details */
+ if (count == 1) {
+ current->mce_addr = m->addr;
+ current->mce_kflags = m->kflags;
+ current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
+ current->mce_whole_page = whole_page(m);
+
+ if (kill_current_task)
+ current->mce_kill_me.func = kill_me_now;
+ else
+ current->mce_kill_me.func = kill_me_maybe;
+ }
+
+ /* Ten is likely overkill. Don't expect more than two faults before task_work() */
+ if (count > 10)
+ mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
+
+ /* Second or later call, make sure page address matches the one from first call */
+ if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
+ mce_panic("Consecutive machine checks to different user pages", m, msg);
+
+ /* Do not call task_work_add() more than once */
+ if (count > 1)
+ return;
task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
}
/* If this triggers there is no way to recover. Die hard. */
BUG_ON(!on_thread_stack() || !user_mode(regs));
- queue_task_work(&m, kill_current_task);
+ queue_task_work(&m, msg, kill_current_task);
} else {
/*
}
if (m.kflags & MCE_IN_KERNEL_COPYIN)
- queue_task_work(&m, kill_current_task);
+ queue_task_work(&m, msg, kill_current_task);
}
out:
mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
x86_init.oem.arch_setup();
+ /*
+ * Do some memory reservations *before* memory is added to memblock, so
+ * memblock allocations won't overwrite it.
+ *
+ * After this point, everything still needed from the boot loader or
+ * firmware or kernel text should be early reserved or marked not RAM in
+ * e820. All other memory is free game.
+ *
+ * This call needs to happen before e820__memory_setup() which calls the
+ * xen_memory_setup() on Xen dom0 which relies on the fact that those
+ * early reservations have happened already.
+ */
+ early_reserve_memory();
+
iomem_resource.end = (1ULL << boot_cpu_data.x86_phys_bits) - 1;
e820__memory_setup();
parse_setup_data();
parse_early_param();
- /*
- * Do some memory reservations *before* memory is added to
- * memblock, so memblock allocations won't overwrite it.
- * Do it after early param, so we could get (unlikely) panic from
- * serial.
- *
- * After this point everything still needed from the boot loader or
- * firmware or kernel text should be early reserved or marked not
- * RAM in e820. All other memory is free game.
- */
- early_reserve_memory();
-
#ifdef CONFIG_MEMORY_HOTPLUG
/*
* Memory used by the kernel cannot be hot-removed because Linux
static void __init pcpu_fc_free(void *ptr, size_t size)
{
- memblock_free(__pa(ptr), size);
+ memblock_free_ptr(ptr, size);
}
static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
#define __get_next(t, insn) \
- ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); leXX_to_cpu(t, r); })
+ ({ t r; memcpy(&r, insn->next_byte, sizeof(t)); insn->next_byte += sizeof(t); leXX_to_cpu(t, r); })
#define __peek_nbyte_next(t, insn, n) \
- ({ t r = *(t*)((insn)->next_byte + n); leXX_to_cpu(t, r); })
+ ({ t r; memcpy(&r, (insn)->next_byte + n, sizeof(t)); leXX_to_cpu(t, r); })
#define get_next(t, insn) \
({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
static noinline void
kernelmode_fixup_or_oops(struct pt_regs *regs, unsigned long error_code,
- unsigned long address, int signal, int si_code)
+ unsigned long address, int signal, int si_code,
+ u32 pkey)
{
WARN_ON_ONCE(user_mode(regs));
set_signal_archinfo(address, error_code);
- /* XXX: hwpoison faults will set the wrong code. */
- force_sig_fault(signal, si_code, (void __user *)address);
+ if (si_code == SEGV_PKUERR) {
+ force_sig_pkuerr((void __user *)address, pkey);
+ } else {
+ /* XXX: hwpoison faults will set the wrong code. */
+ force_sig_fault(signal, si_code, (void __user *)address);
+ }
}
/*
struct task_struct *tsk = current;
if (!user_mode(regs)) {
- kernelmode_fixup_or_oops(regs, error_code, address, pkey, si_code);
+ kernelmode_fixup_or_oops(regs, error_code, address,
+ SIGSEGV, si_code, pkey);
return;
}
{
/* Kernel mode? Handle exceptions or die: */
if (!user_mode(regs)) {
- kernelmode_fixup_or_oops(regs, error_code, address, SIGBUS, BUS_ADRERR);
+ kernelmode_fixup_or_oops(regs, error_code, address,
+ SIGBUS, BUS_ADRERR, ARCH_DEFAULT_PKEY);
return;
}
*/
if (!user_mode(regs))
kernelmode_fixup_or_oops(regs, error_code, address,
- SIGBUS, BUS_ADRERR);
+ SIGBUS, BUS_ADRERR,
+ ARCH_DEFAULT_PKEY);
return;
}
return;
if (fatal_signal_pending(current) && !user_mode(regs)) {
- kernelmode_fixup_or_oops(regs, error_code, address, 0, 0);
+ kernelmode_fixup_or_oops(regs, error_code, address,
+ 0, 0, ARCH_DEFAULT_PKEY);
return;
}
/* Kernel mode? Handle exceptions or die: */
if (!user_mode(regs)) {
kernelmode_fixup_or_oops(regs, error_code, address,
- SIGSEGV, SEGV_MAPERR);
+ SIGSEGV, SEGV_MAPERR,
+ ARCH_DEFAULT_PKEY);
return;
}
return 0;
p4d = p4d_offset(pgd, addr);
- if (p4d_none(*p4d))
+ if (!p4d_present(*p4d))
return 0;
pud = pud_offset(p4d, addr);
- if (pud_none(*pud))
+ if (!pud_present(*pud))
return 0;
if (pud_large(*pud))
return pfn_valid(pud_pfn(*pud));
pmd = pmd_offset(pud, addr);
- if (pmd_none(*pmd))
+ if (!pmd_present(*pmd))
return 0;
if (pmd_large(*pmd))
p = early_alloc(PMD_SIZE, nid, false);
if (p && pmd_set_huge(pmd, __pa(p), PAGE_KERNEL))
return;
- else if (p)
- memblock_free(__pa(p), PMD_SIZE);
+ memblock_free_ptr(p, PMD_SIZE);
}
p = early_alloc(PAGE_SIZE, nid, true);
p = early_alloc(PUD_SIZE, nid, false);
if (p && pud_set_huge(pud, __pa(p), PAGE_KERNEL))
return;
- else if (p)
- memblock_free(__pa(p), PUD_SIZE);
+ memblock_free_ptr(p, PUD_SIZE);
}
p = early_alloc(PAGE_SIZE, nid, true);
/* numa_distance could be 1LU marking allocation failure, test cnt */
if (numa_distance_cnt)
- memblock_free(__pa(numa_distance), size);
+ memblock_free_ptr(numa_distance, size);
numa_distance_cnt = 0;
numa_distance = NULL; /* enable table creation */
}
}
/* free the copied physical distance table */
- if (phys_dist)
- memblock_free(__pa(phys_dist), phys_size);
+ memblock_free_ptr(phys_dist, phys_size);
return;
no_emu:
int err = 0;
start = sanitize_phys(start);
- end = sanitize_phys(end);
+
+ /*
+ * The end address passed into this function is exclusive, but
+ * sanitize_phys() expects an inclusive address.
+ */
+ end = sanitize_phys(end - 1) + 1;
if (start >= end) {
WARN(1, "%s failed: [mem %#010Lx-%#010Lx], req %s\n", __func__,
start, end - 1, cattr_name(req_type));
preempt_enable();
}
-static void xen_convert_trap_info(const struct desc_ptr *desc,
- struct trap_info *traps)
+static unsigned xen_convert_trap_info(const struct desc_ptr *desc,
+ struct trap_info *traps, bool full)
{
unsigned in, out, count;
for (in = out = 0; in < count; in++) {
gate_desc *entry = (gate_desc *)(desc->address) + in;
- if (cvt_gate_to_trap(in, entry, &traps[out]))
+ if (cvt_gate_to_trap(in, entry, &traps[out]) || full)
out++;
}
- traps[out].address = 0;
+
+ return out;
}
void xen_copy_trap_info(struct trap_info *traps)
{
const struct desc_ptr *desc = this_cpu_ptr(&idt_desc);
- xen_convert_trap_info(desc, traps);
+ xen_convert_trap_info(desc, traps, true);
}
/* Load a new IDT into Xen. In principle this can be per-CPU, so we
{
static DEFINE_SPINLOCK(lock);
static struct trap_info traps[257];
+ unsigned out;
trace_xen_cpu_load_idt(desc);
memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
- xen_convert_trap_info(desc, traps);
+ out = xen_convert_trap_info(desc, traps, false);
+ memset(&traps[out], 0, sizeof(traps[0]));
xen_mc_flush();
if (HYPERVISOR_set_trap_table(traps))
x86_platform.legacy.rtc = 1;
}
+static void __init xen_domu_set_legacy_features(void)
+{
+ x86_platform.legacy.rtc = 0;
+}
+
/* First C function to be called on Xen boot */
asmlinkage __visible void __init xen_start_kernel(void)
{
add_preferred_console("xenboot", 0, NULL);
if (pci_xen)
x86_init.pci.arch_init = pci_xen_init;
+ x86_platform.set_legacy_features =
+ xen_domu_set_legacy_features;
} else {
const struct dom0_vga_console_info *info =
(void *)((char *)xen_start_info +
if (pinned) {
struct page *page = pfn_to_page(pfn);
- if (static_branch_likely(&xen_struct_pages_ready))
+ pinned = false;
+ if (static_branch_likely(&xen_struct_pages_ready)) {
+ pinned = PagePinned(page);
SetPagePinned(page);
+ }
xen_mc_batch();
__set_pfn_prot(pfn, PAGE_KERNEL_RO);
- if (level == PT_PTE && USE_SPLIT_PTE_PTLOCKS)
+ if (level == PT_PTE && USE_SPLIT_PTE_PTLOCKS && !pinned)
__pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
xen_mc_issue(PARAVIRT_LAZY_MMU);
#endif
#include <linux/export.h>
-int xen_swiotlb __read_mostly;
+static int xen_swiotlb __read_mostly;
/*
* pci_xen_swiotlb_detect - set xen_swiotlb to 1 if necessary
return xen_swiotlb;
}
-void __init pci_xen_swiotlb_init(void)
+static void __init pci_xen_swiotlb_init(void)
{
if (xen_swiotlb) {
xen_swiotlb_init_early();
gdt = get_cpu_gdt_rw(cpu);
- memset(&ctxt->fpu_ctxt, 0, sizeof(ctxt->fpu_ctxt));
-
/*
* Bring up the CPU in cpu_bringup_and_idle() with the stack
* pointing just below where pt_regs would be if it were a normal
xen_copy_trap_info(ctxt->trap_ctxt);
- ctxt->ldt_ents = 0;
-
BUG_ON((unsigned long)gdt & ~PAGE_MASK);
gdt_mfn = arbitrary_virt_to_mfn(gdt);
if (!bio_integrity_endio(bio))
return;
- if (bio->bi_bdev)
+ if (bio->bi_bdev && bio_flagged(bio, BIO_TRACKED))
rq_qos_done_bio(bio->bi_bdev->bd_disk->queue, bio);
if (bio->bi_bdev && bio_flagged(bio, BIO_TRACE_COMPLETION)) {
if (preloaded)
radix_tree_preload_end();
- ret = blk_iolatency_init(q);
- if (ret)
- goto err_destroy_all;
-
ret = blk_ioprio_init(q);
if (ret)
goto err_destroy_all;
if (ret)
goto err_destroy_all;
+ ret = blk_iolatency_init(q);
+ if (ret) {
+ blk_throtl_exit(q);
+ goto err_destroy_all;
+ }
+
return 0;
err_destroy_all:
/* alloc failed, nothing's initialized yet, free everything */
spin_lock_irq(&q->queue_lock);
list_for_each_entry(blkg, &q->blkg_list, q_node) {
+ struct blkcg *blkcg = blkg->blkcg;
+
+ spin_lock(&blkcg->lock);
if (blkg->pd[pol->plid]) {
pol->pd_free_fn(blkg->pd[pol->plid]);
blkg->pd[pol->plid] = NULL;
}
+ spin_unlock(&blkcg->lock);
}
spin_unlock_irq(&q->queue_lock);
ret = -ENOMEM;
__clear_bit(pol->plid, q->blkcg_pols);
list_for_each_entry(blkg, &q->blkg_list, q_node) {
+ struct blkcg *blkcg = blkg->blkcg;
+
+ spin_lock(&blkcg->lock);
if (blkg->pd[pol->plid]) {
if (pol->pd_offline_fn)
pol->pd_offline_fn(blkg->pd[pol->plid]);
pol->pd_free_fn(blkg->pd[pol->plid]);
blkg->pd[pol->plid] = NULL;
}
+ spin_unlock(&blkcg->lock);
}
spin_unlock_irq(&q->queue_lock);
*/
void blk_integrity_unregister(struct gendisk *disk)
{
+ struct blk_integrity *bi = &disk->queue->integrity;
+
+ if (!bi->profile)
+ return;
+
+ /* ensure all bios are off the integrity workqueue */
+ blk_flush_integrity();
blk_queue_flag_clear(QUEUE_FLAG_STABLE_WRITES, disk->queue);
- memset(&disk->queue->integrity, 0, sizeof(struct blk_integrity));
+ memset(bi, 0, sizeof(*bi));
}
EXPORT_SYMBOL(blk_integrity_unregister);
spin_lock_irqsave(&tags->lock, flags);
rq = tags->rqs[bitnr];
- if (!rq || !refcount_inc_not_zero(&rq->ref))
+ if (!rq || rq->tag != bitnr || !refcount_inc_not_zero(&rq->ref))
rq = NULL;
spin_unlock_irqrestore(&tags->lock, flags);
return rq;
.llseek = default_llseek,
};
+static void bsg_device_release(struct device *dev)
+{
+ struct bsg_device *bd = container_of(dev, struct bsg_device, device);
+
+ ida_simple_remove(&bsg_minor_ida, MINOR(bd->device.devt));
+ kfree(bd);
+}
+
void bsg_unregister_queue(struct bsg_device *bd)
{
if (bd->queue->kobj.sd)
sysfs_remove_link(&bd->queue->kobj, "bsg");
cdev_device_del(&bd->cdev, &bd->device);
- ida_simple_remove(&bsg_minor_ida, MINOR(bd->device.devt));
- kfree(bd);
+ put_device(&bd->device);
}
EXPORT_SYMBOL_GPL(bsg_unregister_queue);
if (ret < 0) {
if (ret == -ENOSPC)
dev_err(parent, "bsg: too many bsg devices\n");
- goto out_kfree;
+ kfree(bd);
+ return ERR_PTR(ret);
}
bd->device.devt = MKDEV(bsg_major, ret);
bd->device.class = bsg_class;
bd->device.parent = parent;
+ bd->device.release = bsg_device_release;
dev_set_name(&bd->device, "%s", name);
device_initialize(&bd->device);
bd->cdev.owner = THIS_MODULE;
ret = cdev_device_add(&bd->cdev, &bd->device);
if (ret)
- goto out_ida_remove;
+ goto out_put_device;
if (q->kobj.sd) {
ret = sysfs_create_link(&q->kobj, &bd->device.kobj, "bsg");
out_device_del:
cdev_device_del(&bd->cdev, &bd->device);
-out_ida_remove:
- ida_simple_remove(&bsg_minor_ida, MINOR(bd->device.devt));
-out_kfree:
- kfree(bd);
+out_put_device:
+ put_device(&bd->device);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(bsg_register_queue);
#include <linux/task_io_accounting_ops.h>
#include <linux/falloc.h>
#include <linux/suspend.h>
+#include <linux/fs.h>
#include "blk.h"
static struct inode *bdev_file_inode(struct file *file)
static long blkdev_fallocate(struct file *file, int mode, loff_t start,
loff_t len)
{
- struct block_device *bdev = I_BDEV(bdev_file_inode(file));
+ struct inode *inode = bdev_file_inode(file);
+ struct block_device *bdev = I_BDEV(inode);
loff_t end = start + len - 1;
loff_t isize;
int error;
if ((start | len) & (bdev_logical_block_size(bdev) - 1))
return -EINVAL;
+ filemap_invalidate_lock(inode->i_mapping);
+
/* Invalidate the page cache, including dirty pages. */
error = truncate_bdev_range(bdev, file->f_mode, start, end);
if (error)
- return error;
+ goto fail;
switch (mode) {
case FALLOC_FL_ZERO_RANGE:
GFP_KERNEL, 0);
break;
default:
- return -EOPNOTSUPP;
+ error = -EOPNOTSUPP;
}
- if (error)
- return error;
- /*
- * Invalidate the page cache again; if someone wandered in and dirtied
- * a page, we just discard it - userspace has no way of knowing whether
- * the write happened before or after discard completing...
- */
- return truncate_bdev_range(bdev, file->f_mode, start, end);
+ fail:
+ filemap_invalidate_unlock(inode->i_mapping);
+ return error;
}
const struct file_operations def_blk_fops = {
#define should_use_kmap(pfn) page_is_ram(pfn)
#endif
-static void __iomem *acpi_map(acpi_physical_address pg_off, unsigned long pg_sz,
- bool memory)
+static void __iomem *acpi_map(acpi_physical_address pg_off, unsigned long pg_sz)
{
unsigned long pfn;
return NULL;
return (void __iomem __force *)kmap(pfn_to_page(pfn));
} else
- return memory ? acpi_os_memmap(pg_off, pg_sz) :
- acpi_os_ioremap(pg_off, pg_sz);
+ return acpi_os_ioremap(pg_off, pg_sz);
}
static void acpi_unmap(acpi_physical_address pg_off, void __iomem *vaddr)
}
/**
- * __acpi_os_map_iomem - Get a virtual address for a given physical address range.
+ * acpi_os_map_iomem - Get a virtual address for a given physical address range.
* @phys: Start of the physical address range to map.
* @size: Size of the physical address range to map.
- * @memory: true if remapping memory, false if IO
*
* Look up the given physical address range in the list of existing ACPI memory
* mappings. If found, get a reference to it and return a pointer to it (its
* During early init (when acpi_permanent_mmap has not been set yet) this
* routine simply calls __acpi_map_table() to get the job done.
*/
-static void __iomem __ref
-*__acpi_os_map_iomem(acpi_physical_address phys, acpi_size size, bool memory)
+void __iomem __ref
+*acpi_os_map_iomem(acpi_physical_address phys, acpi_size size)
{
struct acpi_ioremap *map;
void __iomem *virt;
pg_off = round_down(phys, PAGE_SIZE);
pg_sz = round_up(phys + size, PAGE_SIZE) - pg_off;
- virt = acpi_map(phys, size, memory);
+ virt = acpi_map(phys, size);
if (!virt) {
mutex_unlock(&acpi_ioremap_lock);
kfree(map);
mutex_unlock(&acpi_ioremap_lock);
return map->virt + (phys - map->phys);
}
-
-void __iomem *__ref
-acpi_os_map_iomem(acpi_physical_address phys, acpi_size size)
-{
- return __acpi_os_map_iomem(phys, size, false);
-}
EXPORT_SYMBOL_GPL(acpi_os_map_iomem);
void *__ref acpi_os_map_memory(acpi_physical_address phys, acpi_size size)
{
- return (void *)__acpi_os_map_iomem(phys, size, true);
+ return (void *)acpi_os_map_iomem(phys, size);
}
EXPORT_SYMBOL_GPL(acpi_os_map_memory);
}
static void binder_transaction_buffer_release(struct binder_proc *proc,
+ struct binder_thread *thread,
struct binder_buffer *buffer,
binder_size_t failed_at,
bool is_failure)
&proc->alloc, &fd, buffer,
offset, sizeof(fd));
WARN_ON(err);
- if (!err)
+ if (!err) {
binder_deferred_fd_close(fd);
+ /*
+ * Need to make sure the thread goes
+ * back to userspace to complete the
+ * deferred close
+ */
+ if (thread)
+ thread->looper_need_return = true;
+ }
}
} break;
default:
if (reply) {
binder_enqueue_thread_work(thread, tcomplete);
binder_inner_proc_lock(target_proc);
- if (target_thread->is_dead || target_proc->is_frozen) {
- return_error = target_thread->is_dead ?
- BR_DEAD_REPLY : BR_FROZEN_REPLY;
+ if (target_thread->is_dead) {
+ return_error = BR_DEAD_REPLY;
binder_inner_proc_unlock(target_proc);
goto err_dead_proc_or_thread;
}
err_copy_data_failed:
binder_free_txn_fixups(t);
trace_binder_transaction_failed_buffer_release(t->buffer);
- binder_transaction_buffer_release(target_proc, t->buffer,
+ binder_transaction_buffer_release(target_proc, NULL, t->buffer,
buffer_offset, true);
if (target_node)
binder_dec_node_tmpref(target_node);
* Cleanup buffer and free it.
*/
static void
-binder_free_buf(struct binder_proc *proc, struct binder_buffer *buffer)
+binder_free_buf(struct binder_proc *proc,
+ struct binder_thread *thread,
+ struct binder_buffer *buffer)
{
binder_inner_proc_lock(proc);
if (buffer->transaction) {
binder_node_inner_unlock(buf_node);
}
trace_binder_transaction_buffer_release(buffer);
- binder_transaction_buffer_release(proc, buffer, 0, false);
+ binder_transaction_buffer_release(proc, thread, buffer, 0, false);
binder_alloc_free_buf(&proc->alloc, buffer);
}
proc->pid, thread->pid, (u64)data_ptr,
buffer->debug_id,
buffer->transaction ? "active" : "finished");
- binder_free_buf(proc, buffer);
+ binder_free_buf(proc, thread, buffer);
break;
}
buffer->transaction = NULL;
binder_cleanup_transaction(t, "fd fixups failed",
BR_FAILED_REPLY);
- binder_free_buf(proc, buffer);
+ binder_free_buf(proc, thread, buffer);
binder_debug(BINDER_DEBUG_FAILED_TRANSACTION,
"%d:%d %stransaction %d fd fixups failed %d/%d, line %d\n",
proc->pid, thread->pid,
return 0;
}
+static bool binder_txns_pending_ilocked(struct binder_proc *proc)
+{
+ struct rb_node *n;
+ struct binder_thread *thread;
+
+ if (proc->outstanding_txns > 0)
+ return true;
+
+ for (n = rb_first(&proc->threads); n; n = rb_next(n)) {
+ thread = rb_entry(n, struct binder_thread, rb_node);
+ if (thread->transaction_stack)
+ return true;
+ }
+ return false;
+}
+
static int binder_ioctl_freeze(struct binder_freeze_info *info,
struct binder_proc *target_proc)
{
(!target_proc->outstanding_txns),
msecs_to_jiffies(info->timeout_ms));
- if (!ret && target_proc->outstanding_txns)
- ret = -EAGAIN;
+ /* Check pending transactions that wait for reply */
+ if (ret >= 0) {
+ binder_inner_proc_lock(target_proc);
+ if (binder_txns_pending_ilocked(target_proc))
+ ret = -EAGAIN;
+ binder_inner_proc_unlock(target_proc);
+ }
if (ret < 0) {
binder_inner_proc_lock(target_proc);
{
struct binder_proc *target_proc;
bool found = false;
+ __u32 txns_pending;
info->sync_recv = 0;
info->async_recv = 0;
if (target_proc->pid == info->pid) {
found = true;
binder_inner_proc_lock(target_proc);
- info->sync_recv |= target_proc->sync_recv;
+ txns_pending = binder_txns_pending_ilocked(target_proc);
+ info->sync_recv |= target_proc->sync_recv |
+ (txns_pending << 1);
info->async_recv |= target_proc->async_recv;
binder_inner_proc_unlock(target_proc);
}
* binder transactions
* (protected by @inner_lock)
* @sync_recv: process received sync transactions since last frozen
+ * bit 0: received sync transaction after being frozen
+ * bit 1: new pending sync transaction during freezing
* (protected by @inner_lock)
* @async_recv: process received async transactions since last frozen
* (protected by @inner_lock)
size = numa_distance_cnt * numa_distance_cnt *
sizeof(numa_distance[0]);
- memblock_free(__pa(numa_distance), size);
+ memblock_free_ptr(numa_distance, size);
numa_distance_cnt = 0;
numa_distance = NULL;
}
#include <linux/export.h>
#include <linux/rtc.h>
#include <linux/suspend.h>
+#include <linux/init.h>
#include <linux/mc146818rtc.h>
const char *file = *(const char **)(tracedata + 2);
unsigned int user_hash_value, file_hash_value;
+ if (!x86_platform.legacy.rtc)
+ return;
+
user_hash_value = user % USERHASH;
file_hash_value = hash_string(lineno, file, FILEHASH);
set_magic_time(user_hash_value, file_hash_value, dev_hash_value);
static int __init early_resume_init(void)
{
+ if (!x86_platform.legacy.rtc)
+ return 0;
+
hash_value_early_read = read_magic_time();
register_pm_notifier(&pm_trace_nb);
return 0;
unsigned int val = hash_value_early_read;
unsigned int user, file, dev;
+ if (!x86_platform.legacy.rtc)
+ return 0;
+
user = val % USERHASH;
val = val / USERHASH;
file = val % FILEHASH;
to_swnode(fwnode)->managed = true;
set_secondary_fwnode(dev, fwnode);
+ if (device_is_registered(dev))
+ software_node_notify(dev);
+
return 0;
}
EXPORT_SYMBOL_GPL(device_create_managed_software_node);
mutex_lock(&dev->mutex);
rc = do_insnlist_ioctl(dev, insns, insnlist32.n_insns, file);
mutex_unlock(&dev->mutex);
+ kfree(insns);
return rc;
}
if (count)
return count;
- kobject_put(&attr_set->kobj);
mutex_destroy(&attr_set->update_lock);
+ kobject_put(&attr_set->kobj);
return 0;
}
EXPORT_SYMBOL_GPL(gov_attr_set_put);
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return -ENODEV;
- if (no_load)
- return -ENODEV;
-
id = x86_match_cpu(hwp_support_ids);
if (id) {
+ bool hwp_forced = intel_pstate_hwp_is_enabled();
+
+ if (hwp_forced)
+ pr_info("HWP enabled by BIOS\n");
+ else if (no_load)
+ return -ENODEV;
+
copy_cpu_funcs(&core_funcs);
/*
* Avoid enabling HWP for processors without EPP support,
* If HWP is enabled already, though, there is no choice but to
* deal with it.
*/
- if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) ||
- intel_pstate_hwp_is_enabled()) {
+ if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
hwp_active++;
hwp_mode_bdw = id->driver_data;
intel_pstate.attr = hwp_cpufreq_attrs;
goto hwp_cpu_matched;
}
+ pr_info("HWP not enabled\n");
} else {
+ if (no_load)
+ return -ENODEV;
+
id = x86_match_cpu(intel_pstate_cpu_ids);
if (!id) {
pr_info("CPU model not supported\n");
else if (!strcmp(str, "passive"))
default_driver = &intel_cpufreq;
- if (!strcmp(str, "no_hwp")) {
- pr_info("HWP disabled\n");
+ if (!strcmp(str, "no_hwp"))
no_hwp = 1;
- }
+
if (!strcmp(str, "force"))
force_load = 1;
if (!strcmp(str, "hwp_only"))
static int ve_spc_cpufreq_exit(struct cpufreq_policy *policy)
{
struct device *cpu_dev;
- int cur_cluster = cpu_to_cluster(policy->cpu);
cpu_dev = get_cpu_device(policy->cpu);
if (!cpu_dev) {
dimm->grain = pvt->mem_width_in_bytes;
dimm->dtype = dt;
dimm->mtype = mt;
- dimm->edac_mode = EDAC_FLAG_SECDED;
+ dimm->edac_mode = EDAC_SECDED;
dimm->nr_pages = pages_per_rank / csi->nr_channels;
}
}
for (j = 0; j < csi->nr_channels; j++) {
dimm = csi->channels[j]->dimm;
- dimm->edac_mode = EDAC_FLAG_SECDED;
+ dimm->edac_mode = EDAC_SECDED;
dimm->mtype = p_data->get_mtype(priv->baseaddr);
dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
dimm->grain = SYNPS_EDAC_ERR_GRAIN;
{
unsigned int irq_base, nr_irqs;
struct dfl_feature_info *finfo;
+ u8 revision = 0;
int ret;
- u8 revision;
u64 v;
- v = readq(binfo->ioaddr + ofst);
- revision = FIELD_GET(DFH_REVISION, v);
+ if (fid != FEATURE_ID_AFU) {
+ v = readq(binfo->ioaddr + ofst);
+ revision = FIELD_GET(DFH_REVISION, v);
- /* read feature size and id if inputs are invalid */
- size = size ? size : feature_size(v);
- fid = fid ? fid : feature_id(v);
+ /* read feature size and id if inputs are invalid */
+ size = size ? size : feature_size(v);
+ fid = fid ? fid : feature_id(v);
+ }
if (binfo->len - ofst < size)
return -EINVAL;
goto fail;
get_status(spi, &status);
- if (test_bit(FAIL, &status))
+ if (test_bit(FAIL, &status)) {
+ ret = -EINVAL;
goto fail;
+ }
dump_status_reg(&status);
spi_message_init(&msg);
dump_status_reg(&status);
if (!test_bit(DONE, &status)) {
machxo2_cleanup(mgr);
+ ret = -EINVAL;
goto fail;
}
break;
if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
machxo2_cleanup(mgr);
+ ret = -EINVAL;
goto fail;
}
} while (1);
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, ®, 32)
- generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
+ generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
}
chained_irq_exit(ic, desc);
u32 data;
data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
- if (data & BIT(offset))
+ if (data)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
unsigned int cur_div_reg;
u64 div;
- if (!IS_ERR(bank->db_clk)) {
+ if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
div_debounce_support = true;
freq = clk_get_rate(bank->db_clk);
max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
- return irq_chip_mask_parent(data);
+ irq_chip_mask_parent(data);
}
static void uniphier_gpio_irq_unmask(struct irq_data *data)
uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
- return irq_chip_unmask_parent(data);
+ irq_chip_unmask_parent(data);
}
static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
ret = gpio_set_debounce_timeout(desc, agpio->debounce_timeout);
if (ret)
- gpiochip_free_own_desc(desc);
+ dev_warn(chip->parent,
+ "Failed to set debounce-timeout for pin 0x%04X, err %d\n",
+ pin, ret);
- return ret ? ERR_PTR(ret) : desc;
+ return desc;
}
static bool acpi_gpio_in_ignore_list(const char *controller_in, int pin_in)
MAX_HWIP
};
-#define HWIP_MAX_INSTANCE 8
+#define HWIP_MAX_INSTANCE 10
struct amd_powerplay {
void *pp_handle;
kgd2kfd_suspend(adev->kfd.dev, run_pm);
}
+int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (adev->kfd.dev)
+ r = kgd2kfd_resume_iommu(adev->kfd.dev);
+
+ return r;
+}
+
int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
{
int r = 0;
void amdgpu_amdkfd_fini(void);
void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
+int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
const void *ih_ring_entry);
const struct kgd2kfd_shared_resources *gpu_resources);
void kgd2kfd_device_exit(struct kfd_dev *kfd);
void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
+int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
int kgd2kfd_pre_reset(struct kfd_dev *kfd);
int kgd2kfd_post_reset(struct kfd_dev *kfd);
{
}
+static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
+{
+ return 0;
+}
+
static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
{
return 0;
struct dentry *ent;
int r, i;
-
-
ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
&fops_ib_preempt);
- if (!ent) {
+ if (IS_ERR(ent)) {
DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
- return -EIO;
+ return PTR_ERR(ent);
}
ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
&fops_sclk_set);
- if (!ent) {
+ if (IS_ERR(ent)) {
DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
- return -EIO;
+ return PTR_ERR(ent);
}
/* Register debugfs entries for amdgpu_ttm */
if (r)
goto init_failed;
+ r = amdgpu_amdkfd_resume_iommu(adev);
+ if (r)
+ goto init_failed;
+
r = amdgpu_device_ip_hw_init_phase1(adev);
if (r)
goto init_failed;
{
int r;
+ r = amdgpu_amdkfd_resume_iommu(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_resume_phase1(adev);
if (r)
return r;
dev_warn(tmp_adev->dev, "asic atom init failed!");
} else {
dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
+ r = amdgpu_amdkfd_resume_iommu(tmp_adev);
+ if (r)
+ goto out;
+
r = amdgpu_device_ip_resume_phase1(tmp_adev);
if (r)
goto out;
break;
default:
adev->gmc.tmz_enabled = false;
- dev_warn(adev->dev,
+ dev_info(adev->dev,
"Trusted Memory Zone (TMZ) feature not supported\n");
break;
}
return res;
}
-inline uint32_t amdgpu_ras_eeprom_max_record_count(void)
+uint32_t amdgpu_ras_eeprom_max_record_count(void)
{
return RAS_MAX_RECORD_COUNT;
}
int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
struct eeprom_table_record *records, const u32 num);
-inline uint32_t amdgpu_ras_eeprom_max_record_count(void);
+uint32_t amdgpu_ras_eeprom_max_record_count(void);
void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);
ent = debugfs_create_file(name,
S_IFREG | S_IRUGO, root,
ring, &amdgpu_debugfs_ring_fops);
- if (!ent)
- return -ENOMEM;
+ if (IS_ERR(ent))
+ return PTR_ERR(ent);
i_size_write(ent->d_inode, ring->ring_size + 12);
ring->ent = ent;
goto out;
}
+ if (bo->type == ttm_bo_type_device &&
+ new_mem->mem_type == TTM_PL_VRAM &&
+ old_mem->mem_type != TTM_PL_VRAM) {
+ /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
+ * accesses the BO after it's moved.
+ */
+ abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+ }
+
if (adev->mman.buffer_funcs_enabled) {
if (((old_mem->mem_type == TTM_PL_SYSTEM &&
new_mem->mem_type == TTM_PL_VRAM) ||
return r;
}
- if (bo->type == ttm_bo_type_device &&
- new_mem->mem_type == TTM_PL_VRAM &&
- old_mem->mem_type != TTM_PL_VRAM) {
- /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
- * accesses the BO after it's moved.
- */
- abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- }
-
out:
/* update statistics */
atomic64_add(bo->base.size, &adev->num_bytes_moved);
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 145,
.num_sdma_engines = 2,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 145,
.num_sdma_engines = 2,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 145,
.num_sdma_engines = 2,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 92,
.num_sdma_engines = 4,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 92,
.num_sdma_engines = 2,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.mqd_size_aligned = MQD_SIZE_ALIGNED,
.needs_iommu_device = false,
.supports_cwsr = true,
- .needs_pci_atomics = false,
+ .needs_pci_atomics = true,
+ .no_atomic_fw_version = 92,
.num_sdma_engines = 1,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 2,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 92,
.num_sdma_engines = 2,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.needs_iommu_device = false,
.supports_cwsr = true,
.needs_pci_atomics = true,
+ .no_atomic_fw_version = 92,
.num_sdma_engines = 1,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 8,
.mqd_size_aligned = MQD_SIZE_ALIGNED,
.needs_iommu_device = false,
.supports_cwsr = true,
- .needs_pci_atomics = false,
+ .needs_pci_atomics = true,
+ .no_atomic_fw_version = 92,
.num_sdma_engines = 1,
.num_xgmi_sdma_engines = 0,
.num_sdma_queues_per_engine = 2,
if (!kfd)
return NULL;
- /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
- * 32 and 64-bit requests are possible and must be
- * supported.
- */
- kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
- if (device_info->needs_pci_atomics &&
- !kfd->pci_atomic_requested) {
- dev_info(kfd_device,
- "skipped device %x:%x, PCI rejects atomics\n",
- pdev->vendor, pdev->device);
- kfree(kfd);
- return NULL;
- }
-
kfd->kgd = kgd;
kfd->device_info = device_info;
kfd->pdev = pdev;
kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
- kfd->vm_info.first_vmid_kfd + 1;
+ /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
+ * 32 and 64-bit requests are possible and must be
+ * supported.
+ */
+ kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->kgd);
+ if (!kfd->pci_atomic_requested &&
+ kfd->device_info->needs_pci_atomics &&
+ (!kfd->device_info->no_atomic_fw_version ||
+ kfd->mec_fw_version < kfd->device_info->no_atomic_fw_version)) {
+ dev_info(kfd_device,
+ "skipped device %x:%x, PCI rejects atomics %d<%d\n",
+ kfd->pdev->vendor, kfd->pdev->device,
+ kfd->mec_fw_version,
+ kfd->device_info->no_atomic_fw_version);
+ return false;
+ }
+
/* Verify module parameters regarding mapped process number*/
if ((hws_max_conc_proc < 0)
|| (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
void kgd2kfd_device_exit(struct kfd_dev *kfd)
{
if (kfd->init_complete) {
- svm_migrate_fini((struct amdgpu_device *)kfd->kgd);
device_queue_manager_uninit(kfd->dqm);
kfd_interrupt_exit(kfd);
kfd_topology_remove_device(kfd);
return ret;
}
-static int kfd_resume(struct kfd_dev *kfd)
+int kgd2kfd_resume_iommu(struct kfd_dev *kfd)
{
int err = 0;
err = kfd_iommu_resume(kfd);
- if (err) {
+ if (err)
dev_err(kfd_device,
"Failed to resume IOMMU for device %x:%x\n",
kfd->pdev->vendor, kfd->pdev->device);
- return err;
- }
+ return err;
+}
+
+static int kfd_resume(struct kfd_dev *kfd)
+{
+ int err = 0;
err = kfd->dqm->ops.start(kfd->dqm);
if (err) {
pgmap->ops = &svm_migrate_pgmap_ops;
pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev);
pgmap->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
+
+ /* Device manager releases device-specific resources, memory region and
+ * pgmap when driver disconnects from device.
+ */
r = devm_memremap_pages(adev->dev, pgmap);
if (IS_ERR(r)) {
pr_err("failed to register HMM device memory\n");
+
+ /* Disable SVM support capability */
+ pgmap->type = 0;
devm_release_mem_region(adev->dev, res->start,
res->end - res->start + 1);
return PTR_ERR(r);
return 0;
}
-
-void svm_migrate_fini(struct amdgpu_device *adev)
-{
- struct dev_pagemap *pgmap = &adev->kfd.dev->pgmap;
-
- devm_memunmap_pages(adev->dev, pgmap);
- devm_release_mem_region(adev->dev, pgmap->range.start,
- pgmap->range.end - pgmap->range.start + 1);
-}
svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr);
int svm_migrate_init(struct amdgpu_device *adev);
-void svm_migrate_fini(struct amdgpu_device *adev);
#else
{
return 0;
}
-static inline void svm_migrate_fini(struct amdgpu_device *adev)
-{
- /* empty */
-}
#endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */
bool supports_cwsr;
bool needs_iommu_device;
bool needs_pci_atomics;
+ uint32_t no_atomic_fw_version;
unsigned int num_sdma_engines;
unsigned int num_xgmi_sdma_engines;
unsigned int num_sdma_queues_per_engine;
mmu_interval_notifier_remove(&prange->notifier);
}
+static bool
+svm_is_valid_dma_mapping_addr(struct device *dev, dma_addr_t dma_addr)
+{
+ return dma_addr && !dma_mapping_error(dev, dma_addr) &&
+ !(dma_addr & SVM_RANGE_VRAM_DOMAIN);
+}
+
static int
svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange,
unsigned long offset, unsigned long npages,
addr += offset;
for (i = 0; i < npages; i++) {
- if (WARN_ONCE(addr[i] && !dma_mapping_error(dev, addr[i]),
- "leaking dma mapping\n"))
+ if (svm_is_valid_dma_mapping_addr(dev, addr[i]))
dma_unmap_page(dev, addr[i], PAGE_SIZE, dir);
page = hmm_pfn_to_page(hmm_pfns[i]);
return;
for (i = offset; i < offset + npages; i++) {
- if (!dma_addr[i] || dma_mapping_error(dev, dma_addr[i]))
+ if (!svm_is_valid_dma_mapping_addr(dev, dma_addr[i]))
continue;
pr_debug("dma unmapping 0x%llx\n", dma_addr[i] >> PAGE_SHIFT);
dma_unmap_page(dev, dma_addr[i], PAGE_SIZE, dir);
unsigned long last_start;
int last_domain;
int r = 0;
- int64_t i;
+ int64_t i, j;
last_start = prange->start + offset;
for (i = offset; i < offset + npages; i++) {
last_domain = dma_addr[i] & SVM_RANGE_VRAM_DOMAIN;
dma_addr[i] &= ~SVM_RANGE_VRAM_DOMAIN;
- if ((prange->start + i) < prange->last &&
+
+ /* Collect all pages in the same address range and memory domain
+ * that can be mapped with a single call to update mapping.
+ */
+ if (i < offset + npages - 1 &&
last_domain == (dma_addr[i + 1] & SVM_RANGE_VRAM_DOMAIN))
continue;
NULL, dma_addr,
&vm->last_update,
&table_freed);
+
+ for (j = last_start - prange->start; j <= i; j++)
+ dma_addr[j] |= last_domain;
+
if (r) {
pr_debug("failed %d to map to gpu 0x%lx\n", r, prange->start);
goto out;
uint32_t agp_base, agp_bot, agp_top;
PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
+ memset(pa_config, 0, sizeof(*pa_config));
+
logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
return 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- work = kzalloc(sizeof(*work), GFP_ATOMIC);
- if (!work)
- return -ENOMEM;
+ if (dm->vblank_control_workqueue) {
+ work = kzalloc(sizeof(*work), GFP_ATOMIC);
+ if (!work)
+ return -ENOMEM;
- INIT_WORK(&work->work, vblank_control_worker);
- work->dm = dm;
- work->acrtc = acrtc;
- work->enable = enable;
+ INIT_WORK(&work->work, vblank_control_worker);
+ work->dm = dm;
+ work->acrtc = acrtc;
+ work->enable = enable;
- if (acrtc_state->stream) {
- dc_stream_retain(acrtc_state->stream);
- work->stream = acrtc_state->stream;
- }
+ if (acrtc_state->stream) {
+ dc_stream_retain(acrtc_state->stream);
+ work->stream = acrtc_state->stream;
+ }
- queue_work(dm->vblank_control_workqueue, &work->work);
+ queue_work(dm->vblank_control_workqueue, &work->work);
+ }
#endif
return 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
- struct dc_state *dc_state)
+ struct dc_state *dc_state,
+ struct dsc_mst_fairness_vars *vars)
{
struct dc_stream_state *stream = NULL;
struct drm_connector *connector;
struct drm_connector_state *new_con_state;
struct amdgpu_dm_connector *aconnector;
struct dm_connector_state *dm_conn_state;
- int i, j, clock, bpp;
+ int i, j, clock;
int vcpi, pbn_div, pbn = 0;
for_each_new_connector_in_state(state, connector, new_con_state, i) {
}
pbn_div = dm_mst_get_pbn_divider(stream->link);
- bpp = stream->timing.dsc_cfg.bits_per_pixel;
clock = stream->timing.pix_clk_100hz / 10;
- pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
+ /* pbn is calculated by compute_mst_dsc_configs_for_state*/
+ for (j = 0; j < dc_state->stream_count; j++) {
+ if (vars[j].aconnector == aconnector) {
+ pbn = vars[j].pbn;
+ break;
+ }
+ }
+
vcpi = drm_dp_mst_atomic_enable_dsc(state,
aconnector->port,
pbn, pbn_div,
}
}
+static void amdgpu_set_panel_orientation(struct drm_connector *connector)
+{
+ struct drm_encoder *encoder;
+ struct amdgpu_encoder *amdgpu_encoder;
+ const struct drm_display_mode *native_mode;
+
+ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
+ connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
+ return;
+
+ encoder = amdgpu_dm_connector_to_encoder(connector);
+ if (!encoder)
+ return;
+
+ amdgpu_encoder = to_amdgpu_encoder(encoder);
+
+ native_mode = &amdgpu_encoder->native_mode;
+ if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
+ return;
+
+ drm_connector_set_panel_orientation_with_quirk(connector,
+ DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
+ native_mode->hdisplay,
+ native_mode->vdisplay);
+}
+
static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
struct edid *edid)
{
* restored here.
*/
amdgpu_dm_update_freesync_caps(connector, edid);
+
+ amdgpu_set_panel_orientation(connector);
} else {
amdgpu_dm_connector->num_modes = 0;
}
state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
- /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
- * hot-plug, headless s3, dpms
+ /* Stream removed and re-enabled
+ *
+ * Can sometimes overlap with the HPD case,
+ * thus set update_hdcp to false to avoid
+ * setting HDCP multiple times.
+ *
+ * Handles: DESIRED -> DESIRED (Special case)
+ */
+ if (!(old_state->crtc && old_state->crtc->enabled) &&
+ state->crtc && state->crtc->enabled &&
+ connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+ dm_con_state->update_hdcp = false;
+ return true;
+ }
+
+ /* Hot-plug, headless s3, dpms
+ *
+ * Only start HDCP if the display is connected/enabled.
+ * update_hdcp flag will be set to false until the next
+ * HPD comes in.
*
* Handles: DESIRED -> DESIRED (Special case)
*/
* If PSR or idle optimizations are enabled then flush out
* any pending work before hardware programming.
*/
- flush_workqueue(dm->vblank_control_workqueue);
+ if (dm->vblank_control_workqueue)
+ flush_workqueue(dm->vblank_control_workqueue);
#endif
bundle->stream_update.stream = acrtc_state->stream;
/* if there mode set or reset, disable eDP PSR */
if (mode_set_reset_required) {
#if defined(CONFIG_DRM_AMD_DC_DCN)
- flush_workqueue(dm->vblank_control_workqueue);
+ if (dm->vblank_control_workqueue)
+ flush_workqueue(dm->vblank_control_workqueue);
#endif
amdgpu_dm_psr_disable_all(dm);
}
int ret, i;
bool lock_and_validation_needed = false;
struct dm_crtc_state *dm_old_crtc_state;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ struct dsc_mst_fairness_vars vars[MAX_PIPES];
+#endif
trace_amdgpu_dm_atomic_check_begin(state);
goto fail;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
+ if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars))
goto fail;
- ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
+ ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
if (ret)
goto fail;
#endif
goto fail;
status = dc_validate_global_state(dc, dm_state->context, false);
if (status != DC_OK) {
- DC_LOG_WARNING("DC global validation failure: %s (%d)",
+ drm_dbg_atomic(dev,
+ "DC global validation failure: %s (%d)",
dc_status_to_str(status), status);
ret = -EINVAL;
goto fail;
uint32_t num_slices_h;
uint32_t num_slices_v;
uint32_t bpp_overwrite;
-};
-
-struct dsc_mst_fairness_vars {
- int pbn;
- bool dsc_enabled;
- int bpp_x16;
+ struct amdgpu_dm_connector *aconnector;
};
static int kbps_to_peak_pbn(int kbps)
static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
struct dc_state *dc_state,
- struct dc_link *dc_link)
+ struct dc_link *dc_link,
+ struct dsc_mst_fairness_vars *vars)
{
int i;
struct dc_stream_state *stream;
struct dsc_mst_fairness_params params[MAX_PIPES];
- struct dsc_mst_fairness_vars vars[MAX_PIPES];
struct amdgpu_dm_connector *aconnector;
int count = 0;
bool debugfs_overwrite = false;
params[count].timing = &stream->timing;
params[count].sink = stream->sink;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+ params[count].aconnector = aconnector;
params[count].port = aconnector->port;
params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
}
/* Try no compression */
for (i = 0; i < count; i++) {
+ vars[i].aconnector = params[i].aconnector;
vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
vars[i].dsc_enabled = false;
vars[i].bpp_x16 = 0;
}
bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
- struct dc_state *dc_state)
+ struct dc_state *dc_state,
+ struct dsc_mst_fairness_vars *vars)
{
int i, j;
struct dc_stream_state *stream;
return false;
mutex_lock(&aconnector->mst_mgr.lock);
- if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
+ if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars)) {
mutex_unlock(&aconnector->mst_mgr.lock);
return false;
}
dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev);
#if defined(CONFIG_DRM_AMD_DC_DCN)
+
+struct dsc_mst_fairness_vars {
+ int pbn;
+ bool dsc_enabled;
+ int bpp_x16;
+ struct amdgpu_dm_connector *aconnector;
+};
+
bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
- struct dc_state *dc_state);
+ struct dc_state *dc_state,
+ struct dsc_mst_fairness_vars *vars);
#endif
#endif
depth = *pcpu;
put_cpu_ptr(&fpu_recursion_depth);
- ASSERT(depth > 1);
+ ASSERT(depth >= 1);
}
/**
int dc_link_get_backlight_level(const struct dc_link *link)
{
-
struct abm *abm = get_abm_from_stream_res(link);
+ struct panel_cntl *panel_cntl = link->panel_cntl;
+ struct dc *dc = link->ctx->dc;
+ struct dmcu *dmcu = dc->res_pool->dmcu;
+ bool fw_set_brightness = true;
- if (abm == NULL || abm->funcs->get_current_backlight == NULL)
- return DC_ERROR_UNEXPECTED;
+ if (dmcu)
+ fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
- return (int) abm->funcs->get_current_backlight(abm);
+ if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
+ return panel_cntl->funcs->get_current_backlight(panel_cntl);
+ else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
+ return (int) abm->funcs->get_current_backlight(abm);
+ else
+ return DC_ERROR_UNEXPECTED;
}
int dc_link_get_target_backlight_pwm(const struct dc_link *link)
-/* Copyright 2015 Advanced Micro Devices, Inc. */
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ */
#include "dm_services.h"
#include "dc.h"
#include "dc_link_dp.h"
dp_disable_link_phy(link, signal);
/* Abort link training if failure due to sink being unplugged. */
- if (status == LINK_TRAINING_ABORT)
- break;
- else if (do_fallback) {
+ if (status == LINK_TRAINING_ABORT) {
+ enum dc_connection_type type = dc_connection_none;
+
+ dc_link_detect_sink(link, &type);
+ if (type == dc_connection_none)
+ break;
+ } else if (do_fallback) {
decide_fallback_link_setting(*link_setting, ¤t_setting, status);
/* Fail link training if reduced link bandwidth no longer meets
* stream requirements.
#define DC_LOGGER \
engine->ctx->logger
-#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0)
#define IS_DC_I2CAUX_LOGGING_ENABLED() (false)
#define LOG_FLAG_Error_I2cAux LOG_ERROR
#define LOG_FLAG_I2cAux_DceAux LOG_I2C_AUX
#define DEFAULT_AUX_ENGINE_MULT 0
#define DEFAULT_AUX_ENGINE_LENGTH 69
-#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#define DC_TRACE_LEVEL_MESSAGE(...) do { } while (0)
static void release_engine(
struct dce_aux *engine)
static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
{
uint64_t current_backlight;
- uint32_t round_result;
uint32_t bl_period, bl_int_count;
uint32_t bl_pwm, fractional_duty_cycle_en;
uint32_t bl_period_mask, bl_pwm_mask;
current_backlight = div_u64(current_backlight, bl_period);
current_backlight = (current_backlight + 1) >> 1;
- current_backlight = (uint64_t)(current_backlight) * bl_period;
-
- round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
-
- round_result = (round_result >> (bl_int_count-1)) & 1;
-
- current_backlight >>= bl_int_count;
- current_backlight += round_result;
-
return (uint32_t)(current_backlight);
}
#define TABLE_PMSTATUSLOG 3 // Called by Tools for Agm logging
#define TABLE_DPMCLOCKS 4 // Called by Driver; defined here, but not used, for backward compatible
#define TABLE_MOMENTARY_PM 5 // Called by Tools; defined here, but not used, for backward compatible
-#define TABLE_COUNT 6
+#define TABLE_SMU_METRICS 6 // Called by Driver
+#define TABLE_COUNT 7
-#define NUM_DSPCLK_LEVELS 8
-#define NUM_SOCCLK_DPM_LEVELS 8
-#define NUM_DCEFCLK_DPM_LEVELS 4
-#define NUM_FCLK_DPM_LEVELS 4
-#define NUM_MEMCLK_DPM_LEVELS 4
+typedef struct SmuMetricsTable_t {
+ //CPU status
+ uint16_t CoreFrequency[6]; //[MHz]
+ uint32_t CorePower[6]; //[mW]
+ uint16_t CoreTemperature[6]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
+ uint16_t C0Residency[6]; //Percentage
-#define NUMBER_OF_PSTATES 8
-#define NUMBER_OF_CORES 8
+ // GFX status
+ uint16_t GfxclkFrequency; //[MHz]
+ uint16_t GfxTemperature; //[centi-Celsius]
-typedef enum {
- S3_TYPE_ENTRY,
- S5_TYPE_ENTRY,
-} Sleep_Type_e;
+ // SOC IP info
+ uint16_t SocclkFrequency; //[MHz]
+ uint16_t VclkFrequency; //[MHz]
+ uint16_t DclkFrequency; //[MHz]
+ uint16_t MemclkFrequency; //[MHz]
-typedef enum {
- GFX_OFF = 0,
- GFX_ON = 1,
-} GFX_Mode_e;
+ // power, VF info for CPU/GFX telemetry rails, and then socket power total
+ uint32_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_GFX
+ uint32_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_GFX
+ uint32_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_GFX
+ uint32_t CurrentSocketPower; //[mW]
-typedef enum {
- CPU_P0 = 0,
- CPU_P1,
- CPU_P2,
- CPU_P3,
- CPU_P4,
- CPU_P5,
- CPU_P6,
- CPU_P7
-} CPU_PState_e;
+ uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t EdgeTemperature;
+ uint16_t ThrottlerStatus;
+ uint16_t Spare;
-typedef enum {
- CPU_CORE0 = 0,
- CPU_CORE1,
- CPU_CORE2,
- CPU_CORE3,
- CPU_CORE4,
- CPU_CORE5,
- CPU_CORE6,
- CPU_CORE7
-} CORE_ID_e;
+} SmuMetricsTable_t;
-typedef enum {
- DF_DPM0 = 0,
- DF_DPM1,
- DF_DPM2,
- DF_DPM3,
- DF_PState_Count
-} DF_PState_e;
-
-typedef enum {
- GFX_DPM0 = 0,
- GFX_DPM1,
- GFX_DPM2,
- GFX_DPM3,
- GFX_PState_Count
-} GFX_PState_e;
+typedef struct SmuMetrics_t {
+ SmuMetricsTable_t Current;
+ SmuMetricsTable_t Average;
+ uint32_t SampleStartTime;
+ uint32_t SampleStopTime;
+ uint32_t Accnt;
+} SmuMetrics_t;
#endif
__SMU_DUMMY_MAP(SetUclkDpmMode), \
__SMU_DUMMY_MAP(LightSBR), \
__SMU_DUMMY_MAP(GfxDriverResetRecovery), \
- __SMU_DUMMY_MAP(BoardPowerCalibration),
+ __SMU_DUMMY_MAP(BoardPowerCalibration), \
+ __SMU_DUMMY_MAP(RequestGfxclk), \
+ __SMU_DUMMY_MAP(ForceGfxVid), \
+ __SMU_DUMMY_MAP(UnforceGfxVid),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
#define PPSMC_MSG_SetDriverTableVMID 0x34
#define PPSMC_MSG_SetSoftMinCclk 0x35
#define PPSMC_MSG_SetSoftMaxCclk 0x36
-#define PPSMC_Message_Count 0x37
+#define PPSMC_MSG_GetGfxFrequency 0x37
+#define PPSMC_MSG_GetGfxVid 0x38
+#define PPSMC_MSG_ForceGfxFreq 0x39
+#define PPSMC_MSG_UnForceGfxFreq 0x3A
+#define PPSMC_MSG_ForceGfxVid 0x3B
+#define PPSMC_MSG_UnforceGfxVid 0x3C
+#define PPSMC_MSG_GetEnabledSmuFeatures 0x3D
+#define PPSMC_Message_Count 0x3E
#endif
si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
si_thermal_start_thermal_controller(adev);
+ ni_update_current_ps(adev, boot_ps);
+
return 0;
}
*/
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
- (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
+ (adev->asic_type <= CHIP_BEIGE_GOBY))
return smu_disable_all_features_with_exception(smu,
true,
SMU_FEATURE_COUNT);
struct smu_11_0_dpm_context *dpm_context = NULL;
uint32_t gen_speed, lane_width;
- if (amdgpu_ras_intr_triggered())
- return sysfs_emit(buf, "unavailable\n");
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
+ if (amdgpu_ras_intr_triggered()) {
+ size += sysfs_emit_at(buf, size, "unavailable\n");
+ return size;
+ }
dpm_context = smu_dpm->dpm_context;
#undef pr_info
#undef pr_debug
+/* unit: MHz */
+#define CYAN_SKILLFISH_SCLK_MIN 1000
+#define CYAN_SKILLFISH_SCLK_MAX 2000
+#define CYAN_SKILLFISH_SCLK_DEFAULT 1800
+
+/* unit: mV */
+#define CYAN_SKILLFISH_VDDC_MIN 700
+#define CYAN_SKILLFISH_VDDC_MAX 1129
+#define CYAN_SKILLFISH_VDDC_MAGIC 5118 // 0x13fe
+
+static struct gfx_user_settings {
+ uint32_t sclk;
+ uint32_t vddc;
+} cyan_skillfish_user_settings;
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+ FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_SOC_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+
static struct cmn2asic_msg_mapping cyan_skillfish_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverTableDramAddrLow, 0),
MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
+ MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
+ MSG_MAP(RequestGfxclk, PPSMC_MSG_RequestGfxclk, 0),
+ MSG_MAP(ForceGfxVid, PPSMC_MSG_ForceGfxVid, 0),
+ MSG_MAP(UnforceGfxVid, PPSMC_MSG_UnforceGfxVid, 0),
+};
+
+static struct cmn2asic_mapping cyan_skillfish_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP_VALID(SMU_METRICS),
};
+static int cyan_skillfish_tables_init(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = smu_table->tables;
+
+ SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
+ sizeof(SmuMetrics_t),
+ PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM);
+
+ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ if (!smu_table->metrics_table)
+ goto err0_out;
+
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
+ smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
+ if (!smu_table->gpu_metrics_table)
+ goto err1_out;
+
+ smu_table->metrics_time = 0;
+
+ return 0;
+
+err1_out:
+ smu_table->gpu_metrics_table_size = 0;
+ kfree(smu_table->metrics_table);
+err0_out:
+ return -ENOMEM;
+}
+
+static int cyan_skillfish_init_smc_tables(struct smu_context *smu)
+{
+ int ret = 0;
+
+ ret = cyan_skillfish_tables_init(smu);
+ if (ret)
+ return ret;
+
+ return smu_v11_0_init_smc_tables(smu);
+}
+
+static int cyan_skillfish_finit_smc_tables(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ kfree(smu_table->metrics_table);
+ smu_table->metrics_table = NULL;
+
+ kfree(smu_table->gpu_metrics_table);
+ smu_table->gpu_metrics_table = NULL;
+ smu_table->gpu_metrics_table_size = 0;
+
+ smu_table->metrics_time = 0;
+
+ return 0;
+}
+
+static int
+cyan_skillfish_get_smu_metrics_data(struct smu_context *smu,
+ MetricsMember_t member,
+ uint32_t *value)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+ int ret = 0;
+
+ mutex_lock(&smu->metrics_lock);
+
+ ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
+ if (ret) {
+ mutex_unlock(&smu->metrics_lock);
+ return ret;
+ }
+
+ switch (member) {
+ case METRICS_CURR_GFXCLK:
+ *value = metrics->Current.GfxclkFrequency;
+ break;
+ case METRICS_CURR_SOCCLK:
+ *value = metrics->Current.SocclkFrequency;
+ break;
+ case METRICS_CURR_VCLK:
+ *value = metrics->Current.VclkFrequency;
+ break;
+ case METRICS_CURR_DCLK:
+ *value = metrics->Current.DclkFrequency;
+ break;
+ case METRICS_CURR_UCLK:
+ *value = metrics->Current.MemclkFrequency;
+ break;
+ case METRICS_AVERAGE_SOCKETPOWER:
+ *value = (metrics->Current.CurrentSocketPower << 8) /
+ 1000;
+ break;
+ case METRICS_TEMPERATURE_EDGE:
+ *value = metrics->Current.GfxTemperature / 100 *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case METRICS_TEMPERATURE_HOTSPOT:
+ *value = metrics->Current.SocTemperature / 100 *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case METRICS_VOLTAGE_VDDSOC:
+ *value = metrics->Current.Voltage[0];
+ break;
+ case METRICS_VOLTAGE_VDDGFX:
+ *value = metrics->Current.Voltage[1];
+ break;
+ case METRICS_THROTTLER_STATUS:
+ *value = metrics->Current.ThrottlerStatus;
+ break;
+ default:
+ *value = UINT_MAX;
+ break;
+ }
+
+ mutex_unlock(&smu->metrics_lock);
+
+ return ret;
+}
+
+static int cyan_skillfish_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data,
+ uint32_t *size)
+{
+ int ret = 0;
+
+ if (!data || !size)
+ return -EINVAL;
+
+ mutex_lock(&smu->sensor_lock);
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GFX_SCLK:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_CURR_GFXCLK,
+ (uint32_t *)data);
+ *(uint32_t *)data *= 100;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GFX_MCLK:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_CURR_UCLK,
+ (uint32_t *)data);
+ *(uint32_t *)data *= 100;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GPU_POWER:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_AVERAGE_SOCKETPOWER,
+ (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_TEMPERATURE_HOTSPOT,
+ (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_TEMPERATURE_EDGE,
+ (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_VDDNB:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_VOLTAGE_VDDSOC,
+ (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_VDDGFX:
+ ret = cyan_skillfish_get_smu_metrics_data(smu,
+ METRICS_VOLTAGE_VDDGFX,
+ (uint32_t *)data);
+ *size = 4;
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ mutex_unlock(&smu->sensor_lock);
+
+ return ret;
+}
+
+static int cyan_skillfish_get_current_clk_freq(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value)
+{
+ MetricsMember_t member_type;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ member_type = METRICS_CURR_GFXCLK;
+ break;
+ case SMU_FCLK:
+ case SMU_MCLK:
+ member_type = METRICS_CURR_UCLK;
+ break;
+ case SMU_SOCCLK:
+ member_type = METRICS_CURR_SOCCLK;
+ break;
+ case SMU_VCLK:
+ member_type = METRICS_CURR_VCLK;
+ break;
+ case SMU_DCLK:
+ member_type = METRICS_CURR_DCLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return cyan_skillfish_get_smu_metrics_data(smu, member_type, value);
+}
+
+static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ char *buf)
+{
+ int ret = 0, size = 0;
+ uint32_t cur_value = 0;
+
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
+ switch (clk_type) {
+ case SMU_OD_SCLK:
+ ret = cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK, &cur_value);
+ if (ret)
+ return ret;
+ size += sysfs_emit_at(buf, size,"%s:\n", "OD_SCLK");
+ size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
+ break;
+ case SMU_OD_VDDC_CURVE:
+ ret = cyan_skillfish_get_smu_metrics_data(smu, METRICS_VOLTAGE_VDDGFX, &cur_value);
+ if (ret)
+ return ret;
+ size += sysfs_emit_at(buf, size,"%s:\n", "OD_VDDC");
+ size += sysfs_emit_at(buf, size, "0: %umV *\n", cur_value);
+ break;
+ case SMU_OD_RANGE:
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
+ size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
+ CYAN_SKILLFISH_SCLK_MIN, CYAN_SKILLFISH_SCLK_MAX);
+ size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
+ CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
+ break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ case SMU_FCLK:
+ case SMU_MCLK:
+ case SMU_SOCCLK:
+ case SMU_VCLK:
+ case SMU_DCLK:
+ ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ return ret;
+ size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
+ break;
+ default:
+ dev_warn(smu->adev->dev, "Unsupported clock type\n");
+ return ret;
+ }
+
+ return size;
+}
+
+static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+ uint32_t feature_mask[2];
+ uint64_t feature_enabled;
+
+ /* we need to re-init after suspend so return false */
+ if (adev->in_suspend)
+ return false;
+
+ ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+
+ if (ret)
+ return false;
+
+ feature_enabled = (uint64_t)feature_mask[0] |
+ ((uint64_t)feature_mask[1] << 32);
+
+ return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
+static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu,
+ void **table)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct gpu_metrics_v2_2 *gpu_metrics =
+ (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
+ SmuMetrics_t metrics;
+ int i, ret = 0;
+
+ ret = smu_cmn_get_metrics_table(smu, &metrics, true);
+ if (ret)
+ return ret;
+
+ smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
+
+ gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
+ gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
+
+ gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
+ gpu_metrics->average_soc_power = metrics.Current.Power[0];
+ gpu_metrics->average_gfx_power = metrics.Current.Power[1];
+
+ gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
+ gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
+ gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
+ gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
+ gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
+ gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
+
+ gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
+ gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
+ gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
+ gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
+ gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
+ gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
+
+ for (i = 0; i < 6; i++) {
+ gpu_metrics->temperature_core[i] = metrics.Current.CoreTemperature[i];
+ gpu_metrics->average_core_power[i] = metrics.Average.CorePower[i];
+ gpu_metrics->current_coreclk[i] = metrics.Current.CoreFrequency[i];
+ }
+
+ for (i = 0; i < 2; i++) {
+ gpu_metrics->temperature_l3[i] = metrics.Current.L3Temperature[i];
+ gpu_metrics->current_l3clk[i] = metrics.Current.L3Frequency[i];
+ }
+
+ gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
+ gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
+
+ *table = (void *)gpu_metrics;
+
+ return sizeof(struct gpu_metrics_v2_2);
+}
+
+static int cyan_skillfish_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long input[], uint32_t size)
+{
+ int ret = 0;
+ uint32_t vid;
+
+ switch (type) {
+ case PP_OD_EDIT_VDDC_CURVE:
+ if (size != 3 || input[0] != 0) {
+ dev_err(smu->adev->dev, "Invalid parameter!\n");
+ return -EINVAL;
+ }
+
+ if (input[1] <= CYAN_SKILLFISH_SCLK_MIN ||
+ input[1] > CYAN_SKILLFISH_SCLK_MAX) {
+ dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n",
+ CYAN_SKILLFISH_SCLK_MIN, CYAN_SKILLFISH_SCLK_MAX);
+ return -EINVAL;
+ }
+
+ if (input[2] <= CYAN_SKILLFISH_VDDC_MIN ||
+ input[2] > CYAN_SKILLFISH_VDDC_MAX) {
+ dev_err(smu->adev->dev, "Invalid vddc! Valid vddc range: %umV - %umV\n",
+ CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
+ return -EINVAL;
+ }
+
+ cyan_skillfish_user_settings.sclk = input[1];
+ cyan_skillfish_user_settings.vddc = input[2];
+
+ break;
+ case PP_OD_RESTORE_DEFAULT_TABLE:
+ if (size != 0) {
+ dev_err(smu->adev->dev, "Invalid parameter!\n");
+ return -EINVAL;
+ }
+
+ cyan_skillfish_user_settings.sclk = CYAN_SKILLFISH_SCLK_DEFAULT;
+ cyan_skillfish_user_settings.vddc = CYAN_SKILLFISH_VDDC_MAGIC;
+
+ break;
+ case PP_OD_COMMIT_DPM_TABLE:
+ if (size != 0) {
+ dev_err(smu->adev->dev, "Invalid parameter!\n");
+ return -EINVAL;
+ }
+
+ if (cyan_skillfish_user_settings.sclk < CYAN_SKILLFISH_SCLK_MIN ||
+ cyan_skillfish_user_settings.sclk > CYAN_SKILLFISH_SCLK_MAX) {
+ dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n",
+ CYAN_SKILLFISH_SCLK_MIN, CYAN_SKILLFISH_SCLK_MAX);
+ return -EINVAL;
+ }
+
+ if ((cyan_skillfish_user_settings.vddc != CYAN_SKILLFISH_VDDC_MAGIC) &&
+ (cyan_skillfish_user_settings.vddc < CYAN_SKILLFISH_VDDC_MIN ||
+ cyan_skillfish_user_settings.vddc > CYAN_SKILLFISH_VDDC_MAX)) {
+ dev_err(smu->adev->dev, "Invalid vddc! Valid vddc range: %umV - %umV\n",
+ CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
+ return -EINVAL;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestGfxclk,
+ cyan_skillfish_user_settings.sclk, NULL);
+ if (ret) {
+ dev_err(smu->adev->dev, "Set sclk failed!\n");
+ return ret;
+ }
+
+ if (cyan_skillfish_user_settings.vddc == CYAN_SKILLFISH_VDDC_MAGIC) {
+ ret = smu_cmn_send_smc_msg(smu, SMU_MSG_UnforceGfxVid, NULL);
+ if (ret) {
+ dev_err(smu->adev->dev, "Unforce vddc failed!\n");
+ return ret;
+ }
+ } else {
+ /*
+ * PMFW accepts SVI2 VID code, convert voltage to VID:
+ * vid = (uint32_t)((1.55 - voltage) * 160.0 + 0.00001)
+ */
+ vid = (1550 - cyan_skillfish_user_settings.vddc) * 160 / 1000;
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ForceGfxVid, vid, NULL);
+ if (ret) {
+ dev_err(smu->adev->dev, "Force vddc failed!\n");
+ return ret;
+ }
+ }
+
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
.check_fw_version = smu_v11_0_check_fw_version,
.init_power = smu_v11_0_init_power,
.fini_power = smu_v11_0_fini_power,
+ .init_smc_tables = cyan_skillfish_init_smc_tables,
+ .fini_smc_tables = cyan_skillfish_finit_smc_tables,
+ .read_sensor = cyan_skillfish_read_sensor,
+ .print_clk_levels = cyan_skillfish_print_clk_levels,
+ .is_dpm_running = cyan_skillfish_is_dpm_running,
+ .get_gpu_metrics = cyan_skillfish_get_gpu_metrics,
+ .od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table,
.register_irq_handler = smu_v11_0_register_irq_handler,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
{
smu->ppt_funcs = &cyan_skillfish_ppt_funcs;
smu->message_map = cyan_skillfish_message_map;
+ smu->table_map = cyan_skillfish_table_map;
smu->is_apu = true;
}
struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
uint32_t min_value, max_value;
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
case SMU_OD_RANGE:
if (!smu->od_enabled || !od_table || !od_settings)
break;
- size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
{
struct amdgpu_device *adev = smu->adev;
- if (adev->in_runpm)
+ /*
+ * This aims the case below:
+ * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
+ *
+ * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
+ * make that possible, PMFW needs to acknowledge the dstate transition
+ * process for both gfx(function 0) and audio(function 1) function of
+ * the ASIC.
+ *
+ * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
+ * device representing the audio function of the ASIC. And that means
+ * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
+ * possible runpm suspend kicked on the ASIC. However without the dstate
+ * transition notification from audio function, pmfw cannot handle the
+ * BACO in/exit correctly. And that will cause driver hang on runpm
+ * resuming.
+ *
+ * To address this, we revert to legacy message way(driver masters the
+ * timing for BACO in/exit) on sound driver missing.
+ */
+ if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
else
return smu_v11_0_baco_enter(smu);
{
struct amdgpu_device *adev = smu->adev;
- if (adev->in_runpm) {
+ if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
/* Wait for PMFW handling for the Dstate change */
msleep(10);
return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
uint32_t min_value, max_value;
uint32_t smu_version;
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
if (!smu->od_enabled || !od_table || !od_settings)
break;
- size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
{
struct amdgpu_device *adev = smu->adev;
- if (adev->in_runpm)
+ if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
else
return smu_v11_0_baco_enter(smu);
{
struct amdgpu_device *adev = smu->adev;
- if (adev->in_runpm) {
+ if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
/* Wait for PMFW handling for the Dstate change */
msleep(10);
return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
if (ret)
return ret;
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
switch (clk_type) {
case SMU_OD_SCLK:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
- size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
break;
case SMU_OD_CCLK:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
- size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
+ size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
break;
case SMU_OD_RANGE:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
- size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
if (ret)
return ret;
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
switch (clk_type) {
case SMU_OD_SCLK:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
- size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
break;
case SMU_OD_CCLK:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
- size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
+ size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
break;
case SMU_OD_RANGE:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
- size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
if (ret)
return ret;
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
switch (clk_type) {
case SMU_OD_RANGE:
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
uint32_t freq_values[3] = {0};
uint32_t min_clk, max_clk;
- if (amdgpu_ras_intr_triggered())
- return sysfs_emit(buf, "unavailable\n");
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
+ if (amdgpu_ras_intr_triggered()) {
+ size += sysfs_emit_at(buf, size, "unavailable\n");
+ return size;
+ }
dpm_context = smu_dpm->dpm_context;
switch (type) {
case SMU_OD_SCLK:
- size = sysfs_emit(buf, "%s:\n", "GFXCLK");
+ size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK");
fallthrough;
case SMU_SCLK:
ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
break;
case SMU_OD_MCLK:
- size = sysfs_emit(buf, "%s:\n", "MCLK");
+ size += sysfs_emit_at(buf, size, "%s:\n", "MCLK");
fallthrough;
case SMU_MCLK:
ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+ smu_cmn_get_sysfs_buf(&buf, &size);
+
switch (clk_type) {
case SMU_OD_SCLK:
- size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
break;
case SMU_OD_RANGE:
- size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
break;
return ret;
}
+
+bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
+{
+ struct pci_dev *p = NULL;
+ bool snd_driver_loaded;
+
+ /*
+ * If the ASIC comes with no audio function, we always assume
+ * it is "enabled".
+ */
+ p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
+ adev->pdev->bus->number, 1);
+ if (!p)
+ return true;
+
+ snd_driver_loaded = pci_is_enabled(p) ? true : false;
+
+ pci_dev_put(p);
+
+ return snd_driver_loaded;
+}
int smu_cmn_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state);
+/*
+ * Helper function to make sysfs_emit_at() happy. Align buf to
+ * the current page boundary and record the offset.
+ */
+static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset)
+{
+ if (!*buf || !offset)
+ return;
+
+ *offset = offset_in_page(*buf);
+ *buf -= *offset;
+}
+
+bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev);
+
#endif
#endif
if (switch_mmu_context) {
struct etnaviv_iommu_context *old_context = gpu->mmu_context;
- etnaviv_iommu_context_get(mmu_context);
- gpu->mmu_context = mmu_context;
+ gpu->mmu_context = etnaviv_iommu_context_get(mmu_context);
etnaviv_iommu_context_put(old_context);
}
list_del(&mapping->obj_node);
}
- etnaviv_iommu_context_get(mmu_context);
- mapping->context = mmu_context;
+ mapping->context = etnaviv_iommu_context_get(mmu_context);
mapping->use = 1;
ret = etnaviv_iommu_map_gem(mmu_context, etnaviv_obj,
goto err_submit_objects;
submit->ctx = file->driver_priv;
- etnaviv_iommu_context_get(submit->ctx->mmu);
- submit->mmu_context = submit->ctx->mmu;
+ submit->mmu_context = etnaviv_iommu_context_get(submit->ctx->mmu);
submit->exec_state = args->exec_state;
submit->flags = args->flags;
/* We rely on the GPU running, so program the clock */
etnaviv_gpu_update_clock(gpu);
+ gpu->fe_running = false;
+ gpu->exec_state = -1;
+ if (gpu->mmu_context)
+ etnaviv_iommu_context_put(gpu->mmu_context);
+ gpu->mmu_context = NULL;
+
return 0;
}
VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
}
+
+ gpu->fe_running = true;
}
-static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu)
+static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
+ struct etnaviv_iommu_context *context)
{
- u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
- &gpu->mmu_context->cmdbuf_mapping);
u16 prefetch;
+ u32 address;
/* setup the MMU */
- etnaviv_iommu_restore(gpu, gpu->mmu_context);
+ etnaviv_iommu_restore(gpu, context);
/* Start command processor */
prefetch = etnaviv_buffer_init(gpu);
+ address = etnaviv_cmdbuf_get_va(&gpu->buffer,
+ &gpu->mmu_context->cmdbuf_mapping);
etnaviv_gpu_start_fe(gpu, address, prefetch);
}
/* Now program the hardware */
mutex_lock(&gpu->lock);
etnaviv_gpu_hw_init(gpu);
- gpu->exec_state = -1;
mutex_unlock(&gpu->lock);
pm_runtime_mark_last_busy(gpu->dev);
spin_unlock(&gpu->event_spinlock);
etnaviv_gpu_hw_init(gpu);
- gpu->exec_state = -1;
- gpu->mmu_context = NULL;
mutex_unlock(&gpu->lock);
pm_runtime_mark_last_busy(gpu->dev);
goto out_unlock;
}
- if (!gpu->mmu_context) {
- etnaviv_iommu_context_get(submit->mmu_context);
- gpu->mmu_context = submit->mmu_context;
- etnaviv_gpu_start_fe_idleloop(gpu);
- } else {
- etnaviv_iommu_context_get(gpu->mmu_context);
- submit->prev_mmu_context = gpu->mmu_context;
- }
+ if (!gpu->fe_running)
+ etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
+
+ if (submit->prev_mmu_context)
+ etnaviv_iommu_context_put(submit->prev_mmu_context);
+ submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
if (submit->nr_pmrs) {
gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
{
- if (gpu->initialized && gpu->mmu_context) {
+ if (gpu->initialized && gpu->fe_running) {
/* Replace the last WAIT with END */
mutex_lock(&gpu->lock);
etnaviv_buffer_end(gpu);
*/
etnaviv_gpu_wait_idle(gpu, 100);
- etnaviv_iommu_context_put(gpu->mmu_context);
- gpu->mmu_context = NULL;
+ gpu->fe_running = false;
}
gpu->exec_state = -1;
etnaviv_gpu_hw_suspend(gpu);
#endif
+ if (gpu->mmu_context)
+ etnaviv_iommu_context_put(gpu->mmu_context);
+
if (gpu->initialized) {
etnaviv_cmdbuf_free(&gpu->buffer);
etnaviv_iommu_global_fini(gpu);
struct workqueue_struct *wq;
struct drm_gpu_scheduler sched;
bool initialized;
+ bool fe_running;
/* 'ring'-buffer: */
struct etnaviv_cmdbuf buffer;
struct etnaviv_iommuv1_context *v1_context = to_v1_context(context);
u32 pgtable;
+ if (gpu->mmu_context)
+ etnaviv_iommu_context_put(gpu->mmu_context);
+ gpu->mmu_context = etnaviv_iommu_context_get(context);
+
/* set base addresses */
gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base);
gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base);
if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE)
return;
+ if (gpu->mmu_context)
+ etnaviv_iommu_context_put(gpu->mmu_context);
+ gpu->mmu_context = etnaviv_iommu_context_get(context);
+
prefetch = etnaviv_buffer_config_mmuv2(gpu,
(u32)v2_context->mtlb_dma,
(u32)context->global->bad_page_dma);
if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE)
return;
+ if (gpu->mmu_context)
+ etnaviv_iommu_context_put(gpu->mmu_context);
+ gpu->mmu_context = etnaviv_iommu_context_get(context);
+
gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW,
lower_32_bits(context->global->v2.pta_dma));
gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH,
*/
list_for_each_entry_safe(m, n, &list, scan_node) {
etnaviv_iommu_remove_mapping(context, m);
+ etnaviv_iommu_context_put(m->context);
m->context = NULL;
list_del_init(&m->mmu_node);
list_del_init(&m->scan_node);
struct etnaviv_iommu_context *
etnaviv_iommu_context_init(struct etnaviv_iommu_global *global,
struct etnaviv_cmdbuf_suballoc *suballoc);
-static inline void etnaviv_iommu_context_get(struct etnaviv_iommu_context *ctx)
+static inline struct etnaviv_iommu_context *
+etnaviv_iommu_context_get(struct etnaviv_iommu_context *ctx)
{
kref_get(&ctx->refcount);
+ return ctx;
}
void etnaviv_iommu_context_put(struct etnaviv_iommu_context *ctx);
void etnaviv_iommu_restore(struct etnaviv_gpu *gpu,
subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
# clang warnings
subdir-ccflags-y += $(call cc-disable-warning, sign-compare)
-subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized)
subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)
subdir-ccflags-y += $(call cc-disable-warning, frame-address)
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
struct intel_sa_info {
u16 displayrtids;
- u8 deburst, deprogbwlimit;
+ u8 deburst, deprogbwlimit, derating;
};
static const struct intel_sa_info icl_sa_info = {
.deburst = 8,
.deprogbwlimit = 25, /* GB/s */
.displayrtids = 128,
+ .derating = 10,
};
static const struct intel_sa_info tgl_sa_info = {
.deburst = 16,
.deprogbwlimit = 34, /* GB/s */
.displayrtids = 256,
+ .derating = 10,
};
static const struct intel_sa_info rkl_sa_info = {
.deburst = 16,
.deprogbwlimit = 20, /* GB/s */
.displayrtids = 128,
+ .derating = 10,
};
static const struct intel_sa_info adls_sa_info = {
.deburst = 16,
.deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
+ .derating = 10,
+};
+
+static const struct intel_sa_info adlp_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 38, /* GB/s */
+ .displayrtids = 256,
+ .derating = 20,
};
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
bi->deratedbw[j] = min(maxdebw,
- bw * 9 / 10); /* 90% */
+ bw * (100 - sa->derating) / 100);
drm_dbg_kms(&dev_priv->drm,
"BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
if (IS_DG2(dev_priv))
dg2_get_bw_info(dev_priv);
- else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv))
+ icl_get_bw_info(dev_priv, &adlp_sa_info);
+ else if (IS_ALDERLAKE_S(dev_priv))
icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
*/
void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
{
+ int id;
+
if (!HAS_DMC(dev_priv))
return;
intel_dmc_ucode_suspend(dev_priv);
drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
+ for (id = 0; id < DMC_FW_MAX; id++)
+ kfree(dev_priv->dmc.dmc_info[id].payload);
}
*/
if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
- sizeof(intel_dp->edp_dpcd))
+ sizeof(intel_dp->edp_dpcd)) {
drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
(int)sizeof(intel_dp->edp_dpcd),
intel_dp->edp_dpcd);
+ intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
+ }
+
/*
* This has to be called after intel_dp->edp_dpcd is filled, PSR checks
* for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
}
if (ret)
- intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
+ ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
if (intel_dp->set_idle_link_train)
intel_dp->set_idle_link_train(intel_dp, crtc_state);
trace_i915_context_free(ctx);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ if (ctx->syncobj)
+ drm_syncobj_put(ctx->syncobj);
+
mutex_destroy(&ctx->engines_mutex);
mutex_destroy(&ctx->lut_mutex);
if (vm)
i915_vm_close(vm);
- if (ctx->syncobj)
- drm_syncobj_put(ctx->syncobj);
-
ctx->file_priv = ERR_PTR(-EBADF);
/*
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
- if (likely(obj)) {
- /* This releases all gem object bindings to the backend. */
+ if (likely(obj))
i915_ttm_free_cached_io_st(obj);
- __i915_gem_free_object(obj);
- }
}
static struct intel_memory_region *
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ /* This releases all gem object bindings to the backend. */
+ __i915_gem_free_object(obj);
+
i915_gem_object_release_memory_region(obj);
mutex_destroy(&obj->ttm.get_io_page.lock);
+
if (obj->ttm.created)
call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
}
err = PTR_ERR(import);
goto out_dmabuf;
}
+ import_obj = to_intel_bo(import);
if (import != &obj->base) {
pr_err("i915_gem_prime_import created a new object!\n");
err = -EINVAL;
goto out_import;
}
- import_obj = to_intel_bo(import);
i915_gem_object_lock(import_obj, NULL);
err = __i915_gem_object_get_pages(import_obj);
pr_err("i915_gem_prime_import failed with the wrong err=%ld\n",
PTR_ERR(import));
err = PTR_ERR(import);
+ } else {
+ err = 0;
}
dma_buf_put(dmabuf);
err = PTR_ERR(import);
goto out_dmabuf;
}
+ import_obj = to_intel_bo(import);
if (import == &obj->base) {
pr_err("i915_gem_prime_import reused gem object!\n");
goto out_import;
}
- import_obj = to_intel_bo(import);
-
i915_gem_object_lock(import_obj, NULL);
err = __i915_gem_object_get_pages(import_obj);
if (err) {
return I915_MMAP_TYPE_GTT;
}
+static struct drm_i915_gem_object *
+create_sys_or_internal(struct drm_i915_private *i915,
+ unsigned long size)
+{
+ if (HAS_LMEM(i915)) {
+ struct intel_memory_region *sys_region =
+ i915->mm.regions[INTEL_REGION_SMEM];
+
+ return __i915_gem_object_create_user(i915, size, &sys_region, 1);
+ }
+
+ return i915_gem_object_create_internal(i915, size);
+}
+
static bool assert_mmap_offset(struct drm_i915_private *i915,
unsigned long size,
int expected)
u64 offset;
int ret;
- obj = i915_gem_object_create_internal(i915, size);
+ obj = create_sys_or_internal(i915, size);
if (IS_ERR(obj))
return expected && expected == PTR_ERR(obj);
struct drm_mm_node *hole, *next;
int loop, err = 0;
u64 offset;
+ int enospc = HAS_LMEM(i915) ? -ENXIO : -ENOSPC;
/* Disable background reaper */
disable_retire_worker(i915);
}
/* Too large */
- if (!assert_mmap_offset(i915, 2 * PAGE_SIZE, -ENOSPC)) {
+ if (!assert_mmap_offset(i915, 2 * PAGE_SIZE, enospc)) {
pr_err("Unexpectedly succeeded in inserting too large object into single page hole\n");
err = -EINVAL;
goto out;
}
/* Fill the hole, further allocation attempts should then fail */
- obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ obj = create_sys_or_internal(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
pr_err("Unable to create object for reclaimed hole\n");
goto err_obj;
}
- if (!assert_mmap_offset(i915, PAGE_SIZE, -ENOSPC)) {
+ if (!assert_mmap_offset(i915, PAGE_SIZE, enospc)) {
pr_err("Unexpectedly succeeded in inserting object into no holes!\n");
err = -EINVAL;
goto err_obj;
static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
{
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
bool no_map;
- if (HAS_LMEM(i915))
+ if (obj->ops->mmap_offset)
return type == I915_MMAP_TYPE_FIXED;
else if (type == I915_MMAP_TYPE_FIXED)
return false;
u32 intel_rps_read_punit_req(struct intel_rps *rps)
{
struct intel_uncore *uncore = rps_to_uncore(rps);
+ struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm;
+ intel_wakeref_t wakeref;
+ u32 freq = 0;
- return intel_uncore_read(uncore, GEN6_RPNSWREQ);
+ with_intel_runtime_pm_if_in_use(rpm, wakeref)
+ freq = intel_uncore_read(uncore, GEN6_RPNSWREQ);
+
+ return freq;
}
static u32 intel_rps_get_req(u32 pureq)
__uc_free_load_err_log(uc);
}
-static inline bool guc_communication_enabled(struct intel_guc *guc)
-{
- return intel_guc_ct_enabled(&guc->ct);
-}
-
/*
* Events triggered while CT buffers are disabled are logged in the SCRATCH_15
* register using the same bits used in the CT message payload. Since our
static void guc_handle_mmio_msg(struct intel_guc *guc)
{
/* we need communication to be enabled to reply to GuC */
- GEM_BUG_ON(!guc_communication_enabled(guc));
+ GEM_BUG_ON(!intel_guc_ct_enabled(&guc->ct));
spin_lock_irq(&guc->irq_lock);
if (guc->mmio_msg) {
struct drm_i915_private *i915 = gt->i915;
int ret;
- GEM_BUG_ON(guc_communication_enabled(guc));
+ GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct));
ret = i915_inject_probe_error(i915, -ENXIO);
if (ret)
return 0;
/* Make sure we enable communication if and only if it's disabled */
- GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
+ GEM_BUG_ON(enable_communication == intel_guc_ct_enabled(&guc->ct));
if (enable_communication)
guc_enable_communication(guc);
args->v0.count = 0;
args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
- args->v0.pwrsrc = -ENOSYS;
+ args->v0.pwrsrc = -ENODEV;
args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;
}
#endif
if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
- rdev->agp = radeon_agp_head_init(rdev->ddev);
+ rdev->agp = radeon_agp_head_init(dev);
if (rdev->agp) {
rdev->agp->agp_mtrr = arch_phys_wc_add(
rdev->agp->agp_info.aper_base,
return ret;
}
-static int cdn_dp_resume(struct device *dev)
+static __maybe_unused int cdn_dp_resume(struct device *dev)
{
struct cdn_dp_device *dp = dev_get_drvdata(dev);
else
gfp_flags |= GFP_HIGHUSER;
- for (order = min(MAX_ORDER - 1UL, __fls(num_pages)); num_pages;
+ for (order = min_t(unsigned int, MAX_ORDER - 1, __fls(num_pages));
+ num_pages;
order = min_t(unsigned int, order, __fls(num_pages))) {
bool apply_caching = false;
struct ttm_pool_type *pt;
struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
bool connected = false;
- WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
-
if (vc4_hdmi->hpd_gpio &&
gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
connected = true;
}
}
- pm_runtime_put(&vc4_hdmi->pdev->dev);
return connector_status_connected;
}
cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
- pm_runtime_put(&vc4_hdmi->pdev->dev);
return connector_status_disconnected;
}
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
struct drm_connector *connector = &vc4_hdmi->connector;
struct drm_connector_state *cstate = connector->state;
- struct drm_crtc *crtc = cstate->crtc;
+ struct drm_crtc *crtc = encoder->crtc;
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
union hdmi_infoframe frame;
int ret;
static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
{
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
- struct drm_connector *connector = &vc4_hdmi->connector;
- struct drm_connector_state *cstate = connector->state;
- struct drm_crtc *crtc = cstate->crtc;
- struct drm_display_mode *mode = &crtc->state->adjusted_mode;
if (!vc4_hdmi_supports_scrambling(encoder, mode))
return;
static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
- struct drm_connector *connector = &vc4_hdmi->connector;
- struct drm_connector_state *cstate = connector->state;
+ struct drm_crtc *crtc = encoder->crtc;
/*
- * At boot, connector->state will be NULL. Since we don't know the
+ * At boot, encoder->crtc will be NULL. Since we don't know the
* state of the scrambler and in order to avoid any
* inconsistency, let's disable it all the time.
*/
- if (cstate && !vc4_hdmi_supports_scrambling(encoder, &cstate->crtc->mode))
+ if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
return;
- if (cstate && !vc4_hdmi_mode_needs_scrambling(&cstate->crtc->mode))
+ if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
return;
if (delayed_work_pending(&vc4_hdmi->scrambling_work))
vc4_hdmi->variant->phy_disable(vc4_hdmi);
clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
vc4_hdmi_encoder_get_connector_state(encoder, state);
struct vc4_hdmi_connector_state *vc4_conn_state =
conn_state_to_vc4_hdmi_conn_state(conn_state);
- struct drm_crtc_state *crtc_state =
- drm_atomic_get_new_crtc_state(state, conn_state->crtc);
- struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long bvb_rate, pixel_rate, hsm_rate;
int ret;
return;
}
+ ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
+ if (ret) {
+ DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
+ clk_disable_unprepare(vc4_hdmi->pixel_clock);
+ return;
+ }
+
vc4_hdmi_cec_update_clk_div(vc4_hdmi);
if (pixel_rate > 297000000)
ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
if (ret) {
DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
return;
}
ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
if (ret) {
DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
return;
}
static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
- struct drm_connector_state *conn_state =
- vc4_hdmi_encoder_get_connector_state(encoder, state);
- struct drm_crtc_state *crtc_state =
- drm_atomic_get_new_crtc_state(state, conn_state->crtc);
- struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
- struct drm_connector_state *conn_state =
- vc4_hdmi_encoder_get_connector_state(encoder, state);
- struct drm_crtc_state *crtc_state =
- drm_atomic_get_new_crtc_state(state, conn_state->crtc);
- struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
{
- struct drm_connector *connector = &vc4_hdmi->connector;
- struct drm_crtc *crtc = connector->state->crtc;
+ struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
+ struct drm_crtc *crtc = encoder->crtc;
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
u32 n, cts;
u64 tmp;
static int vc4_hdmi_audio_startup(struct device *dev, void *data)
{
struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
- struct drm_connector *connector = &vc4_hdmi->connector;
+ struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
/*
* If the HDMI encoder hasn't probed, or the encoder is
* currently in DVI mode, treat the codec dai as missing.
*/
- if (!connector->state || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
+ if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
VC4_HDMI_RAM_PACKET_ENABLE))
return -ENODEV;
return 0;
}
-#ifdef CONFIG_PM
-static int vc4_hdmi_runtime_suspend(struct device *dev)
-{
- struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
-
- clk_disable_unprepare(vc4_hdmi->hsm_clock);
-
- return 0;
-}
-
-static int vc4_hdmi_runtime_resume(struct device *dev)
-{
- struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
- int ret;
-
- ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
- if (ret)
- return ret;
-
- return 0;
-}
-#endif
-
static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
{
const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
{}
};
-static const struct dev_pm_ops vc4_hdmi_pm_ops = {
- SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
- vc4_hdmi_runtime_resume,
- NULL)
-};
-
struct platform_driver vc4_hdmi_driver = {
.probe = vc4_hdmi_dev_probe,
.remove = vc4_hdmi_dev_remove,
.driver = {
.name = "vc4_hdmi",
.of_match_table = vc4_hdmi_dt_match,
- .pm = &vc4_hdmi_pm_ops,
},
};
mutex_unlock(&ring_info->ring_buffer_mutex);
kfree(ring_info->pkt_buffer);
+ ring_info->pkt_buffer = NULL;
ring_info->pkt_buffer_size = 0;
}
*/
#include <linux/platform_device.h>
+#include <linux/slab.h>
#include "coresight-config.h"
#include "coresight-etm-perf.h"
config GOLDFISH_PIC
bool "Goldfish programmable interrupt controller"
depends on MIPS && (GOLDFISH || COMPILE_TEST)
+ select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
help
Say yes here to enable Goldfish interrupt controller driver used
ARMADA_370_XP_SW_TRIG_INT_OFFS);
}
-static void armada_370_xp_ipi_eoi(struct irq_data *d)
+static void armada_370_xp_ipi_ack(struct irq_data *d)
{
writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
}
static struct irq_chip ipi_irqchip = {
.name = "IPI",
+ .irq_ack = armada_370_xp_ipi_ack,
.irq_mask = armada_370_xp_ipi_mask,
.irq_unmask = armada_370_xp_ipi_unmask,
- .irq_eoi = armada_370_xp_ipi_eoi,
.ipi_send_mask = armada_370_xp_ipi_send_mask,
};
if (err) {
if (i > 0)
- its_vpe_irq_domain_free(domain, virq, i - 1);
+ its_vpe_irq_domain_free(domain, virq, i);
its_lpi_free(bitmap, base, nr_ids);
its_free_prop_table(vprop_page);
#endif
+static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
+
/*
* The GIC mapping of CPU interfaces does not necessarily match
* the logical CPU numbering. Let's use a mapping as returned
#endif
#ifdef CONFIG_SMP
+static void rmw_writeb(u8 bval, void __iomem *addr)
+{
+ static DEFINE_RAW_SPINLOCK(rmw_lock);
+ unsigned long offset = (unsigned long)addr & 3UL;
+ unsigned long shift = offset * 8;
+ unsigned long flags;
+ u32 val;
+
+ raw_spin_lock_irqsave(&rmw_lock, flags);
+
+ addr -= offset;
+ val = readl_relaxed(addr);
+ val &= ~GENMASK(shift + 7, shift);
+ val |= bval << shift;
+ writel_relaxed(val, addr);
+
+ raw_spin_unlock_irqrestore(&rmw_lock, flags);
+}
+
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
bool force)
{
if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
return -EINVAL;
- writeb_relaxed(gic_cpu_map[cpu], reg);
+ if (static_branch_unlikely(&needs_rmw_access))
+ rmw_writeb(gic_cpu_map[cpu], reg);
+ else
+ writeb_relaxed(gic_cpu_map[cpu], reg);
irq_data_update_effective_affinity(d, cpumask_of(cpu));
return IRQ_SET_MASK_OK_DONE;
return true;
}
+static bool gic_enable_rmw_access(void *data)
+{
+ /*
+ * The EMEV2 class of machines has a broken interconnect, and
+ * locks up on accesses that are less than 32bit. So far, only
+ * the affinity setting requires it.
+ */
+ if (of_machine_is_compatible("renesas,emev2")) {
+ static_branch_enable(&needs_rmw_access);
+ return true;
+ }
+
+ return false;
+}
+
+static const struct gic_quirk gic_quirks[] = {
+ {
+ .desc = "broken byte access",
+ .compatible = "arm,pl390",
+ .init = gic_enable_rmw_access,
+ },
+ { },
+};
+
static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
{
if (!gic || !node)
if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
gic->percpu_offset = 0;
+ gic_enable_of_quirks(node, gic_quirks, gic);
+
return 0;
error:
/* The maximum IRQ pin number of mbigen chip(start from 0) */
#define MAXIMUM_IRQ_PIN_NUM 1407
-/**
+/*
* In mbigen vector register
* bit[21:12]: event id value
* bit[11:0]: device id
/* offset of vector register in mbigen node */
#define REG_MBIGEN_VEC_OFFSET 0x200
-/**
+/*
* offset of clear register in mbigen node
* This register is used to clear the status
* of interrupt
*/
#define REG_MBIGEN_CLEAR_OFFSET 0xa000
-/**
+/*
* offset of interrupt type register
* This register is used to configure interrupt
* trigger type
goto out_put_node;
}
- priv->chip.name = "rza1-irqc",
- priv->chip.irq_mask = irq_chip_mask_parent,
- priv->chip.irq_unmask = irq_chip_unmask_parent,
- priv->chip.irq_eoi = rza1_irqc_eoi,
- priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy,
- priv->chip.irq_set_type = rza1_irqc_set_type,
+ priv->chip.name = "rza1-irqc";
+ priv->chip.irq_mask = irq_chip_mask_parent;
+ priv->chip.irq_unmask = irq_chip_unmask_parent;
+ priv->chip.irq_eoi = rza1_irqc_eoi;
+ priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy;
+ priv->chip.irq_set_type = rza1_irqc_set_type;
priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
fail_db_node:
of_node_put(smu->db_node);
fail_bootmem:
- memblock_free(__pa(smu), sizeof(struct smu_device));
+ memblock_free_ptr(smu, sizeof(struct smu_device));
smu = NULL;
fail_np:
of_node_put(np);
bus_nr = ida_simple_get(&mcb_ida, 0, 0, GFP_KERNEL);
if (bus_nr < 0) {
- rc = bus_nr;
- goto err_free;
+ kfree(bus);
+ return ERR_PTR(bus_nr);
}
bus->bus_nr = bus_nr;
dev_set_name(&bus->dev, "mcb:%d", bus_nr);
rc = device_add(&bus->dev);
if (rc)
- goto err_free;
+ goto err_put;
return bus;
-err_free:
- put_device(carrier);
- kfree(bus);
+
+err_put:
+ put_device(&bus->dev);
return ERR_PTR(rc);
}
EXPORT_SYMBOL_NS_GPL(mcb_alloc_bus, MCB);
disk->flags |= GENHD_FL_EXT_DEVT;
disk->events |= DISK_EVENT_MEDIA_CHANGE;
mddev->gendisk = disk;
- /* As soon as we call add_disk(), another thread could get
- * through to md_open, so make sure it doesn't get too far
- */
- mutex_lock(&mddev->open_mutex);
add_disk(disk);
error = kobject_add(&mddev->kobj, &disk_to_dev(disk)->kobj, "%s", "md");
if (mddev->kobj.sd &&
sysfs_create_group(&mddev->kobj, &md_bitmap_group))
pr_debug("pointless warning\n");
- mutex_unlock(&mddev->open_mutex);
abort:
mutex_unlock(&disks_mutex);
if (!error && mddev->kobj.sd) {
struct device *tty_dev;
tty_port_init(&vk->tty[i].port);
- tty_dev = tty_port_register_device(&vk->tty[i].port, tty_drv,
- i, dev);
+ tty_dev = tty_port_register_device_attr(&vk->tty[i].port,
+ tty_drv, i, dev, vk,
+ NULL);
if (IS_ERR(tty_dev)) {
err = PTR_ERR(tty_dev);
goto unwind;
}
- dev_set_drvdata(tty_dev, vk);
vk->tty[i].is_opened = false;
}
/* check for 64-bit DMA address supported (DAC) */
/* check for 32-bit DMA address supported (SAC) */
- if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)) ||
+ if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)) &&
dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32))) {
dev_err(&pci_dev->dev,
"err: neither DMA32 nor DMA64 supported\n");
static void cs_handle_tdr(struct hl_device *hdev, struct hl_cs *cs)
{
bool next_entry_found = false;
- struct hl_cs *next;
+ struct hl_cs *next, *first_cs;
if (!cs_needs_timeout(cs))
return;
/* We need to handle tdr only once for the complete staged submission.
* Hence, we choose the CS that reaches this function first which is
* the CS marked as 'staged_last'.
+ * In case single staged cs was submitted which has both first and last
+ * indications, then "cs_find_first" below will return NULL, since we
+ * removed the cs node from the list before getting here,
+ * in such cases just continue with the cs to cancel it's TDR work.
*/
- if (cs->staged_cs && cs->staged_last)
- cs = hl_staged_cs_find_first(hdev, cs->staged_sequence);
+ if (cs->staged_cs && cs->staged_last) {
+ first_cs = hl_staged_cs_find_first(hdev, cs->staged_sequence);
+ if (first_cs)
+ cs = first_cs;
+ }
spin_unlock(&hdev->cs_mirror_lock);
if (rc)
goto free_cs_object;
+ /* If this is a staged submission we must return the staged sequence
+ * rather than the internal CS sequence
+ */
+ if (cs->staged_cs)
+ *cs_seq = cs->staged_sequence;
+
/* Validate ALL the CS chunks before submitting the CS */
for (i = 0 ; i < num_chunks ; i++) {
struct hl_cs_chunk *chunk = &cs_chunk_array[i];
goto free_cs_chunk_array;
}
+ if (!hdev->nic_ports_mask) {
+ atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+ atomic64_inc(&cntr->validation_drop_cnt);
+ dev_err(hdev->dev,
+ "Collective operations not supported when NIC ports are disabled");
+ rc = -EINVAL;
+ goto free_cs_chunk_array;
+ }
+
collective_engine_id = chunk->collective_engine_id;
}
spin_unlock(&ctx->sig_mgr.lock);
if (!handle_found) {
- dev_err(hdev->dev, "Cannot find encapsulated signals handle for seq 0x%llx\n",
+ /* treat as signal CS already finished */
+ dev_dbg(hdev->dev, "Cannot find encapsulated signals handle for seq 0x%llx\n",
signal_seq);
- rc = -EINVAL;
+ rc = 0;
goto free_cs_chunk_array;
}
* completed after the poll function.
*/
if (!mcs_data.completion_bitmap) {
- dev_err(hdev->dev, "Multi-CS got completion on wait but no CS completed\n");
+ dev_warn_ratelimited(hdev->dev,
+ "Multi-CS got completion on wait but no CS completed\n");
rc = -EFAULT;
}
}
else
interrupt = &hdev->user_interrupt[interrupt_offset];
+ /* Add pending user interrupt to relevant list for the interrupt
+ * handler to monitor
+ */
+ spin_lock_irqsave(&interrupt->wait_list_lock, flags);
+ list_add_tail(&pend->wait_list_node, &interrupt->wait_list_head);
+ spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+
+ /* We check for completion value as interrupt could have been received
+ * before we added the node to the wait list
+ */
if (copy_from_user(&completion_value, u64_to_user_ptr(user_address), 4)) {
dev_err(hdev->dev, "Failed to copy completion value from user\n");
rc = -EFAULT;
- goto free_fence;
+ goto remove_pending_user_interrupt;
}
if (completion_value >= target_value)
*status = CS_WAIT_STATUS_BUSY;
if (!timeout_us || (*status == CS_WAIT_STATUS_COMPLETED))
- goto free_fence;
-
- /* Add pending user interrupt to relevant list for the interrupt
- * handler to monitor
- */
- spin_lock_irqsave(&interrupt->wait_list_lock, flags);
- list_add_tail(&pend->wait_list_node, &interrupt->wait_list_head);
- spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+ goto remove_pending_user_interrupt;
wait_again:
/* Wait for interrupt handler to signal completion */
* If comparison fails, keep waiting until timeout expires
*/
if (completion_rc > 0) {
+ spin_lock_irqsave(&interrupt->wait_list_lock, flags);
+ /* reinit_completion must be called before we check for user
+ * completion value, otherwise, if interrupt is received after
+ * the comparison and before the next wait_for_completion,
+ * we will reach timeout and fail
+ */
+ reinit_completion(&pend->fence.completion);
+ spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+
if (copy_from_user(&completion_value, u64_to_user_ptr(user_address), 4)) {
dev_err(hdev->dev, "Failed to copy completion value from user\n");
rc = -EFAULT;
if (completion_value >= target_value) {
*status = CS_WAIT_STATUS_COMPLETED;
} else {
- spin_lock_irqsave(&interrupt->wait_list_lock, flags);
- reinit_completion(&pend->fence.completion);
timeout = completion_rc;
-
- spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
goto wait_again;
}
} else if (completion_rc == -ERESTARTSYS) {
list_del(&pend->wait_list_node);
spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
-free_fence:
kfree(pend);
hl_ctx_put(ctx);
struct hl_cs_compl *cs_cmpl)
{
struct hl_cs_encaps_sig_handle *handle = cs->encaps_sig_hdl;
+ u32 offset = 0;
cs_cmpl->hw_sob = handle->hw_sob;
* set offset 1 for example he mean to wait only for the first
* signal only, which will be pre_sob_val, and if he set offset 2
* then the value required is (pre_sob_val + 1) and so on...
+ * if user set wait offset to 0, then treat it as legacy wait cs,
+ * wait for the next signal.
*/
- cs_cmpl->sob_val = handle->pre_sob_val +
- (job->encaps_sig_wait_offset - 1);
+ if (job->encaps_sig_wait_offset)
+ offset = job->encaps_sig_wait_offset - 1;
+
+ cs_cmpl->sob_val = handle->pre_sob_val + offset;
}
static int init_wait_cs(struct hl_device *hdev, struct hl_cs *cs,
static struct hl_hw_obj_name_entry gaudi_monitor_id_to_str[] = {
{ .id = 200, .name = "MON_OBJ_DMA_DOWN_FEEDBACK_RESET" },
- { .id = 201, .name = "MON_OBJ_DMA_UP_FEADBACK_RESET" },
+ { .id = 201, .name = "MON_OBJ_DMA_UP_FEEDBACK_RESET" },
{ .id = 203, .name = "MON_OBJ_DRAM_TO_SRAM_QUEUE_FENCE" },
{ .id = 204, .name = "MON_OBJ_TPC_0_CLK_GATE" },
{ .id = 205, .name = "MON_OBJ_TPC_1_CLK_GATE" },
{
struct gaudi_device *gaudi = hdev->asic_specific;
struct packet_msg_prot *cq_pkt;
+ u64 msi_addr;
u32 tmp;
cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
cq_pkt->ctl = cpu_to_le32(tmp);
cq_pkt->value = cpu_to_le32(1);
- if (!gaudi->multi_msi_mode)
- msi_vec = 0;
+ if (gaudi->multi_msi_mode)
+ msi_addr = mmPCIE_MSI_INTR_0 + msi_vec * 4;
+ else
+ msi_addr = mmPCIE_CORE_MSI_REQ;
- cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_MSI_INTR_0 + msi_vec * 4);
+ cq_pkt->addr = cpu_to_le64(CFG_BASE + msi_addr);
}
static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val)
#include "gaudiP.h"
#include "../include/gaudi/asic_reg/gaudi_regs.h"
-#define GAUDI_NUMBER_OF_RR_REGS 24
-#define GAUDI_NUMBER_OF_LBW_RANGES 12
+#define GAUDI_NUMBER_OF_LBW_RR_REGS 28
+#define GAUDI_NUMBER_OF_HBW_RR_REGS 24
+#define GAUDI_NUMBER_OF_LBW_RANGES 10
-static u64 gaudi_rr_lbw_hit_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_lbw_hit_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+ mmDMA_IF_W_S_SOB_HIT_WPROT,
mmDMA_IF_W_S_DMA0_HIT_WPROT,
mmDMA_IF_W_S_DMA1_HIT_WPROT,
+ mmDMA_IF_E_S_SOB_HIT_WPROT,
mmDMA_IF_E_S_DMA0_HIT_WPROT,
mmDMA_IF_E_S_DMA1_HIT_WPROT,
+ mmDMA_IF_W_N_SOB_HIT_WPROT,
mmDMA_IF_W_N_DMA0_HIT_WPROT,
mmDMA_IF_W_N_DMA1_HIT_WPROT,
+ mmDMA_IF_E_N_SOB_HIT_WPROT,
mmDMA_IF_E_N_DMA0_HIT_WPROT,
mmDMA_IF_E_N_DMA1_HIT_WPROT,
mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW,
mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW,
};
-static u64 gaudi_rr_lbw_hit_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_lbw_hit_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+ mmDMA_IF_W_S_SOB_HIT_RPROT,
mmDMA_IF_W_S_DMA0_HIT_RPROT,
mmDMA_IF_W_S_DMA1_HIT_RPROT,
+ mmDMA_IF_E_S_SOB_HIT_RPROT,
mmDMA_IF_E_S_DMA0_HIT_RPROT,
mmDMA_IF_E_S_DMA1_HIT_RPROT,
+ mmDMA_IF_W_N_SOB_HIT_RPROT,
mmDMA_IF_W_N_DMA0_HIT_RPROT,
mmDMA_IF_W_N_DMA1_HIT_RPROT,
+ mmDMA_IF_E_N_SOB_HIT_RPROT,
mmDMA_IF_E_N_DMA0_HIT_RPROT,
mmDMA_IF_E_N_DMA1_HIT_RPROT,
mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR,
mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR,
};
-static u64 gaudi_rr_lbw_min_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_lbw_min_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+ mmDMA_IF_W_S_SOB_MIN_WPROT_0,
mmDMA_IF_W_S_DMA0_MIN_WPROT_0,
mmDMA_IF_W_S_DMA1_MIN_WPROT_0,
+ mmDMA_IF_E_S_SOB_MIN_WPROT_0,
mmDMA_IF_E_S_DMA0_MIN_WPROT_0,
mmDMA_IF_E_S_DMA1_MIN_WPROT_0,
+ mmDMA_IF_W_N_SOB_MIN_WPROT_0,
mmDMA_IF_W_N_DMA0_MIN_WPROT_0,
mmDMA_IF_W_N_DMA1_MIN_WPROT_0,
+ mmDMA_IF_E_N_SOB_MIN_WPROT_0,
mmDMA_IF_E_N_DMA0_MIN_WPROT_0,
mmDMA_IF_E_N_DMA1_MIN_WPROT_0,
mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0,
mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0,
};
-static u64 gaudi_rr_lbw_max_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_lbw_max_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+ mmDMA_IF_W_S_SOB_MAX_WPROT_0,
mmDMA_IF_W_S_DMA0_MAX_WPROT_0,
mmDMA_IF_W_S_DMA1_MAX_WPROT_0,
+ mmDMA_IF_E_S_SOB_MAX_WPROT_0,
mmDMA_IF_E_S_DMA0_MAX_WPROT_0,
mmDMA_IF_E_S_DMA1_MAX_WPROT_0,
+ mmDMA_IF_W_N_SOB_MAX_WPROT_0,
mmDMA_IF_W_N_DMA0_MAX_WPROT_0,
mmDMA_IF_W_N_DMA1_MAX_WPROT_0,
+ mmDMA_IF_E_N_SOB_MAX_WPROT_0,
mmDMA_IF_E_N_DMA0_MAX_WPROT_0,
mmDMA_IF_E_N_DMA1_MAX_WPROT_0,
mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0,
mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0,
};
-static u64 gaudi_rr_lbw_min_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_lbw_min_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+ mmDMA_IF_W_S_SOB_MIN_RPROT_0,
mmDMA_IF_W_S_DMA0_MIN_RPROT_0,
mmDMA_IF_W_S_DMA1_MIN_RPROT_0,
+ mmDMA_IF_E_S_SOB_MIN_RPROT_0,
mmDMA_IF_E_S_DMA0_MIN_RPROT_0,
mmDMA_IF_E_S_DMA1_MIN_RPROT_0,
+ mmDMA_IF_W_N_SOB_MIN_RPROT_0,
mmDMA_IF_W_N_DMA0_MIN_RPROT_0,
mmDMA_IF_W_N_DMA1_MIN_RPROT_0,
+ mmDMA_IF_E_N_SOB_MIN_RPROT_0,
mmDMA_IF_E_N_DMA0_MIN_RPROT_0,
mmDMA_IF_E_N_DMA1_MIN_RPROT_0,
mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0,
mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0,
};
-static u64 gaudi_rr_lbw_max_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_lbw_max_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+ mmDMA_IF_W_S_SOB_MAX_RPROT_0,
mmDMA_IF_W_S_DMA0_MAX_RPROT_0,
mmDMA_IF_W_S_DMA1_MAX_RPROT_0,
+ mmDMA_IF_E_S_SOB_MAX_RPROT_0,
mmDMA_IF_E_S_DMA0_MAX_RPROT_0,
mmDMA_IF_E_S_DMA1_MAX_RPROT_0,
+ mmDMA_IF_W_N_SOB_MAX_RPROT_0,
mmDMA_IF_W_N_DMA0_MAX_RPROT_0,
mmDMA_IF_W_N_DMA1_MAX_RPROT_0,
+ mmDMA_IF_E_N_SOB_MAX_RPROT_0,
mmDMA_IF_E_N_DMA0_MAX_RPROT_0,
mmDMA_IF_E_N_DMA1_MAX_RPROT_0,
mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0,
mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0,
};
-static u64 gaudi_rr_hbw_hit_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_hit_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW,
mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW
};
-static u64 gaudi_rr_hbw_hit_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_hit_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR,
mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR
};
-static u64 gaudi_rr_hbw_base_low_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_base_low_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0
};
-static u64 gaudi_rr_hbw_base_high_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_base_high_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0
};
-static u64 gaudi_rr_hbw_mask_low_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_mask_low_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0
};
-static u64 gaudi_rr_hbw_mask_high_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_mask_high_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0
};
-static u64 gaudi_rr_hbw_base_low_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_base_low_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0
};
-static u64 gaudi_rr_hbw_base_high_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_base_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0
};
-static u64 gaudi_rr_hbw_mask_low_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_mask_low_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0,
mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0
};
-static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = {
+static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0,
mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0,
mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0,
u32 lbw_rng_end[GAUDI_NUMBER_OF_LBW_RANGES];
int i, j;
- lbw_rng_start[0] = (0xFBFE0000 & 0x3FFFFFF) - 1;
- lbw_rng_end[0] = (0xFBFFF000 & 0x3FFFFFF) + 1;
+ lbw_rng_start[0] = (0xFC0E8000 & 0x3FFFFFF) - 1; /* 0x000E7FFF */
+ lbw_rng_end[0] = (0xFC11FFFF & 0x3FFFFFF) + 1; /* 0x00120000 */
- lbw_rng_start[1] = (0xFC0E8000 & 0x3FFFFFF) - 1;
- lbw_rng_end[1] = (0xFC120000 & 0x3FFFFFF) + 1;
+ lbw_rng_start[1] = (0xFC1E8000 & 0x3FFFFFF) - 1; /* 0x001E7FFF */
+ lbw_rng_end[1] = (0xFC48FFFF & 0x3FFFFFF) + 1; /* 0x00490000 */
- lbw_rng_start[2] = (0xFC1E8000 & 0x3FFFFFF) - 1;
- lbw_rng_end[2] = (0xFC48FFFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[2] = (0xFC600000 & 0x3FFFFFF) - 1; /* 0x005FFFFF */
+ lbw_rng_end[2] = (0xFCC48FFF & 0x3FFFFFF) + 1; /* 0x00C49000 */
- lbw_rng_start[3] = (0xFC600000 & 0x3FFFFFF) - 1;
- lbw_rng_end[3] = (0xFCC48FFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[3] = (0xFCC4A000 & 0x3FFFFFF) - 1; /* 0x00C49FFF */
+ lbw_rng_end[3] = (0xFCCDFFFF & 0x3FFFFFF) + 1; /* 0x00CE0000 */
- lbw_rng_start[4] = (0xFCC4A000 & 0x3FFFFFF) - 1;
- lbw_rng_end[4] = (0xFCCDFFFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[4] = (0xFCCE4000 & 0x3FFFFFF) - 1; /* 0x00CE3FFF */
+ lbw_rng_end[4] = (0xFCD1FFFF & 0x3FFFFFF) + 1; /* 0x00D20000 */
- lbw_rng_start[5] = (0xFCCE4000 & 0x3FFFFFF) - 1;
- lbw_rng_end[5] = (0xFCD1FFFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[5] = (0xFCD24000 & 0x3FFFFFF) - 1; /* 0x00D23FFF */
+ lbw_rng_end[5] = (0xFCD5FFFF & 0x3FFFFFF) + 1; /* 0x00D60000 */
- lbw_rng_start[6] = (0xFCD24000 & 0x3FFFFFF) - 1;
- lbw_rng_end[6] = (0xFCD5FFFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[6] = (0xFCD64000 & 0x3FFFFFF) - 1; /* 0x00D63FFF */
+ lbw_rng_end[6] = (0xFCD9FFFF & 0x3FFFFFF) + 1; /* 0x00DA0000 */
- lbw_rng_start[7] = (0xFCD64000 & 0x3FFFFFF) - 1;
- lbw_rng_end[7] = (0xFCD9FFFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[7] = (0xFCDA4000 & 0x3FFFFFF) - 1; /* 0x00DA3FFF */
+ lbw_rng_end[7] = (0xFCDDFFFF & 0x3FFFFFF) + 1; /* 0x00DE0000 */
- lbw_rng_start[8] = (0xFCDA4000 & 0x3FFFFFF) - 1;
- lbw_rng_end[8] = (0xFCDDFFFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[8] = (0xFCDE4000 & 0x3FFFFFF) - 1; /* 0x00DE3FFF */
+ lbw_rng_end[8] = (0xFCE05FFF & 0x3FFFFFF) + 1; /* 0x00E06000 */
- lbw_rng_start[9] = (0xFCDE4000 & 0x3FFFFFF) - 1;
- lbw_rng_end[9] = (0xFCE05FFF & 0x3FFFFFF) + 1;
+ lbw_rng_start[9] = (0xFCFC9000 & 0x3FFFFFF) - 1; /* 0x00FC8FFF */
+ lbw_rng_end[9] = (0xFFFFFFFE & 0x3FFFFFF) + 1; /* 0x03FFFFFF */
- lbw_rng_start[10] = (0xFEC43000 & 0x3FFFFFF) - 1;
- lbw_rng_end[10] = (0xFEC43FFF & 0x3FFFFFF) + 1;
-
- lbw_rng_start[11] = (0xFE484000 & 0x3FFFFFF) - 1;
- lbw_rng_end[11] = (0xFE484FFF & 0x3FFFFFF) + 1;
-
- for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) {
+ for (i = 0 ; i < GAUDI_NUMBER_OF_LBW_RR_REGS ; i++) {
WREG32(gaudi_rr_lbw_hit_aw_regs[i],
(1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1);
WREG32(gaudi_rr_lbw_hit_ar_regs[i],
(1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1);
}
- for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++)
+ for (i = 0 ; i < GAUDI_NUMBER_OF_LBW_RR_REGS ; i++)
for (j = 0 ; j < GAUDI_NUMBER_OF_LBW_RANGES ; j++) {
WREG32(gaudi_rr_lbw_min_aw_regs[i] + (j << 2),
lbw_rng_start[j]);
* 6th range is the host
*/
- for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) {
+ for (i = 0 ; i < GAUDI_NUMBER_OF_HBW_RR_REGS ; i++) {
WREG32(gaudi_rr_hbw_hit_aw_regs[i], 0x1F);
WREG32(gaudi_rr_hbw_hit_ar_regs[i], 0x1D);
}
- for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) {
+ for (i = 0 ; i < GAUDI_NUMBER_OF_HBW_RR_REGS ; i++) {
WREG32(gaudi_rr_hbw_base_low_aw_regs[i], dram_addr_lo);
WREG32(gaudi_rr_hbw_base_low_ar_regs[i], dram_addr_lo);
#define mmPCIE_AUX_FLR_CTRL 0xC07394
#define mmPCIE_AUX_DBI 0xC07490
+#define mmPCIE_CORE_MSI_REQ 0xC04100
+
#define mmPSOC_PCI_PLL_NR 0xC72100
#define mmSRAM_W_PLL_NR 0x4C8100
#define mmPSOC_HBM_PLL_NR 0xC74100
static void b53_mdio_remove(struct mdio_device *mdiodev)
{
struct b53_device *dev = dev_get_drvdata(&mdiodev->dev);
- struct dsa_switch *ds = dev->ds;
- dsa_unregister_switch(ds);
+ if (!dev)
+ return;
+
+ b53_switch_remove(dev);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void b53_mdio_shutdown(struct mdio_device *mdiodev)
+{
+ struct b53_device *dev = dev_get_drvdata(&mdiodev->dev);
+
+ if (!dev)
+ return;
+
+ b53_switch_shutdown(dev);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static const struct of_device_id b53_of_match[] = {
static struct mdio_driver b53_mdio_driver = {
.probe = b53_mdio_probe,
.remove = b53_mdio_remove,
+ .shutdown = b53_mdio_shutdown,
.mdiodrv.driver = {
.name = "bcm53xx",
.of_match_table = b53_of_match,
if (dev)
b53_switch_remove(dev);
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
+static void b53_mmap_shutdown(struct platform_device *pdev)
+{
+ struct b53_device *dev = platform_get_drvdata(pdev);
+
+ if (dev)
+ b53_switch_shutdown(dev);
+
+ platform_set_drvdata(pdev, NULL);
+}
+
static const struct of_device_id b53_mmap_of_table[] = {
{ .compatible = "brcm,bcm3384-switch" },
{ .compatible = "brcm,bcm6328-switch" },
static struct platform_driver b53_mmap_driver = {
.probe = b53_mmap_probe,
.remove = b53_mmap_remove,
+ .shutdown = b53_mmap_shutdown,
.driver = {
.name = "b53-switch",
.of_match_table = b53_mmap_of_table,
dsa_unregister_switch(dev->ds);
}
+static inline void b53_switch_shutdown(struct b53_device *dev)
+{
+ dsa_switch_shutdown(dev->ds);
+}
+
#define b53_build_op(type_op_size, val_type) \
static inline int b53_##type_op_size(struct b53_device *dev, u8 page, \
u8 reg, val_type val) \
if (dev)
b53_switch_remove(dev);
+ spi_set_drvdata(spi, NULL);
+
return 0;
}
+static void b53_spi_shutdown(struct spi_device *spi)
+{
+ struct b53_device *dev = spi_get_drvdata(spi);
+
+ if (dev)
+ b53_switch_shutdown(dev);
+
+ spi_set_drvdata(spi, NULL);
+}
+
static const struct of_device_id b53_spi_of_match[] = {
{ .compatible = "brcm,bcm5325" },
{ .compatible = "brcm,bcm5365" },
},
.probe = b53_spi_probe,
.remove = b53_spi_remove,
+ .shutdown = b53_spi_shutdown,
};
module_spi_driver(b53_spi_driver);
static int b53_srab_remove(struct platform_device *pdev)
{
struct b53_device *dev = platform_get_drvdata(pdev);
- struct b53_srab_priv *priv = dev->priv;
- b53_srab_intr_set(priv, false);
+ if (!dev)
+ return 0;
+
+ b53_srab_intr_set(dev->priv, false);
b53_switch_remove(dev);
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
+static void b53_srab_shutdown(struct platform_device *pdev)
+{
+ struct b53_device *dev = platform_get_drvdata(pdev);
+
+ if (!dev)
+ return;
+
+ b53_switch_shutdown(dev);
+
+ platform_set_drvdata(pdev, NULL);
+}
+
static struct platform_driver b53_srab_driver = {
.probe = b53_srab_probe,
.remove = b53_srab_remove,
+ .shutdown = b53_srab_shutdown,
.driver = {
.name = "b53-srab-switch",
.of_match_table = b53_srab_of_match,
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
unsigned int port, count = 0;
- for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
+ for (port = 0; port < ds->num_ports; port++) {
if (dsa_is_cpu_port(ds, port))
continue;
if (priv->port_sts[port].enabled)
{
struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
+ if (!priv)
+ return 0;
+
priv->wol_ports_mask = 0;
/* Disable interrupts */
bcm_sf2_intr_disable(priv);
if (priv->type == BCM7278_DEVICE_ID)
reset_control_assert(priv->rcdev);
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
{
struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
+ if (!priv)
+ return;
+
/* For a kernel about to be kexec'd we want to keep the GPHY on for a
* successful MDIO bus scan to occur. If we did turn off the GPHY
* before (e.g: port_disable), this will also power it back on.
*/
if (priv->hw_params.num_gphy == 1)
bcm_sf2_gphy_enable_set(priv->dev->ds, true);
+
+ dsa_switch_shutdown(priv->dev->ds);
+
+ platform_set_drvdata(pdev, NULL);
}
#ifdef CONFIG_PM_SLEEP
static void dsa_loop_drv_remove(struct mdio_device *mdiodev)
{
struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
- struct dsa_loop_priv *ps = ds->priv;
+ struct dsa_loop_priv *ps;
+
+ if (!ds)
+ return;
+
+ ps = ds->priv;
dsa_unregister_switch(ds);
dev_put(ps->netdev);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void dsa_loop_drv_shutdown(struct mdio_device *mdiodev)
+{
+ struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
+
+ if (!ds)
+ return;
+
+ dsa_switch_shutdown(ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static struct mdio_driver dsa_loop_drv = {
},
.probe = dsa_loop_drv_probe,
.remove = dsa_loop_drv_remove,
+ .shutdown = dsa_loop_drv_shutdown,
};
#define NUM_FIXED_PHYS (DSA_LOOP_NUM_PORTS - 2)
{
struct hellcreek *hellcreek = platform_get_drvdata(pdev);
+ if (!hellcreek)
+ return 0;
+
hellcreek_hwtstamp_free(hellcreek);
hellcreek_ptp_free(hellcreek);
dsa_unregister_switch(hellcreek->ds);
return 0;
}
+static void hellcreek_shutdown(struct platform_device *pdev)
+{
+ struct hellcreek *hellcreek = platform_get_drvdata(pdev);
+
+ if (!hellcreek)
+ return;
+
+ dsa_switch_shutdown(hellcreek->ds);
+
+ platform_set_drvdata(pdev, NULL);
+}
+
static const struct hellcreek_platform_data de1soc_r1_pdata = {
.name = "r4c30",
.num_ports = 4,
static struct platform_driver hellcreek_driver = {
.probe = hellcreek_probe,
.remove = hellcreek_remove,
+ .shutdown = hellcreek_shutdown,
.driver = {
.name = "hellcreek",
.of_match_table = hellcreek_of_match,
}
EXPORT_SYMBOL(lan9303_remove);
+void lan9303_shutdown(struct lan9303 *chip)
+{
+ dsa_switch_shutdown(chip->ds);
+}
+EXPORT_SYMBOL(lan9303_shutdown);
+
MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
MODULE_LICENSE("GPL v2");
int lan9303_probe(struct lan9303 *chip, struct device_node *np);
int lan9303_remove(struct lan9303 *chip);
+void lan9303_shutdown(struct lan9303 *chip);
static int lan9303_i2c_remove(struct i2c_client *client)
{
- struct lan9303_i2c *sw_dev;
+ struct lan9303_i2c *sw_dev = i2c_get_clientdata(client);
- sw_dev = i2c_get_clientdata(client);
if (!sw_dev)
- return -ENODEV;
+ return 0;
+
+ lan9303_remove(&sw_dev->chip);
+
+ i2c_set_clientdata(client, NULL);
+
+ return 0;
+}
+
+static void lan9303_i2c_shutdown(struct i2c_client *client)
+{
+ struct lan9303_i2c *sw_dev = i2c_get_clientdata(client);
+
+ if (!sw_dev)
+ return;
+
+ lan9303_shutdown(&sw_dev->chip);
- return lan9303_remove(&sw_dev->chip);
+ i2c_set_clientdata(client, NULL);
}
/*-------------------------------------------------------------------------*/
},
.probe = lan9303_i2c_probe,
.remove = lan9303_i2c_remove,
+ .shutdown = lan9303_i2c_shutdown,
.id_table = lan9303_i2c_id,
};
module_i2c_driver(lan9303_i2c_driver);
return;
lan9303_remove(&sw_dev->chip);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void lan9303_mdio_shutdown(struct mdio_device *mdiodev)
+{
+ struct lan9303_mdio *sw_dev = dev_get_drvdata(&mdiodev->dev);
+
+ if (!sw_dev)
+ return;
+
+ lan9303_shutdown(&sw_dev->chip);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
/*-------------------------------------------------------------------------*/
},
.probe = lan9303_mdio_probe,
.remove = lan9303_mdio_remove,
+ .shutdown = lan9303_mdio_shutdown,
};
mdio_module_driver(lan9303_mdio_driver);
reset_control_assert(gphy_fw->reset);
+ /* The vendor BSP uses a 200ms delay after asserting the reset line.
+ * Without this some users are observing that the PHY is not coming up
+ * on the MDIO bus.
+ */
+ msleep(200);
+
ret = request_firmware(&fw, gphy_fw->fw_name, dev);
if (ret) {
dev_err(dev, "failed to load firmware: %s, error: %i\n",
struct gswip_priv *priv = platform_get_drvdata(pdev);
int i;
+ if (!priv)
+ return 0;
+
/* disable the switch */
gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
for (i = 0; i < priv->num_gphy_fw; i++)
gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
+static void gswip_shutdown(struct platform_device *pdev)
+{
+ struct gswip_priv *priv = platform_get_drvdata(pdev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ platform_set_drvdata(pdev, NULL);
+}
+
static const struct gswip_hw_info gswip_xrx200 = {
.max_ports = 7,
.cpu_port = 6,
static struct platform_driver gswip_driver = {
.probe = gswip_probe,
.remove = gswip_remove,
+ .shutdown = gswip_shutdown,
.driver = {
.name = "gswip",
.of_match_table = gswip_of_match,
if (dev)
ksz_switch_remove(dev);
+ spi_set_drvdata(spi, NULL);
+
return 0;
}
{
struct ksz_device *dev = spi_get_drvdata(spi);
- if (dev && dev->dev_ops->shutdown)
+ if (!dev)
+ return;
+
+ if (dev->dev_ops->shutdown)
dev->dev_ops->shutdown(dev);
+
+ dsa_switch_shutdown(dev->ds);
+
+ spi_set_drvdata(spi, NULL);
}
static const struct of_device_id ksz8795_dt_ids[] = {
if (dev)
ksz_switch_remove(dev);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void ksz8863_smi_shutdown(struct mdio_device *mdiodev)
+{
+ struct ksz_device *dev = dev_get_drvdata(&mdiodev->dev);
+
+ if (dev)
+ dsa_switch_shutdown(dev->ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static const struct of_device_id ksz8863_dt_ids[] = {
static struct mdio_driver ksz8863_driver = {
.probe = ksz8863_smi_probe,
.remove = ksz8863_smi_remove,
+ .shutdown = ksz8863_smi_shutdown,
.mdiodrv.driver = {
.name = "ksz8863-switch",
.of_match_table = ksz8863_dt_ids,
{
struct ksz_device *dev = i2c_get_clientdata(i2c);
- ksz_switch_remove(dev);
+ if (dev)
+ ksz_switch_remove(dev);
+
+ i2c_set_clientdata(i2c, NULL);
return 0;
}
{
struct ksz_device *dev = i2c_get_clientdata(i2c);
- if (dev && dev->dev_ops->shutdown)
+ if (!dev)
+ return;
+
+ if (dev->dev_ops->shutdown)
dev->dev_ops->shutdown(dev);
+
+ dsa_switch_shutdown(dev->ds);
+
+ i2c_set_clientdata(i2c, NULL);
}
static const struct i2c_device_id ksz9477_i2c_id[] = {
if (dev)
ksz_switch_remove(dev);
+ spi_set_drvdata(spi, NULL);
+
return 0;
}
{
struct ksz_device *dev = spi_get_drvdata(spi);
- if (dev && dev->dev_ops->shutdown)
- dev->dev_ops->shutdown(dev);
+ if (dev)
+ dsa_switch_shutdown(dev->ds);
+
+ spi_set_drvdata(spi, NULL);
}
static const struct of_device_id ksz9477_dt_ids[] = {
struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
int ret = 0;
+ if (!priv)
+ return;
+
ret = regulator_disable(priv->core_pwr);
if (ret < 0)
dev_err(priv->dev,
dsa_unregister_switch(priv->ds);
mutex_destroy(&priv->reg_mutex);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void mt7530_shutdown(struct mdio_device *mdiodev)
+{
+ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static struct mdio_driver mt7530_mdio_driver = {
.probe = mt7530_probe,
.remove = mt7530_remove,
+ .shutdown = mt7530_shutdown,
.mdiodrv.driver = {
.name = "mt7530",
.of_match_table = mt7530_of_match,
{
struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
+ if (!ds)
+ return;
+
dsa_unregister_switch(ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void mv88e6060_shutdown(struct mdio_device *mdiodev)
+{
+ struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
+
+ if (!ds)
+ return;
+
+ dsa_switch_shutdown(ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static const struct of_device_id mv88e6060_of_match[] = {
static struct mdio_driver mv88e6060_driver = {
.probe = mv88e6060_probe,
.remove = mv88e6060_remove,
+ .shutdown = mv88e6060_shutdown,
.mdiodrv.driver = {
.name = "mv88e6060",
.of_match_table = mv88e6060_of_match,
{
mv88e6xxx_teardown_devlink_params(ds);
dsa_devlink_resources_unregister(ds);
- mv88e6xxx_teardown_devlink_regions(ds);
+ mv88e6xxx_teardown_devlink_regions_global(ds);
}
static int mv88e6xxx_setup(struct dsa_switch *ds)
if (err)
goto out_resources;
- err = mv88e6xxx_setup_devlink_regions(ds);
+ err = mv88e6xxx_setup_devlink_regions_global(ds);
if (err)
goto out_params;
return err;
}
+static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
+{
+ return mv88e6xxx_setup_devlink_regions_port(ds, port);
+}
+
+static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
+{
+ mv88e6xxx_teardown_devlink_regions_port(ds, port);
+}
+
/* prod_id for switch families which do not have a PHY model number */
static const u16 family_prod_id_table[] = {
[MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
.change_tag_protocol = mv88e6xxx_change_tag_protocol,
.setup = mv88e6xxx_setup,
.teardown = mv88e6xxx_teardown,
+ .port_setup = mv88e6xxx_port_setup,
+ .port_teardown = mv88e6xxx_port_teardown,
.phylink_validate = mv88e6xxx_validate,
.phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
.phylink_mac_config = mv88e6xxx_mac_config,
static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
- struct mv88e6xxx_chip *chip = ds->priv;
+ struct mv88e6xxx_chip *chip;
+
+ if (!ds)
+ return;
+
+ chip = ds->priv;
if (chip->info->ptp_support) {
mv88e6xxx_hwtstamp_free(chip);
mv88e6xxx_g1_irq_free(chip);
else
mv88e6xxx_irq_poll_free(chip);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
+{
+ struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
+
+ if (!ds)
+ return;
+
+ dsa_switch_shutdown(ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static const struct of_device_id mv88e6xxx_of_match[] = {
static struct mdio_driver mv88e6xxx_driver = {
.probe = mv88e6xxx_probe,
.remove = mv88e6xxx_remove,
+ .shutdown = mv88e6xxx_shutdown,
.mdiodrv.driver = {
.name = "mv88e6085",
.of_match_table = mv88e6xxx_of_match,
},
};
-static void
-mv88e6xxx_teardown_devlink_regions_global(struct mv88e6xxx_chip *chip)
+void mv88e6xxx_teardown_devlink_regions_global(struct dsa_switch *ds)
{
+ struct mv88e6xxx_chip *chip = ds->priv;
int i;
for (i = 0; i < ARRAY_SIZE(mv88e6xxx_regions); i++)
dsa_devlink_region_destroy(chip->regions[i]);
}
-static void
-mv88e6xxx_teardown_devlink_regions_port(struct mv88e6xxx_chip *chip,
- int port)
+void mv88e6xxx_teardown_devlink_regions_port(struct dsa_switch *ds, int port)
{
+ struct mv88e6xxx_chip *chip = ds->priv;
+
dsa_devlink_region_destroy(chip->ports[port].region);
}
-static int mv88e6xxx_setup_devlink_regions_port(struct dsa_switch *ds,
- struct mv88e6xxx_chip *chip,
- int port)
+int mv88e6xxx_setup_devlink_regions_port(struct dsa_switch *ds, int port)
{
+ struct mv88e6xxx_chip *chip = ds->priv;
struct devlink_region *region;
region = dsa_devlink_port_region_create(ds,
return 0;
}
-static void
-mv88e6xxx_teardown_devlink_regions_ports(struct mv88e6xxx_chip *chip)
-{
- int port;
-
- for (port = 0; port < mv88e6xxx_num_ports(chip); port++)
- mv88e6xxx_teardown_devlink_regions_port(chip, port);
-}
-
-static int mv88e6xxx_setup_devlink_regions_ports(struct dsa_switch *ds,
- struct mv88e6xxx_chip *chip)
-{
- int port;
- int err;
-
- for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
- err = mv88e6xxx_setup_devlink_regions_port(ds, chip, port);
- if (err)
- goto out;
- }
-
- return 0;
-
-out:
- while (port-- > 0)
- mv88e6xxx_teardown_devlink_regions_port(chip, port);
-
- return err;
-}
-
-static int mv88e6xxx_setup_devlink_regions_global(struct dsa_switch *ds,
- struct mv88e6xxx_chip *chip)
+int mv88e6xxx_setup_devlink_regions_global(struct dsa_switch *ds)
{
bool (*cond)(struct mv88e6xxx_chip *chip);
+ struct mv88e6xxx_chip *chip = ds->priv;
struct devlink_region_ops *ops;
struct devlink_region *region;
u64 size;
return PTR_ERR(region);
}
-int mv88e6xxx_setup_devlink_regions(struct dsa_switch *ds)
-{
- struct mv88e6xxx_chip *chip = ds->priv;
- int err;
-
- err = mv88e6xxx_setup_devlink_regions_global(ds, chip);
- if (err)
- return err;
-
- err = mv88e6xxx_setup_devlink_regions_ports(ds, chip);
- if (err)
- mv88e6xxx_teardown_devlink_regions_global(chip);
-
- return err;
-}
-
-void mv88e6xxx_teardown_devlink_regions(struct dsa_switch *ds)
-{
- struct mv88e6xxx_chip *chip = ds->priv;
-
- mv88e6xxx_teardown_devlink_regions_ports(chip);
- mv88e6xxx_teardown_devlink_regions_global(chip);
-}
-
int mv88e6xxx_devlink_info_get(struct dsa_switch *ds,
struct devlink_info_req *req,
struct netlink_ext_ack *extack)
struct devlink_param_gset_ctx *ctx);
int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
struct devlink_param_gset_ctx *ctx);
-int mv88e6xxx_setup_devlink_regions(struct dsa_switch *ds);
-void mv88e6xxx_teardown_devlink_regions(struct dsa_switch *ds);
+int mv88e6xxx_setup_devlink_regions_global(struct dsa_switch *ds);
+void mv88e6xxx_teardown_devlink_regions_global(struct dsa_switch *ds);
+int mv88e6xxx_setup_devlink_regions_port(struct dsa_switch *ds, int port);
+void mv88e6xxx_teardown_devlink_regions_port(struct dsa_switch *ds, int port);
int mv88e6xxx_devlink_info_get(struct dsa_switch *ds,
struct devlink_info_req *req,
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2019-2021 NXP Semiconductors
+/* Copyright 2019-2021 NXP
*
* This is an umbrella module for all network switches that are
* register-compatible with Ocelot and that perform I/O to their host CPU
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright 2019 NXP Semiconductors
+/* Copyright 2019 NXP
*/
#ifndef _MSCC_FELIX_H
#define _MSCC_FELIX_H
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright 2017 Microsemi Corporation
- * Copyright 2018-2019 NXP Semiconductors
+ * Copyright 2018-2019 NXP
*/
#include <linux/fsl/enetc_mdio.h>
#include <soc/mscc/ocelot_qsys.h>
static void felix_pci_remove(struct pci_dev *pdev)
{
- struct felix *felix;
+ struct felix *felix = pci_get_drvdata(pdev);
- felix = pci_get_drvdata(pdev);
+ if (!felix)
+ return;
dsa_unregister_switch(felix->ds);
kfree(felix);
pci_disable_device(pdev);
+
+ pci_set_drvdata(pdev, NULL);
+}
+
+static void felix_pci_shutdown(struct pci_dev *pdev)
+{
+ struct felix *felix = pci_get_drvdata(pdev);
+
+ if (!felix)
+ return;
+
+ dsa_switch_shutdown(felix->ds);
+
+ pci_set_drvdata(pdev, NULL);
}
static struct pci_device_id felix_ids[] = {
.id_table = felix_ids,
.probe = felix_pci_probe,
.remove = felix_pci_remove,
+ .shutdown = felix_pci_shutdown,
};
module_pci_driver(felix_vsc9959_pci_driver);
static int seville_remove(struct platform_device *pdev)
{
- struct felix *felix;
+ struct felix *felix = platform_get_drvdata(pdev);
- felix = platform_get_drvdata(pdev);
+ if (!felix)
+ return 0;
dsa_unregister_switch(felix->ds);
kfree(felix->ds);
kfree(felix);
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
+static void seville_shutdown(struct platform_device *pdev)
+{
+ struct felix *felix = platform_get_drvdata(pdev);
+
+ if (!felix)
+ return;
+
+ dsa_switch_shutdown(felix->ds);
+
+ platform_set_drvdata(pdev, NULL);
+}
+
static const struct of_device_id seville_of_match[] = {
{ .compatible = "mscc,vsc9953-switch" },
{ },
static struct platform_driver seville_vsc9953_driver = {
.probe = seville_probe,
.remove = seville_remove,
+ .shutdown = seville_shutdown,
.driver = {
.name = "mscc_seville",
.of_match_table = of_match_ptr(seville_of_match),
struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
unsigned int i;
+ if (!priv)
+ return;
+
for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
struct ar9331_sw_port *port = &priv->port[i];
dsa_unregister_switch(&priv->ds);
reset_control_assert(priv->sw_reset);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void ar9331_sw_shutdown(struct mdio_device *mdiodev)
+{
+ struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(&priv->ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static const struct of_device_id ar9331_sw_of_match[] = {
static struct mdio_driver ar9331_sw_mdio_driver = {
.probe = ar9331_sw_probe,
.remove = ar9331_sw_remove,
+ .shutdown = ar9331_sw_shutdown,
.mdiodrv.driver = {
.name = AR9331_SW_NAME,
.of_match_table = ar9331_sw_of_match,
}
static int
-qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data)
+qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)
{
- struct qca8k_priv *priv = salve_bus->priv;
- struct mii_bus *bus = priv->bus;
u16 r1, r2, page;
u32 val;
int ret;
}
static int
-qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)
+qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)
{
- struct qca8k_priv *priv = salve_bus->priv;
- struct mii_bus *bus = priv->bus;
u16 r1, r2, page;
u32 val;
int ret;
}
static int
+qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
+{
+ struct qca8k_priv *priv = slave_bus->priv;
+ struct mii_bus *bus = priv->bus;
+
+ return qca8k_mdio_write(bus, phy, regnum, data);
+}
+
+static int
+qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
+{
+ struct qca8k_priv *priv = slave_bus->priv;
+ struct mii_bus *bus = priv->bus;
+
+ return qca8k_mdio_read(bus, phy, regnum);
+}
+
+static int
qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
{
struct qca8k_priv *priv = ds->priv;
bus->priv = (void *)priv;
bus->name = "qca8k slave mii";
- bus->read = qca8k_mdio_read;
- bus->write = qca8k_mdio_write;
+ bus->read = qca8k_internal_mdio_read;
+ bus->write = qca8k_internal_mdio_write;
snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
ds->index);
struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
int i;
+ if (!priv)
+ return;
+
for (i = 0; i < QCA8K_NUM_PORTS; i++)
qca8k_port_set_status(priv, i, 0);
dsa_unregister_switch(priv->ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
+{
+ struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
#ifdef CONFIG_PM_SLEEP
static struct mdio_driver qca8kmdio_driver = {
.probe = qca8k_sw_probe,
.remove = qca8k_sw_remove,
+ .shutdown = qca8k_sw_shutdown,
.mdiodrv.driver = {
.name = "qca8k",
.of_match_table = qca8k_of_match,
smi->slave_mii_bus->parent = smi->dev;
smi->ds->slave_mii_bus = smi->slave_mii_bus;
- ret = of_mdiobus_register(smi->slave_mii_bus, mdio_np);
+ ret = devm_of_mdiobus_register(smi->dev, smi->slave_mii_bus, mdio_np);
if (ret) {
dev_err(smi->dev, "unable to register MDIO bus %s\n",
smi->slave_mii_bus->id);
static int realtek_smi_remove(struct platform_device *pdev)
{
- struct realtek_smi *smi = dev_get_drvdata(&pdev->dev);
+ struct realtek_smi *smi = platform_get_drvdata(pdev);
+
+ if (!smi)
+ return 0;
dsa_unregister_switch(smi->ds);
if (smi->slave_mii_bus)
of_node_put(smi->slave_mii_bus->dev.of_node);
gpiod_set_value(smi->reset, 1);
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
+static void realtek_smi_shutdown(struct platform_device *pdev)
+{
+ struct realtek_smi *smi = platform_get_drvdata(pdev);
+
+ if (!smi)
+ return;
+
+ dsa_switch_shutdown(smi->ds);
+
+ platform_set_drvdata(pdev, NULL);
+}
+
static const struct of_device_id realtek_smi_of_match[] = {
{
.compatible = "realtek,rtl8366rb",
},
.probe = realtek_smi_probe,
.remove = realtek_smi_remove,
+ .shutdown = realtek_smi_shutdown,
};
module_platform_driver(realtek_smi_driver);
// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (c) 2016-2018, NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
*/
#include <linux/packing.h>
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
- * Copyright 2020 NXP Semiconductors
+ * Copyright 2020 NXP
*/
#include "sja1105.h"
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2020, NXP Semiconductors
+/* Copyright 2020 NXP
*/
#include "sja1105.h"
#include "sja1105_vl.h"
static int sja1105_remove(struct spi_device *spi)
{
struct sja1105_private *priv = spi_get_drvdata(spi);
- struct dsa_switch *ds = priv->ds;
- dsa_unregister_switch(ds);
+ if (!priv)
+ return 0;
+
+ dsa_unregister_switch(priv->ds);
+
+ spi_set_drvdata(spi, NULL);
return 0;
}
+static void sja1105_shutdown(struct spi_device *spi)
+{
+ struct sja1105_private *priv = spi_get_drvdata(spi);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ spi_set_drvdata(spi, NULL);
+}
+
static const struct of_device_id sja1105_dt_ids[] = {
{ .compatible = "nxp,sja1105e", .data = &sja1105e_info },
{ .compatible = "nxp,sja1105t", .data = &sja1105t_info },
},
.probe = sja1105_probe,
.remove = sja1105_remove,
+ .shutdown = sja1105_shutdown,
};
module_spi_driver(sja1105_driver);
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2021, NXP Semiconductors
+/* Copyright 2021 NXP
*/
#include <linux/pcs/pcs-xpcs.h>
#include <linux/of_mdio.h>
// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (c) 2016-2018, NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
*/
// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (c) 2016-2018, NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
*/
#include "sja1105_static_config.h"
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (c) 2016-2018, NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
*/
#ifndef _SJA1105_STATIC_CONFIG_H
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2020, NXP Semiconductors
+/* Copyright 2020 NXP
*/
#include <net/tc_act/tc_gate.h>
#include <linux/dsa/8021q.h>
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright 2020, NXP Semiconductors
+/* Copyright 2020 NXP
*/
#ifndef _SJA1105_VL_H
#define _SJA1105_VL_H
}
EXPORT_SYMBOL(vsc73xx_remove);
+void vsc73xx_shutdown(struct vsc73xx *vsc)
+{
+ dsa_switch_shutdown(vsc->ds);
+}
+EXPORT_SYMBOL(vsc73xx_shutdown);
+
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver");
MODULE_LICENSE("GPL v2");
{
struct vsc73xx_platform *vsc_platform = platform_get_drvdata(pdev);
- return vsc73xx_remove(&vsc_platform->vsc);
+ if (!vsc_platform)
+ return 0;
+
+ vsc73xx_remove(&vsc_platform->vsc);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static void vsc73xx_platform_shutdown(struct platform_device *pdev)
+{
+ struct vsc73xx_platform *vsc_platform = platform_get_drvdata(pdev);
+
+ if (!vsc_platform)
+ return;
+
+ vsc73xx_shutdown(&vsc_platform->vsc);
+
+ platform_set_drvdata(pdev, NULL);
}
static const struct vsc73xx_ops vsc73xx_platform_ops = {
static struct platform_driver vsc73xx_platform_driver = {
.probe = vsc73xx_platform_probe,
.remove = vsc73xx_platform_remove,
+ .shutdown = vsc73xx_platform_shutdown,
.driver = {
.name = "vsc73xx-platform",
.of_match_table = vsc73xx_of_match,
{
struct vsc73xx_spi *vsc_spi = spi_get_drvdata(spi);
- return vsc73xx_remove(&vsc_spi->vsc);
+ if (!vsc_spi)
+ return 0;
+
+ vsc73xx_remove(&vsc_spi->vsc);
+
+ spi_set_drvdata(spi, NULL);
+
+ return 0;
+}
+
+static void vsc73xx_spi_shutdown(struct spi_device *spi)
+{
+ struct vsc73xx_spi *vsc_spi = spi_get_drvdata(spi);
+
+ if (!vsc_spi)
+ return;
+
+ vsc73xx_shutdown(&vsc_spi->vsc);
+
+ spi_set_drvdata(spi, NULL);
}
static const struct vsc73xx_ops vsc73xx_spi_ops = {
static struct spi_driver vsc73xx_spi_driver = {
.probe = vsc73xx_spi_probe,
.remove = vsc73xx_spi_remove,
+ .shutdown = vsc73xx_spi_shutdown,
.driver = {
.name = "vsc73xx-spi",
.of_match_table = vsc73xx_of_match,
int vsc73xx_is_addr_valid(u8 block, u8 subblock);
int vsc73xx_probe(struct vsc73xx *vsc);
int vsc73xx_remove(struct vsc73xx *vsc);
+void vsc73xx_shutdown(struct vsc73xx *vsc);
}
EXPORT_SYMBOL(xrs700x_switch_remove);
+void xrs700x_switch_shutdown(struct xrs700x *priv)
+{
+ dsa_switch_shutdown(priv->ds);
+}
+EXPORT_SYMBOL(xrs700x_switch_shutdown);
+
MODULE_AUTHOR("George McCollister <george.mccollister@gmail.com>");
MODULE_DESCRIPTION("Arrow SpeedChips XRS700x DSA driver");
MODULE_LICENSE("GPL v2");
struct xrs700x *xrs700x_switch_alloc(struct device *base, void *devpriv);
int xrs700x_switch_register(struct xrs700x *priv);
void xrs700x_switch_remove(struct xrs700x *priv);
+void xrs700x_switch_shutdown(struct xrs700x *priv);
{
struct xrs700x *priv = i2c_get_clientdata(i2c);
+ if (!priv)
+ return 0;
+
xrs700x_switch_remove(priv);
+ i2c_set_clientdata(i2c, NULL);
+
return 0;
}
+static void xrs700x_i2c_shutdown(struct i2c_client *i2c)
+{
+ struct xrs700x *priv = i2c_get_clientdata(i2c);
+
+ if (!priv)
+ return;
+
+ xrs700x_switch_shutdown(priv);
+
+ i2c_set_clientdata(i2c, NULL);
+}
+
static const struct i2c_device_id xrs700x_i2c_id[] = {
{ "xrs700x-switch", 0 },
{},
},
.probe = xrs700x_i2c_probe,
.remove = xrs700x_i2c_remove,
+ .shutdown = xrs700x_i2c_shutdown,
.id_table = xrs700x_i2c_id,
};
{
struct xrs700x *priv = dev_get_drvdata(&mdiodev->dev);
+ if (!priv)
+ return;
+
xrs700x_switch_remove(priv);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
+}
+
+static void xrs700x_mdio_shutdown(struct mdio_device *mdiodev)
+{
+ struct xrs700x *priv = dev_get_drvdata(&mdiodev->dev);
+
+ if (!priv)
+ return;
+
+ xrs700x_switch_shutdown(priv);
+
+ dev_set_drvdata(&mdiodev->dev, NULL);
}
static const struct of_device_id __maybe_unused xrs700x_mdio_dt_ids[] = {
},
.probe = xrs700x_mdio_probe,
.remove = xrs700x_mdio_remove,
+ .shutdown = xrs700x_mdio_shutdown,
};
mdio_module_driver(xrs700x_mdio_driver);
#ifdef VORTEX_BUS_MASTER
if (vp->bus_master) {
/* Set the bus-master controller to transfer the packet. */
- outl((int) (skb->data), ioaddr + Wn7_MasterAddr);
+ outl(isa_virt_to_bus(skb->data), ioaddr + Wn7_MasterAddr);
outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
vp->tx_skb = skb;
outw(StartDMADown, ioaddr + EL3_CMD);
}
}
-#ifdef MODULE
static int __init ne_init(void)
{
int retval;
- ne_add_devices();
+
+ if (IS_MODULE(CONFIG_NE2000))
+ ne_add_devices();
+
retval = platform_driver_probe(&ne_driver, ne_drv_probe);
- if (retval) {
+
+ if (IS_MODULE(CONFIG_NE2000) && retval) {
if (io[0] == 0)
pr_notice("ne.c: You must supply \"io=0xNNN\""
" value(s) for ISA cards.\n");
return retval;
}
module_init(ne_init);
-#else /* MODULE */
-static int __init ne_init(void)
-{
- int retval = platform_driver_probe(&ne_driver, ne_drv_probe);
-
- /* Unregister unused platform_devices. */
- ne_loop_rm_unreg(0);
- return retval;
-}
-module_init(ne_init);
-#ifdef CONFIG_NETDEV_LEGACY_INIT
+#if !defined(MODULE) && defined(CONFIG_NETDEV_LEGACY_INIT)
struct net_device * __init ne_probe(int unit)
{
int this_dev;
return ERR_PTR(-ENODEV);
}
#endif
-#endif /* MODULE */
static void __exit ne_exit(void)
{
#ifdef XMT_VIA_SKB
skb_save[i] = p->tmd_skb[i];
#endif
- buffer[i] = (u32) isa_bus_to_virt(tmdp->u.buffer);
+ buffer[i] = (unsigned long)isa_bus_to_virt(tmdp->u.buffer);
blen[i] = tmdp->blen;
tmdp->u.s.status = 0x0;
}
if (deep) {
/* Reinitialize Nic/Vecs objects */
aq_nic_deinit(nic, !nic->aq_hw->aq_nic_cfg->wol);
+ }
+ if (netif_running(nic->ndev)) {
ret = aq_nic_init(nic);
if (ret)
goto err_exit;
- }
- if (netif_running(nic->ndev)) {
ret = aq_nic_start(nic);
if (ret)
goto err_exit;
bcma_set_drvdata(core, bgmac);
err = of_get_mac_address(bgmac->dev->of_node, bgmac->net_dev->dev_addr);
+ if (err == -EPROBE_DEFER)
+ return err;
/* If no MAC address assigned via device tree, check SPROM */
if (err) {
/* SR-IOV capability was enabled but there are no VFs*/
if (iov->total == 0) {
- err = -EINVAL;
+ err = 0;
goto failed;
}
* netif_tx_queue_stopped().
*/
smp_mb();
- if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) {
+ if (bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh) {
netif_tx_wake_queue(txq);
return false;
}
smp_mb();
if (unlikely(netif_tx_queue_stopped(txq)) &&
- bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
+ bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh &&
READ_ONCE(txr->dev_state) != BNXT_DEV_STATE_CLOSING)
netif_tx_wake_queue(txq);
}
DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
bp->current_interval * 10);
fw_health->tmr_counter = fw_health->tmr_multiplier;
- if (!fw_health->enabled) {
+ if (!fw_health->enabled)
fw_health->last_fw_heartbeat =
bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
- fw_health->last_fw_reset_cnt =
- bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
- }
+ fw_health->last_fw_reset_cnt =
+ bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
netif_info(bp, drv, bp->dev,
"Error recovery info: error recovery[1], master[%d], reset count[%u], health status: 0x%x\n",
fw_health->master, fw_health->last_fw_reset_cnt,
if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
tx_pkts++;
/* return full budget so NAPI will complete. */
- if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
+ if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
rx_pkts = budget;
raw_cons = NEXT_RAW_CMP(raw_cons);
if (budget)
struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
int j;
+ if (!txr->tx_buf_ring)
+ continue;
+
for (j = 0; j < max_idx;) {
struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
struct sk_buff *skb;
}
skip_rx_tpa_free:
+ if (!rxr->rx_buf_ring)
+ goto skip_rx_buf_free;
+
for (i = 0; i < max_idx; i++) {
struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
dma_addr_t mapping = rx_buf->mapping;
kfree(data);
}
}
+
+skip_rx_buf_free:
+ if (!rxr->rx_agg_ring)
+ goto skip_rx_agg_free;
+
for (i = 0; i < max_agg_idx; i++) {
struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
struct page *page = rx_agg_buf->page;
__free_page(page);
}
+
+skip_rx_agg_free:
if (rxr->rx_page) {
__free_page(rxr->rx_page);
rxr->rx_page = NULL;
struct pci_dev *pdev = bp->pdev;
int i;
+ if (!rmem->pg_arr)
+ goto skip_pages;
+
for (i = 0; i < rmem->nr_pages; i++) {
if (!rmem->pg_arr[i])
continue;
rmem->pg_arr[i] = NULL;
}
+skip_pages:
if (rmem->pg_tbl) {
size_t pg_tbl_size = rmem->nr_pages * 8;
static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr)
{
+ struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
+
kfree(cpr->cp_desc_ring);
cpr->cp_desc_ring = NULL;
+ ring->ring_mem.pg_arr = NULL;
kfree(cpr->cp_desc_mapping);
cpr->cp_desc_mapping = NULL;
+ ring->ring_mem.dma_arr = NULL;
}
static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n)
u16 i;
bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
- MAX_SKB_FRAGS + 1);
+ BNXT_MIN_TX_DESC_CNT);
for (i = 0; i < bp->tx_nr_rings; i++) {
struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
return;
}
+ if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) &&
+ bp->fw_health->enabled) {
+ bp->fw_health->last_fw_reset_cnt =
+ bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
+ }
bp->fw_reset_state = 0;
/* Make sure fw_reset_state is 0 before clearing the flag */
smp_mb__before_atomic();
#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
+/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
+ * BD because the first TX BD is always a long BD.
+ */
+#define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
+
#define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
(ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
- (ering->tx_pending <= MAX_SKB_FRAGS))
+ (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
return -EINVAL;
if (netif_running(dev))
{
struct bnxt_flower_indr_block_cb_priv *cb_priv;
- /* All callback list access should be protected by RTNL. */
- ASSERT_RTNL();
-
list_for_each_entry(cb_priv, &bp->tc_indr_block_list, list)
if (cb_priv->tunnel_netdev == netdev)
return cb_priv;
struct platform_device *plat_dev = pci_get_drvdata(pdev);
struct macb_platform_data *plat_data = dev_get_platdata(&plat_dev->dev);
- platform_device_unregister(plat_dev);
clk_unregister(plat_data->pclk);
clk_unregister(plat_data->hclk);
+ platform_device_unregister(plat_dev);
}
static const struct pci_device_id dev_id_table[] = {
static void enetc_rx_net_dim(struct enetc_int_vector *v)
{
- struct dim_sample dim_sample;
+ struct dim_sample dim_sample = {};
v->comp_cnt++;
static int enetc_setup_irqs(struct enetc_ndev_priv *priv)
{
struct pci_dev *pdev = priv->si->pdev;
- cpumask_t cpu_mask;
int i, j, err;
for (i = 0; i < priv->bdr_int_num; i++) {
enetc_wr(hw, ENETC_SIMSITRV(idx), entry);
}
- cpumask_clear(&cpu_mask);
- cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
- irq_set_affinity_hint(irq, &cpu_mask);
+ irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus()));
}
return 0;
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/* Copyright 2021 NXP Semiconductors
+/* Copyright 2021 NXP
*
* The Integrated Endpoint Register Block (IERB) is configured by pre-boot
* software and is supposed to be to ENETC what a NVRAM is to a 'real' PCIe
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/* Copyright 2021 NXP Semiconductors */
+/* Copyright 2021 NXP */
#include <linux/pci.h>
#include <linux/platform_device.h>
module_platform_driver(fec_driver);
-MODULE_ALIAS("platform:"DRIVER_NAME);
MODULE_LICENSE("GPL");
module_param(tx_sgl, uint, 0600);
MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
+static bool page_pool_enabled = true;
+module_param(page_pool_enabled, bool, 0400);
+
#define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
sizeof(struct sg_table))
#define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
#define HNS3_OUTER_VLAN_TAG 2
#define HNS3_MIN_TX_LEN 33U
+#define HNS3_MIN_TUN_PKT_LEN 65U
/* hns3_pci_tbl - PCI Device ID Table
*
l4.tcp->doff);
break;
case IPPROTO_UDP:
- if (hns3_tunnel_csum_bug(skb))
- return skb_checksum_help(skb);
+ if (hns3_tunnel_csum_bug(skb)) {
+ int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
+
+ return ret ? ret : skb_checksum_help(skb);
+ }
hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
goto out_with_desc_cb;
if (!HNAE3_IS_TX_RING(ring)) {
- hns3_alloc_page_pool(ring);
+ if (page_pool_enabled)
+ hns3_alloc_page_pool(ring);
ret = hns3_alloc_ring_buffers(ring);
if (ret)
}
bd_num = le32_to_cpu(req->bd_num);
+ if (!bd_num) {
+ dev_err(&hdev->pdev->dev, "imp statistics bd number is 0!\n");
+ return -EINVAL;
+ }
desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
if (!desc_src)
return;
}
- dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%u), queue_id(%u)\n",
+ dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vport(%u), queue_id(%u)\n",
vf_id, q_id);
if (vf_id) {
if (vf_id >= hdev->num_alloc_vport) {
- dev_err(dev, "invalid vf id(%u)\n", vf_id);
+ dev_err(dev, "invalid vport(%u)\n", vf_id);
return;
}
ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]);
if (ret)
- dev_err(dev, "inform reset to vf(%u) failed %d!\n",
- hdev->vport->vport_id, ret);
+ dev_err(dev, "inform reset to vport(%u) failed %d!\n",
+ vf_id, ret);
} else {
set_bit(HNAE3_FUNC_RESET, reset_requests);
}
static int hclge_configure(struct hclge_dev *hdev)
{
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ const struct cpumask *cpumask = cpu_online_mask;
struct hclge_cfg cfg;
unsigned int i;
- int ret;
+ int node, ret;
ret = hclge_get_cfg(hdev, &cfg);
if (ret)
hclge_init_kdump_kernel_config(hdev);
- /* Set the init affinity based on pci func number */
- i = cpumask_weight(cpumask_of_node(dev_to_node(&hdev->pdev->dev)));
- i = i ? PCI_FUNC(hdev->pdev->devfn) % i : 0;
- cpumask_set_cpu(cpumask_local_spread(i, dev_to_node(&hdev->pdev->dev)),
- &hdev->affinity_mask);
+ /* Set the affinity based on numa node */
+ node = dev_to_node(&hdev->pdev->dev);
+ if (node != NUMA_NO_NODE)
+ cpumask = cpumask_of_node(node);
+
+ cpumask_copy(&hdev->affinity_mask, cpumask);
return ret;
}
if (ret) {
dev_err(&hdev->pdev->dev,
"set vf(%u) rst failed %d!\n",
- vport->vport_id, ret);
+ vport->vport_id - HCLGE_VF_VPORT_START_NUM,
+ ret);
return ret;
}
if (ret)
dev_warn(&hdev->pdev->dev,
"inform reset to vf(%u) failed %d!\n",
- vport->vport_id, ret);
+ vport->vport_id - HCLGE_VF_VPORT_START_NUM,
+ ret);
}
return 0;
return 0;
}
+static int hclge_parse_rss_hfunc(struct hclge_vport *vport, const u8 hfunc,
+ u8 *hash_algo)
+{
+ switch (hfunc) {
+ case ETH_RSS_HASH_TOP:
+ *hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
+ return 0;
+ case ETH_RSS_HASH_XOR:
+ *hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
+ return 0;
+ case ETH_RSS_HASH_NO_CHANGE:
+ *hash_algo = vport->rss_algo;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
const u8 *key, const u8 hfunc)
{
u8 hash_algo;
int ret, i;
+ ret = hclge_parse_rss_hfunc(vport, hfunc, &hash_algo);
+ if (ret) {
+ dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
+ return ret;
+ }
+
/* Set the RSS Hash Key if specififed by the user */
if (key) {
- switch (hfunc) {
- case ETH_RSS_HASH_TOP:
- hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
- break;
- case ETH_RSS_HASH_XOR:
- hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
- break;
- case ETH_RSS_HASH_NO_CHANGE:
- hash_algo = vport->rss_algo;
- break;
- default:
- return -EINVAL;
- }
-
ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
if (ret)
return ret;
/* Update the shadow RSS key with user specified qids */
memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
- vport->rss_algo = hash_algo;
+ } else {
+ ret = hclge_set_rss_algo_key(hdev, hash_algo,
+ vport->rss_hash_key);
+ if (ret)
+ return ret;
}
+ vport->rss_algo = hash_algo;
/* Update the shadow RSS table with user specified qids */
for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie);
u16 tqps;
+ /* To keep consistent with user's configuration, minus 1 when
+ * printing 'vf', because vf id from ethtool is added 1 for vf.
+ */
if (vf > hdev->num_req_vfs) {
dev_err(&hdev->pdev->dev,
- "Error: vf id (%u) > max vf num (%u)\n",
- vf, hdev->num_req_vfs);
+ "Error: vf id (%u) should be less than %u\n",
+ vf - 1, hdev->num_req_vfs);
return -EINVAL;
}
hclge_clear_arfs_rules(hdev);
spin_unlock_bh(&hdev->fd_rule_lock);
- /* If it is not PF reset, the firmware will disable the MAC,
+ /* If it is not PF reset or FLR, the firmware will disable the MAC,
* so it only need to stop phy here.
*/
if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
- hdev->reset_type != HNAE3_FUNC_RESET) {
+ hdev->reset_type != HNAE3_FUNC_RESET &&
+ hdev->reset_type != HNAE3_FLR_RESET) {
hclge_mac_stop_phy(hdev);
hclge_update_link_status(hdev);
return;
if (is_kill && !vlan_id)
return 0;
+ if (vlan_id >= VLAN_N_VID)
+ return -EINVAL;
+
ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
if (ret) {
dev_err(&hdev->pdev->dev,
return 0;
}
-static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
+static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id,
+ u8 *reset_status)
{
struct hclge_reset_tqp_queue_cmd *req;
struct hclge_desc desc;
return ret;
}
- return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
+ *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
+
+ return 0;
}
u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
u16 reset_try_times = 0;
- int reset_status;
+ u8 reset_status;
u16 queue_gid;
int ret;
u16 i;
}
while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
- reset_status = hclge_get_reset_status(hdev, queue_gid);
+ ret = hclge_get_reset_status(hdev, queue_gid,
+ &reset_status);
+ if (ret)
+ return ret;
+
if (reset_status)
break;
struct hclge_vport *vport = &hdev->vport[i];
int ret;
- /* Send cmd to clear VF's FUNC_RST_ING */
+ /* Send cmd to clear vport's FUNC_RST_ING */
ret = hclge_set_vf_rst(hdev, vport->vport_id, false);
if (ret)
dev_warn(&hdev->pdev->dev,
- "clear vf(%u) rst failed %d!\n",
+ "clear vport(%u) rst failed %d!\n",
vport->vport_id, ret);
}
}
struct hclge_dev *hdev = vport->back;
dev_warn(&hdev->pdev->dev, "PF received VF reset request from VF %u!",
- vport->vport_id);
+ vport->vport_id - HCLGE_VF_VPORT_START_NUM);
return hclge_func_reset_cmd(hdev, vport->vport_id);
}
struct hclge_mbx_vf_to_pf_cmd *mbx_req,
struct hclge_respond_to_vf_msg *resp_msg)
{
+ struct hnae3_handle *handle = &vport->nic;
+ struct hclge_dev *hdev = vport->back;
u16 queue_id, qid_in_pf;
memcpy(&queue_id, mbx_req->msg.data, sizeof(queue_id));
+ if (queue_id >= handle->kinfo.num_tqps) {
+ dev_err(&hdev->pdev->dev, "Invalid queue id(%u) from VF %u\n",
+ queue_id, mbx_req->mbx_src_vfid);
+ return;
+ }
+
qid_in_pf = hclge_covert_handle_qid_global(&vport->nic, queue_id);
memcpy(resp_msg->data, &qid_in_pf, sizeof(qid_in_pf));
resp_msg->len = sizeof(qid_in_pf);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
- "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n",
+ "vport%u, qs%u failed to set tx_rate:%d, ret=%d\n",
vport->vport_id, shap_cfg_cmd->qs_id,
max_tx_rate, ret);
return ret;
return 0;
}
+static int hclgevf_parse_rss_hfunc(struct hclgevf_dev *hdev, const u8 hfunc,
+ u8 *hash_algo)
+{
+ switch (hfunc) {
+ case ETH_RSS_HASH_TOP:
+ *hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
+ return 0;
+ case ETH_RSS_HASH_XOR:
+ *hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
+ return 0;
+ case ETH_RSS_HASH_NO_CHANGE:
+ *hash_algo = hdev->rss_cfg.hash_algo;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
const u8 *key, const u8 hfunc)
{
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
+ u8 hash_algo;
int ret, i;
if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ ret = hclgevf_parse_rss_hfunc(hdev, hfunc, &hash_algo);
+ if (ret)
+ return ret;
+
/* Set the RSS Hash Key if specififed by the user */
if (key) {
- switch (hfunc) {
- case ETH_RSS_HASH_TOP:
- rss_cfg->hash_algo =
- HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
- break;
- case ETH_RSS_HASH_XOR:
- rss_cfg->hash_algo =
- HCLGEVF_RSS_HASH_ALGO_SIMPLE;
- break;
- case ETH_RSS_HASH_NO_CHANGE:
- break;
- default:
- return -EINVAL;
- }
-
- ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
- key);
- if (ret)
+ ret = hclgevf_set_rss_algo_key(hdev, hash_algo, key);
+ if (ret) {
+ dev_err(&hdev->pdev->dev,
+ "invalid hfunc type %u\n", hfunc);
return ret;
+ }
/* Update the shadow RSS key with user specified qids */
memcpy(rss_cfg->rss_hash_key, key,
HCLGEVF_RSS_KEY_SIZE);
+ } else {
+ ret = hclgevf_set_rss_algo_key(hdev, hash_algo,
+ rss_cfg->rss_hash_key);
+ if (ret)
+ return ret;
}
+ rss_cfg->hash_algo = hash_algo;
}
/* update the shadow RSS table with user specified qids */
hclgevf_enable_vector(&hdev->misc_vector, false);
event_cause = hclgevf_check_evt_cause(hdev, &clearval);
+ if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
+ hclgevf_clear_event_cause(hdev, clearval);
switch (event_cause) {
case HCLGEVF_VECTOR0_EVENT_RST:
break;
}
- if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
- hclgevf_clear_event_cause(hdev, clearval);
+ if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
hclgevf_enable_vector(&hdev->misc_vector, true);
- }
return IRQ_HANDLED;
}
err = -ENODEV;
goto out;
}
- memcpy(eth_addr, (void *) 0xfffc1f2c, ETH_ALEN); /* YUCK! Get addr from NOVRAM */
+ memcpy(eth_addr, absolute_pointer(0xfffc1f2c), ETH_ALEN); /* YUCK! Get addr from NOVRAM */
dev->base_addr = MVME_I596_BASE;
dev->irq = (unsigned) MVME16x_IRQ_I596;
goto found;
return 0;
}
+ if (adapter->failover_pending) {
+ adapter->init_done_rc = -EAGAIN;
+ netdev_dbg(netdev, "Failover pending, ignoring login response\n");
+ complete(&adapter->init_done);
+ /* login response buffer will be released on reset */
+ return 0;
+ }
+
+ if (adapter->failover_pending) {
+ adapter->init_done_rc = -EAGAIN;
+ netdev_dbg(netdev, "Failover pending, ignoring login response\n");
+ complete(&adapter->init_done);
+ /* login response buffer will be released on reset */
+ return 0;
+ }
+
netdev->mtu = adapter->req_mtu - ETH_HLEN;
netdev_dbg(adapter->netdev, "Login Response Buffer:\n");
tristate "Intel(R) Ethernet Controller I225-LM/I225-V support"
default n
depends on PCI
+ depends on PTP_1588_CLOCK_OPTIONAL
help
This driver supports Intel(R) Ethernet Controller I225-LM/I225-V
family of adapters.
{
if (pf->hw.func_caps.common_cap.rdma && pf->num_rdma_msix) {
set_bit(ICE_FLAG_RDMA_ENA, pf->flags);
+ set_bit(ICE_FLAG_AUX_ENA, pf->flags);
ice_plug_aux_dev(pf);
}
}
{
ice_unplug_aux_dev(pf);
clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);
+ clear_bit(ICE_FLAG_AUX_ENA, pf->flags);
}
#endif /* _ICE_H_ */
struct auxiliary_device *adev;
int ret;
+ /* if this PF doesn't support a technology that requires auxiliary
+ * devices, then gracefully exit
+ */
+ if (!ice_is_aux_ena(pf))
+ return 0;
+
iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
if (!iadev)
return -ENOMEM;
if (pci_using_dac)
netdev->features |= NETIF_F_HIGHDMA;
- netdev->vlan_features |= netdev->features;
+ netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
+ netdev->mpls_features |= NETIF_F_HW_CSUM;
+ netdev->hw_enc_features |= netdev->vlan_features;
/* MTU range: 68 - 9216 */
netdev->min_mtu = ETH_MIN_MTU;
int hash;
int i;
+ if (rhashtable_lookup(ð->flow_table, &f->cookie, mtk_flow_ht_params))
+ return -EEXIST;
+
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) {
struct flow_match_meta match;
int nhoff = skb_network_offset(skb);
int ret = 0;
+ if (skb->encapsulation)
+ return -EPROTONOSUPPORT;
+
if (skb->protocol != htons(ETH_P_IP))
return -EPROTONOSUPPORT;
if (!netif_carrier_ok(dev)) {
if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
if (priv->port_state.link_state) {
- priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
netif_carrier_on(dev);
en_dbg(LINK, priv, "Link Up\n");
}
mutex_unlock(&mdev->state_lock);
}
-static void mlx4_en_linkstate(struct work_struct *work)
+static void mlx4_en_linkstate(struct mlx4_en_priv *priv)
+{
+ struct mlx4_en_port_state *port_state = &priv->port_state;
+ struct mlx4_en_dev *mdev = priv->mdev;
+ struct net_device *dev = priv->dev;
+ bool up;
+
+ if (mlx4_en_QUERY_PORT(mdev, priv->port))
+ port_state->link_state = MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN;
+
+ up = port_state->link_state == MLX4_PORT_STATE_DEV_EVENT_PORT_UP;
+ if (up == netif_carrier_ok(dev))
+ netif_carrier_event(dev);
+ if (!up) {
+ en_info(priv, "Link Down\n");
+ netif_carrier_off(dev);
+ } else {
+ en_info(priv, "Link Up\n");
+ netif_carrier_on(dev);
+ }
+}
+
+static void mlx4_en_linkstate_work(struct work_struct *work)
{
struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
linkstate_task);
struct mlx4_en_dev *mdev = priv->mdev;
- int linkstate = priv->link_state;
mutex_lock(&mdev->state_lock);
- /* If observable port state changed set carrier state and
- * report to system log */
- if (priv->last_link_state != linkstate) {
- if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
- en_info(priv, "Link Down\n");
- netif_carrier_off(priv->dev);
- } else {
- en_info(priv, "Link Up\n");
- netif_carrier_on(priv->dev);
- }
- }
- priv->last_link_state = linkstate;
+ mlx4_en_linkstate(priv);
mutex_unlock(&mdev->state_lock);
}
mlx4_en_clear_stats(dev);
err = mlx4_en_start_port(dev);
- if (err)
+ if (err) {
en_err(priv, "Failed starting port:%d\n", priv->port);
-
+ goto out;
+ }
+ mlx4_en_linkstate(priv);
out:
mutex_unlock(&mdev->state_lock);
return err;
spin_lock_init(&priv->stats_lock);
INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
INIT_WORK(&priv->restart_task, mlx4_en_restart);
- INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
+ INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate_work);
INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
#ifdef CONFIG_RFS_ACCEL
struct mlx4_hwq_resources res;
int link_state;
- int last_link_state;
bool port_up;
int port;
int registered;
static int mlx5_devlink_rdma_param_register(struct devlink *devlink)
{
- struct mlx5_core_dev *dev = devlink_priv(devlink);
union devlink_param_value value;
int err;
- if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND) || MLX5_ESWITCH_MANAGER(dev))
+ if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
return 0;
err = devlink_param_register(devlink, &enable_rdma_param);
static void mlx5_devlink_rdma_param_unregister(struct devlink *devlink)
{
- struct mlx5_core_dev *dev = devlink_priv(devlink);
-
- if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND) || MLX5_ESWITCH_MANAGER(dev))
+ if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
return;
devlink_param_unpublish(devlink, &enable_rdma_param);
err = mlx5_core_alloc_pd(dev, &tracer->buff.pdn);
if (err) {
mlx5_core_warn(dev, "FWTracer: Failed to allocate PD %d\n", err);
- return err;
+ goto err_cancel_work;
}
err = mlx5_fw_tracer_create_mkey(tracer);
mlx5_core_destroy_mkey(dev, &tracer->buff.mkey);
err_dealloc_pd:
mlx5_core_dealloc_pd(dev, tracer->buff.pdn);
+err_cancel_work:
cancel_work_sync(&tracer->read_fw_strings_work);
return err;
}
int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
-int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
+int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
u16 vid);
u16 vport_num, esw_owner_vhca_id;
struct netlink_ext_ack *extack;
int ifindex = upper->ifindex;
- int err;
+ int err = 0;
if (!netif_is_bridge_master(upper))
return 0;
struct netlink_ext_ack *extack = switchdev_notifier_info_to_extack(&port_attr_info->info);
const struct switchdev_attr *attr = port_attr_info->attr;
u16 vport_num, esw_owner_vhca_id;
- int err;
+ int err = 0;
if (!mlx5_esw_bridge_lower_rep_vport_num_vhca_id_get(dev, br_offloads->esw, &vport_num,
&esw_owner_vhca_id))
{
struct mlx5e_rep_indr_block_priv *cb_priv;
- /* All callback list access should be protected by RTNL. */
- ASSERT_RTNL();
-
list_for_each_entry(cb_priv,
&rpriv->uplink_priv.tc_indr_block_priv_list,
list)
if (res->features & MLX5E_RX_RES_FEATURE_PTP) {
u32 rqn;
- if (mlx5e_channels_get_ptp_rqn(chs, &rqn))
+ if (!mlx5e_channels_get_ptp_rqn(chs, &rqn))
rqn = res->drop_rqn;
err = mlx5e_rqt_redirect_direct(&res->ptp.rqt, rqn);
return set_pflag_cqe_based_moder(netdev, enable, true);
}
-int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
+int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter)
{
bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
struct mlx5e_params new_params;
if (curr_val == new_val)
return 0;
- if (new_val && !priv->profile->rx_ptp_support &&
- priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
+ if (new_val && !priv->profile->rx_ptp_support && rx_filter) {
netdev_err(priv->netdev,
"Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");
return -EINVAL;
new_params = priv->channels.params;
MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
- if (priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE)
+ if (rx_filter)
new_params.ptp_rx = new_val;
if (new_params.ptp_rx == priv->channels.params.ptp_rx)
{
struct mlx5e_priv *priv = netdev_priv(netdev);
struct mlx5_core_dev *mdev = priv->mdev;
+ bool rx_filter;
int err;
if (!MLX5_CAP_GEN(mdev, cqe_compression))
return -EOPNOTSUPP;
- err = mlx5e_modify_rx_cqe_compression_locked(priv, enable);
+ rx_filter = priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE;
+ err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter);
if (err)
return err;
if (!rx_filter)
/* Reset CQE compression to Admin default */
- return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
+ return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
return 0;
/* Disable CQE compression */
netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
- err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
+ err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
if (err)
netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
curr_match = kmalloc(sizeof(*curr_match), GFP_ATOMIC);
if (!curr_match) {
+ rcu_read_unlock();
free_match_list(match_head, ft_locked);
- err = -ENOMEM;
- goto out;
+ return -ENOMEM;
}
curr_match->g = g;
list_add_tail(&curr_match->list, &match_head->list);
}
-out:
rcu_read_unlock();
return err;
}
struct mlx5_core_dev *dev1;
struct mlx5_lag *ldev;
+ ldev = mlx5_lag_dev(dev);
+ if (!ldev)
+ return;
+
mlx5_dev_list_lock();
- ldev = mlx5_lag_dev(dev);
dev0 = ldev->pf[MLX5_LAG_P1].dev;
dev1 = ldev->pf[MLX5_LAG_P2].dev;
{
struct mlx5_lag *ldev;
- mlx5_dev_list_lock();
ldev = mlx5_lag_dev(dev);
+ if (!ldev)
+ return;
+
+ mlx5_dev_list_lock();
ldev->mode_changes_in_progress--;
mlx5_dev_list_unlock();
mlx5_queue_bond_work(ldev, 0);
err = mlxbf_gige_clean_port(priv);
if (err)
goto free_irqs;
+
+ /* Clear driver's valid_polarity to match hardware,
+ * since the above call to clean_port() resets the
+ * receive polarity used by hardware.
+ */
+ priv->valid_polarity = 0;
+
err = mlxbf_gige_rx_init(priv);
if (err)
goto free_irqs;
int err;
u16 i;
- dma_buf = kzalloc(sizeof(*dma_buf) +
- q_depth * sizeof(struct hwc_work_request),
- GFP_KERNEL);
+ dma_buf = kzalloc(struct_size(dma_buf, reqs, q_depth), GFP_KERNEL);
if (!dma_buf)
return -ENOMEM;
ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
- /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
- * reset
- */
- ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
- DEV_CLOCK_CFG);
-
- /* No PFC */
- ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
- ANA_PFC_PFC_CFG, port);
-
/* Core: Enable port for frame transfer */
ocelot_fields_write(ocelot, port,
QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
return mask;
}
-static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot,
+static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port,
struct net_device *bridge)
{
+ struct ocelot_port *ocelot_port = ocelot->ports[src_port];
u32 mask = 0;
int port;
+ if (!ocelot_port || ocelot_port->bridge != bridge ||
+ ocelot_port->stp_state != BR_STATE_FORWARDING)
+ return 0;
+
for (port = 0; port < ocelot->num_phys_ports; port++) {
- struct ocelot_port *ocelot_port = ocelot->ports[port];
+ ocelot_port = ocelot->ports[port];
if (!ocelot_port)
continue;
struct net_device *bridge = ocelot_port->bridge;
struct net_device *bond = ocelot_port->bond;
- mask = ocelot_get_bridge_fwd_mask(ocelot, bridge);
+ mask = ocelot_get_bridge_fwd_mask(ocelot, port, bridge);
mask |= cpu_fwd_mask;
mask &= ~BIT(port);
if (bond) {
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright 2020-2021 NXP Semiconductors
+/* Copyright 2020-2021 NXP
*/
#include <net/devlink.h>
#include "ocelot.h"
/* Microsemi Ocelot Switch driver
*
* Copyright (c) 2017, 2019 Microsemi Corporation
- * Copyright 2020-2021 NXP Semiconductors
+ * Copyright 2020-2021 NXP
*/
#include <linux/if_bridge.h>
* mscc_ocelot_switch_lib.
*
* Copyright (c) 2017, 2019 Microsemi Corporation
- * Copyright 2020-2021 NXP Semiconductors
+ * Copyright 2020-2021 NXP
*/
#include <linux/if_bridge.h>
struct nfp_flower_indr_block_cb_priv *cb_priv;
struct nfp_flower_priv *priv = app->priv;
- /* All callback list access should be protected by RTNL. */
- ASSERT_RTNL();
-
list_for_each_entry(cb_priv, &priv->indr_block_cb_priv, list)
if (cb_priv->netdev == netdev)
return cb_priv;
prev_weight = weight;
while (weight) {
+ /* If the HW device is during recovery, all resources are
+ * immediately reset without receiving a per-cid indication
+ * from HW. In this case we don't expect the cid_map to be
+ * cleared.
+ */
+ if (p_hwfn->cdev->recov_in_prog)
+ return 0;
+
msleep(QED_IWARP_MAX_CID_CLEAN_TIME);
weight = bitmap_weight(bmap->bitmap, bmap->max_count);
struct qed_nvm_image_att *p_image_att)
{
enum nvm_image_type type;
+ int rc;
u32 i;
/* Translate image_id into MFW definitions */
return -EINVAL;
}
- qed_mcp_nvm_info_populate(p_hwfn);
+ rc = qed_mcp_nvm_info_populate(p_hwfn);
+ if (rc)
+ return rc;
+
for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
if (type == p_hwfn->nvm_info.image_att[i].image_type)
break;
* Beyond the added delay we clear the bitmap anyway.
*/
while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) {
+ /* If the HW device is during recovery, all resources are
+ * immediately reset without receiving a per-cid indication
+ * from HW. In this case we don't expect the cid bitmap to be
+ * cleared.
+ */
+ if (p_hwfn->cdev->recov_in_prog)
+ return;
+
msleep(100);
if (wait_count++ > 20) {
DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n");
struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
const struct firmware *fw = fw_info->fw;
u32 dest, *p_cache, *temp;
- int i, ret = -EIO;
__le32 *temp_le;
u8 data[16];
size_t size;
+ int i, ret;
u64 addr;
temp = vzalloc(fw->size);
#define PHY_ST 0x8A /* PHY status register */
#define MAC_SM 0xAC /* MAC status machine */
#define MAC_SM_RST 0x0002 /* MAC status machine reset */
+#define MD_CSC 0xb6 /* MDC speed control register */
+#define MD_CSC_DEFAULT 0x0030
#define MAC_ID 0xBE /* Identifier register */
#define TX_DCNT 0x80 /* TX descriptor count */
{
void __iomem *ioaddr = lp->base;
int limit = MAC_DEF_TIMEOUT;
- u16 cmd;
+ u16 cmd, md_csc;
+ md_csc = ioread16(ioaddr + MD_CSC);
iowrite16(MAC_RST, ioaddr + MCR1);
while (limit--) {
cmd = ioread16(ioaddr + MCR1);
iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
iowrite16(0, ioaddr + MAC_SM);
mdelay(5);
+
+ /* Restore MDIO clock frequency */
+ if (md_csc != MD_CSC_DEFAULT)
+ iowrite16(md_csc, ioaddr + MD_CSC);
}
static void r6040_init_mac_regs(struct net_device *dev)
* We need a channel per event queue, plus a VI per tx queue.
* This may be more pessimistic than it needs to be.
*/
- if (n_channels + n_xdp_ev > max_channels) {
- netif_err(efx, drv, efx->net_dev,
- "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
- n_xdp_ev, n_channels, max_channels);
- netif_err(efx, drv, efx->net_dev,
- "XDP_TX and XDP_REDIRECT will not work on this interface");
- efx->n_xdp_channels = 0;
- efx->xdp_tx_per_channel = 0;
- efx->xdp_tx_queue_count = 0;
+ if (n_channels >= max_channels) {
+ efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED;
+ netif_warn(efx, drv, efx->net_dev,
+ "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
+ n_xdp_ev, n_channels, max_channels);
+ netif_warn(efx, drv, efx->net_dev,
+ "XDP_TX and XDP_REDIRECT might decrease device's performance\n");
} else if (n_channels + n_xdp_tx > efx->max_vis) {
- netif_err(efx, drv, efx->net_dev,
- "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n",
- n_xdp_tx, n_channels, efx->max_vis);
- netif_err(efx, drv, efx->net_dev,
- "XDP_TX and XDP_REDIRECT will not work on this interface");
- efx->n_xdp_channels = 0;
- efx->xdp_tx_per_channel = 0;
- efx->xdp_tx_queue_count = 0;
+ efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED;
+ netif_warn(efx, drv, efx->net_dev,
+ "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n",
+ n_xdp_tx, n_channels, efx->max_vis);
+ netif_warn(efx, drv, efx->net_dev,
+ "XDP_TX and XDP_REDIRECT might decrease device's performance\n");
+ } else if (n_channels + n_xdp_ev > max_channels) {
+ efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_SHARED;
+ netif_warn(efx, drv, efx->net_dev,
+ "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
+ n_xdp_ev, n_channels, max_channels);
+
+ n_xdp_ev = max_channels - n_channels;
+ netif_warn(efx, drv, efx->net_dev,
+ "XDP_TX and XDP_REDIRECT will work with reduced performance (%d cpus/tx_queue)\n",
+ DIV_ROUND_UP(n_xdp_tx, tx_per_ev * n_xdp_ev));
} else {
+ efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_DEDICATED;
+ }
+
+ if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_BORROWED) {
efx->n_xdp_channels = n_xdp_ev;
efx->xdp_tx_per_channel = tx_per_ev;
efx->xdp_tx_queue_count = n_xdp_tx;
n_channels += n_xdp_ev;
netif_dbg(efx, drv, efx->net_dev,
"Allocating %d TX and %d event queues for XDP\n",
- n_xdp_tx, n_xdp_ev);
+ n_xdp_ev * tx_per_ev, n_xdp_ev);
+ } else {
+ efx->n_xdp_channels = 0;
+ efx->xdp_tx_per_channel = 0;
+ efx->xdp_tx_queue_count = n_xdp_tx;
}
if (vec_count < n_channels) {
goto out;
}
+static inline int
+efx_set_xdp_tx_queue(struct efx_nic *efx, int xdp_queue_number,
+ struct efx_tx_queue *tx_queue)
+{
+ if (xdp_queue_number >= efx->xdp_tx_queue_count)
+ return -EINVAL;
+
+ netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is XDP %u, HW %u\n",
+ tx_queue->channel->channel, tx_queue->label,
+ xdp_queue_number, tx_queue->queue);
+ efx->xdp_tx_queues[xdp_queue_number] = tx_queue;
+ return 0;
+}
+
int efx_set_channels(struct efx_nic *efx)
{
struct efx_tx_queue *tx_queue;
if (efx_channel_is_xdp_tx(channel)) {
efx_for_each_channel_tx_queue(tx_queue, channel) {
tx_queue->queue = next_queue++;
-
- /* We may have a few left-over XDP TX
- * queues owing to xdp_tx_queue_count
- * not dividing evenly by EFX_MAX_TXQ_PER_CHANNEL.
- * We still allocate and probe those
- * TXQs, but never use them.
- */
- if (xdp_queue_number < efx->xdp_tx_queue_count) {
- netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is XDP %u, HW %u\n",
- channel->channel, tx_queue->label,
- xdp_queue_number, tx_queue->queue);
- efx->xdp_tx_queues[xdp_queue_number] = tx_queue;
+ rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue);
+ if (rc == 0)
xdp_queue_number++;
- }
}
} else {
efx_for_each_channel_tx_queue(tx_queue, channel) {
channel->channel, tx_queue->label,
tx_queue->queue);
}
+
+ /* If XDP is borrowing queues from net stack, it must use the queue
+ * with no csum offload, which is the first one of the channel
+ * (note: channel->tx_queue_by_type is not initialized yet)
+ */
+ if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) {
+ tx_queue = &channel->tx_queue[0];
+ rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue);
+ if (rc == 0)
+ xdp_queue_number++;
+ }
}
}
}
- WARN_ON(xdp_queue_number != efx->xdp_tx_queue_count);
+ WARN_ON(efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_DEDICATED &&
+ xdp_queue_number != efx->xdp_tx_queue_count);
+ WARN_ON(efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED &&
+ xdp_queue_number > efx->xdp_tx_queue_count);
+
+ /* If we have more CPUs than assigned XDP TX queues, assign the already
+ * existing queues to the exceeding CPUs
+ */
+ next_queue = 0;
+ while (xdp_queue_number < efx->xdp_tx_queue_count) {
+ tx_queue = efx->xdp_tx_queues[next_queue++];
+ rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue);
+ if (rc == 0)
+ xdp_queue_number++;
+ }
rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
if (rc)
#define EFX_RPS_MAX_IN_FLIGHT 8
#endif /* CONFIG_RFS_ACCEL */
+enum efx_xdp_tx_queues_mode {
+ EFX_XDP_TX_QUEUES_DEDICATED, /* one queue per core, locking not needed */
+ EFX_XDP_TX_QUEUES_SHARED, /* each queue used by more than 1 core */
+ EFX_XDP_TX_QUEUES_BORROWED /* queues borrowed from net stack */
+};
+
/**
* struct efx_nic - an Efx NIC
* @name: Device name (net device name or bus id before net device registered)
* should be allocated for this NIC
* @xdp_tx_queue_count: Number of entries in %xdp_tx_queues.
* @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
+ * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
* @rxq_entries: Size of receive queues requested by user.
* @txq_entries: Size of transmit queues requested by user.
* @txq_stop_thresh: TX queue fill level at or above which we stop it.
unsigned int xdp_tx_queue_count;
struct efx_tx_queue **xdp_tx_queues;
+ enum efx_xdp_tx_queues_mode xdp_txq_queues_mode;
unsigned rxq_entries;
unsigned txq_entries;
unsigned int len;
int space;
int cpu;
- int i;
+ int i = 0;
- cpu = raw_smp_processor_id();
+ if (unlikely(n && !xdpfs))
+ return -EINVAL;
+ if (unlikely(!n))
+ return 0;
- if (!efx->xdp_tx_queue_count ||
- unlikely(cpu >= efx->xdp_tx_queue_count))
+ cpu = raw_smp_processor_id();
+ if (unlikely(cpu >= efx->xdp_tx_queue_count))
return -EINVAL;
tx_queue = efx->xdp_tx_queues[cpu];
if (unlikely(!tx_queue))
return -EINVAL;
- if (unlikely(n && !xdpfs))
- return -EINVAL;
+ if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED)
+ HARD_TX_LOCK(efx->net_dev, tx_queue->core_txq, cpu);
- if (!n)
- return 0;
+ /* If we're borrowing net stack queues we have to handle stop-restart
+ * or we might block the queue and it will be considered as frozen
+ */
+ if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) {
+ if (netif_tx_queue_stopped(tx_queue->core_txq))
+ goto unlock;
+ efx_tx_maybe_stop_queue(tx_queue);
+ }
/* Check for available space. We should never need multiple
* descriptors per frame.
if (flush && i > 0)
efx_nic_push_buffers(tx_queue);
+unlock:
+ if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED)
+ HARD_TX_UNLOCK(efx->net_dev, tx_queue->core_txq);
+
return i == 0 ? -EIO : i;
}
priv->clk_csr = STMMAC_CSR_100_150M;
else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
priv->clk_csr = STMMAC_CSR_150_250M;
- else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
+ else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
priv->clk_csr = STMMAC_CSR_250_300M;
}
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
u32 chan;
- int ret;
if (!ndev || !netif_running(ndev))
return 0;
} else {
stmmac_mac_set(priv, priv->ioaddr, false);
pinctrl_pm_select_sleep_state(priv->device);
- /* Disable clock in case of PWM is off */
- clk_disable_unprepare(priv->plat->clk_ptp_ref);
- ret = pm_runtime_force_suspend(dev);
- if (ret) {
- mutex_unlock(&priv->lock);
- return ret;
- }
}
mutex_unlock(&priv->lock);
priv->irq_wake = 0;
} else {
pinctrl_pm_select_default_state(priv->device);
- /* enable the clk previously disabled */
- ret = pm_runtime_force_resume(dev);
- if (ret)
- return ret;
- if (priv->plat->clk_ptp_ref)
- clk_prepare_enable(priv->plat->clk_ptp_ref);
/* reset the phy so that it's ready */
if (priv->mii)
stmmac_mdio_reset(priv->mii);
*******************************************************************************/
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
return stmmac_bus_clks_config(priv, true);
}
+static int __maybe_unused stmmac_pltfr_noirq_suspend(struct device *dev)
+{
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct stmmac_priv *priv = netdev_priv(ndev);
+ int ret;
+
+ if (!netif_running(ndev))
+ return 0;
+
+ if (!device_may_wakeup(priv->device) || !priv->plat->pmt) {
+ /* Disable clock in case of PWM is off */
+ clk_disable_unprepare(priv->plat->clk_ptp_ref);
+
+ ret = pm_runtime_force_suspend(dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __maybe_unused stmmac_pltfr_noirq_resume(struct device *dev)
+{
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct stmmac_priv *priv = netdev_priv(ndev);
+ int ret;
+
+ if (!netif_running(ndev))
+ return 0;
+
+ if (!device_may_wakeup(priv->device) || !priv->plat->pmt) {
+ /* enable the clk previously disabled */
+ ret = pm_runtime_force_resume(dev);
+ if (ret)
+ return ret;
+
+ clk_prepare_enable(priv->plat->clk_ptp_ref);
+ }
+
+ return 0;
+}
+
const struct dev_pm_ops stmmac_pltfr_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(stmmac_pltfr_suspend, stmmac_pltfr_resume)
SET_RUNTIME_PM_OPS(stmmac_runtime_suspend, stmmac_runtime_resume, NULL)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(stmmac_pltfr_noirq_suspend, stmmac_pltfr_noirq_resume)
};
EXPORT_SYMBOL_GPL(stmmac_pltfr_pm_ops);
#define SIXP_DAMA_OFF 0
/* default level 2 parameters */
-#define SIXP_TXDELAY (HZ/4) /* in 1 s */
+#define SIXP_TXDELAY 25 /* 250 ms */
#define SIXP_PERSIST 50 /* in 256ths */
-#define SIXP_SLOTTIME (HZ/10) /* in 1 s */
+#define SIXP_SLOTTIME 10 /* 100 ms */
#define SIXP_INIT_RESYNC_TIMEOUT (3*HZ/2) /* in 1 s */
#define SIXP_RESYNC_TIMEOUT 5*HZ /* in 1 s */
flags = claim_dma_lock();
set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
set_dma_addr(priv->param.dma,
- (int) priv->tx_buf[priv->tx_tail] + n);
+ virt_to_bus(priv->tx_buf[priv->tx_tail]) + n);
set_dma_count(priv->param.dma,
priv->tx_len[priv->tx_tail] - n);
release_dma_lock(flags);
flags = claim_dma_lock();
set_dma_mode(priv->param.dma, DMA_MODE_READ);
set_dma_addr(priv->param.dma,
- (int) priv->rx_buf[priv->rx_head]);
+ virt_to_bus(priv->rx_buf[priv->rx_head]));
set_dma_count(priv->param.dma, BUF_SIZE);
release_dma_lock(flags);
enable_dma(priv->param.dma);
if (priv->param.dma >= 0) {
flags = claim_dma_lock();
set_dma_addr(priv->param.dma,
- (int) priv->rx_buf[priv->rx_head]);
+ virt_to_bus(priv->rx_buf[priv->rx_head]));
set_dma_count(priv->param.dma, BUF_SIZE);
release_dma_lock(flags);
} else {
* table region determines the number of entries it has.
*/
if (filter) {
- count = hweight32(ipa->filter_map);
+ /* Include one extra "slot" to hold the filter map itself */
+ count = 1 + hweight32(ipa->filter_map);
hash_count = hash_mem->size ? count : 0;
} else {
count = mem->size / sizeof(__le64);
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2021 NXP Semiconductors
+/* Copyright 2021 NXP
*/
#include <linux/pcs/pcs-xpcs.h>
#include "pcs-xpcs.h"
#ifndef HAVE_DP83640_REGISTERS
#define HAVE_DP83640_REGISTERS
-#define PAGE0 0x0000
+/* #define PAGE0 0x0000 */
#define PHYCR2 0x001c /* PHY Control Register 2 */
#define PAGE4 0x0004
return 0;
}
+static void mdio_shutdown(struct device *dev)
+{
+ struct mdio_device *mdiodev = to_mdio_device(dev);
+ struct device_driver *drv = mdiodev->dev.driver;
+ struct mdio_driver *mdiodrv = to_mdio_driver(drv);
+
+ if (mdiodrv->shutdown)
+ mdiodrv->shutdown(mdiodev);
+}
+
/**
* mdio_driver_register - register an mdio_driver with the MDIO layer
* @drv: new mdio_driver to register
mdiodrv->driver.bus = &mdio_bus_type;
mdiodrv->driver.probe = mdio_probe;
mdiodrv->driver.remove = mdio_remove;
+ mdiodrv->driver.shutdown = mdio_shutdown;
retval = driver_register(&mdiodrv->driver);
if (retval) {
static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
{
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
struct net_device *netdev = phydev->attached_dev;
- if (!phydev->drv->suspend)
+ if (!drv || !phydrv->suspend)
return false;
/* PHY not attached? May suspend if the PHY has not already been
if (config.an_enabled && phylink_is_empty_linkmode(config.advertising))
return -EINVAL;
+ /* If this link is with an SFP, ensure that changes to advertised modes
+ * also cause the associated interface to be selected such that the
+ * link can be configured correctly.
+ */
+ if (pl->sfp_port && pl->sfp_bus) {
+ config.interface = sfp_select_interface(pl->sfp_bus,
+ config.advertising);
+ if (config.interface == PHY_INTERFACE_MODE_NA) {
+ phylink_err(pl,
+ "selection of interface failed, advertisement %*pb\n",
+ __ETHTOOL_LINK_MODE_MASK_NBITS,
+ config.advertising);
+ return -EINVAL;
+ }
+
+ /* Revalidate with the selected interface */
+ linkmode_copy(support, pl->supported);
+ if (phylink_validate(pl, support, &config)) {
+ phylink_err(pl, "validation of %s/%s with support %*pb failed\n",
+ phylink_an_mode_str(pl->cur_link_an_mode),
+ phy_modes(config.interface),
+ __ETHTOOL_LINK_MODE_MASK_NBITS, support);
+ return -EINVAL;
+ }
+ }
+
mutex_lock(&pl->state_mutex);
pl->link_config.speed = config.speed;
pl->link_config.duplex = config.duplex;
if (phy_interface_mode_is_8023z(iface) && pl->phydev)
return -EINVAL;
- changed = !linkmode_equal(pl->supported, support);
+ changed = !linkmode_equal(pl->supported, support) ||
+ !linkmode_equal(pl->link_config.advertising,
+ config.advertising);
if (changed) {
linkmode_copy(pl->supported, support);
linkmode_copy(pl->link_config.advertising, config.advertising);
serial = kzalloc(sizeof(*serial), GFP_KERNEL);
if (!serial)
- goto exit;
+ goto err_free_dev;
hso_dev->port_data.dev_serial = serial;
serial->parent = hso_dev;
if (hso_serial_common_create
(serial, 1, CTRL_URB_RX_SIZE, CTRL_URB_TX_SIZE))
- goto exit;
+ goto err_free_serial;
serial->tx_data_length--;
serial->write_data = hso_mux_serial_write_data;
/* done, return it */
return hso_dev;
-exit:
- if (serial) {
- tty_unregister_device(tty_drv, serial->minor);
- kfree(serial);
- }
+err_free_serial:
+ kfree(serial);
+err_free_dev:
kfree(hso_dev);
return NULL;
skb_reserve(skb, p - buf);
skb_put(skb, len);
+
+ page = (struct page *)page->private;
+ if (page)
+ give_pages(rq, page);
goto ok;
}
LIST_HEAD(list);
unsigned int h;
- rtnl_lock();
list_for_each_entry(net, net_list, exit_list) {
struct vxlan_net *vn = net_generic(net, vxlan_net_id);
unregister_nexthop_notifier(net, &vn->nexthop_notifier_block);
}
+ rtnl_lock();
list_for_each_entry(net, net_list, exit_list)
vxlan_destroy_tunnels(net, &list);
clean-files := wanxlfw.inc
$(obj)/wanxl.o: $(obj)/wanxlfw.inc
+CROSS_COMPILE_M68K = m68k-linux-gnu-
+
ifeq ($(CONFIG_WANXL_BUILD_FIRMWARE),y)
ifeq ($(ARCH),m68k)
M68KCC = $(CC)
* the header's copy failed, and they are
* sharing a slot, send an error
*/
- if (i == 0 && sharedslot)
+ if (i == 0 && !first_shinfo && sharedslot)
xenvif_idx_release(queue, pending_idx,
XEN_NETIF_RSP_ERROR);
else
static struct spi_device_id st_nci_spi_id_table[] = {
{ST_NCI_SPI_DRIVER_NAME, 0},
+ {"st21nfcb-spi", 0},
{}
};
MODULE_DEVICE_TABLE(spi, st_nci_spi_id_table);
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/backing-dev.h>
-#include <linux/list_sort.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/pr.h>
lockdep_assert_held(&subsys->lock);
list_for_each_entry(h, &subsys->nsheads, entry) {
- if (h->ns_id == nsid && nvme_tryget_ns_head(h))
+ if (h->ns_id != nsid)
+ continue;
+ if (!list_empty(&h->list) && nvme_tryget_ns_head(h))
return h;
}
return ret;
}
-static int ns_cmp(void *priv, const struct list_head *a,
- const struct list_head *b)
-{
- struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
- struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
-
- return nsa->head->ns_id - nsb->head->ns_id;
-}
-
struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
{
struct nvme_ns *ns, *ret = NULL;
}
EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
+/*
+ * Add the namespace to the controller list while keeping the list ordered.
+ */
+static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns)
+{
+ struct nvme_ns *tmp;
+
+ list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) {
+ if (tmp->head->ns_id < ns->head->ns_id) {
+ list_add(&ns->list, &tmp->list);
+ return;
+ }
+ }
+ list_add(&ns->list, &ns->ctrl->namespaces);
+}
+
static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid,
struct nvme_ns_ids *ids)
{
goto out_unlink_ns;
down_write(&ctrl->namespaces_rwsem);
- list_add_tail(&ns->list, &ctrl->namespaces);
+ nvme_ns_add_to_ctrl_list(ns);
up_write(&ctrl->namespaces_rwsem);
-
nvme_get_ctrl(ctrl);
if (device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups))
mutex_lock(&ns->ctrl->subsys->lock);
list_del_rcu(&ns->siblings);
+ if (list_empty(&ns->head->list)) {
+ list_del_init(&ns->head->entry);
+ last_path = true;
+ }
mutex_unlock(&ns->ctrl->subsys->lock);
/* guarantee not available in head->list */
nvme_cdev_del(&ns->cdev, &ns->cdev_device);
del_gendisk(ns->disk);
blk_cleanup_queue(ns->queue);
- if (blk_get_integrity(ns->disk))
- blk_integrity_unregister(ns->disk);
down_write(&ns->ctrl->namespaces_rwsem);
list_del_init(&ns->list);
up_write(&ns->ctrl->namespaces_rwsem);
- /* Synchronize with nvme_init_ns_head() */
- mutex_lock(&ns->head->subsys->lock);
- if (list_empty(&ns->head->list)) {
- list_del_init(&ns->head->entry);
- last_path = true;
- }
- mutex_unlock(&ns->head->subsys->lock);
if (last_path)
nvme_mpath_shutdown_disk(ns->head);
nvme_put_ns(ns);
if (nvme_scan_ns_list(ctrl) != 0)
nvme_scan_ns_sequential(ctrl);
mutex_unlock(&ctrl->scan_lock);
-
- down_write(&ctrl->namespaces_rwsem);
- list_sort(NULL, &ctrl->namespaces, ns_cmp);
- up_write(&ctrl->namespaces_rwsem);
}
/*
*/
if (ctrl->ctrl.queue_count > 1) {
nvme_stop_queues(&ctrl->ctrl);
+ nvme_sync_io_queues(&ctrl->ctrl);
blk_mq_tagset_busy_iter(&ctrl->tag_set,
nvme_fc_terminate_exchange, &ctrl->ctrl);
blk_mq_tagset_wait_completed_request(&ctrl->tag_set);
* clean up the admin queue. Same thing as above.
*/
blk_mq_quiesce_queue(ctrl->ctrl.admin_q);
+ blk_sync_queue(ctrl->ctrl.admin_q);
blk_mq_tagset_busy_iter(&ctrl->admin_tag_set,
nvme_fc_terminate_exchange, &ctrl->ctrl);
blk_mq_tagset_wait_completed_request(&ctrl->admin_tag_set);
if (ctrl->ctrl.queue_count == 1)
return 0;
+ if (prior_ioq_cnt != nr_io_queues) {
+ dev_info(ctrl->ctrl.device,
+ "reconnect: revising io queue count from %d to %d\n",
+ prior_ioq_cnt, nr_io_queues);
+ blk_mq_update_nr_hw_queues(&ctrl->tag_set, nr_io_queues);
+ }
+
ret = nvme_fc_create_hw_io_queues(ctrl, ctrl->ctrl.sqsize + 1);
if (ret)
goto out_free_io_queues;
if (ret)
goto out_delete_hw_queues;
- if (prior_ioq_cnt != nr_io_queues) {
- dev_info(ctrl->ctrl.device,
- "reconnect: revising io queue count from %d to %d\n",
- prior_ioq_cnt, nr_io_queues);
- nvme_wait_freeze(&ctrl->ctrl);
- blk_mq_update_nr_hw_queues(&ctrl->tag_set, nr_io_queues);
- nvme_unfreeze(&ctrl->ctrl);
- }
-
return 0;
out_delete_hw_queues:
down_read(&ctrl->namespaces_rwsem);
list_for_each_entry(ns, &ctrl->namespaces, list) {
- unsigned nsid = le32_to_cpu(desc->nsids[n]);
-
+ unsigned nsid;
+again:
+ nsid = le32_to_cpu(desc->nsids[n]);
if (ns->head->ns_id < nsid)
continue;
if (ns->head->ns_id == nsid)
nvme_update_ns_ana_state(desc, ns);
if (++n == nr_nsids)
break;
+ if (ns->head->ns_id > nsid)
+ goto again;
}
up_read(&ctrl->namespaces_rwsem);
return 0;
if (!test_and_clear_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
return;
- nvme_rdma_destroy_queue_ib(queue);
rdma_destroy_id(queue->cm_id);
+ nvme_rdma_destroy_queue_ib(queue);
mutex_destroy(&queue->queue_lock);
}
for (i = 0; i < queue->queue_size; i++) {
ret = nvme_rdma_post_recv(queue, &queue->rsp_ring[i]);
if (ret)
- goto out_destroy_queue_ib;
+ return ret;
}
return 0;
-
-out_destroy_queue_ib:
- nvme_rdma_destroy_queue_ib(queue);
- return ret;
}
static int nvme_rdma_conn_rejected(struct nvme_rdma_queue *queue,
if (ret) {
dev_err(ctrl->ctrl.device,
"rdma_connect_locked failed (%d).\n", ret);
- goto out_destroy_queue_ib;
+ return ret;
}
return 0;
-
-out_destroy_queue_ib:
- nvme_rdma_destroy_queue_ib(queue);
- return ret;
}
static int nvme_rdma_cm_handler(struct rdma_cm_id *cm_id,
case RDMA_CM_EVENT_ROUTE_ERROR:
case RDMA_CM_EVENT_CONNECT_ERROR:
case RDMA_CM_EVENT_UNREACHABLE:
- nvme_rdma_destroy_queue_ib(queue);
- fallthrough;
case RDMA_CM_EVENT_ADDR_ERROR:
dev_dbg(queue->ctrl->ctrl.device,
"CM error event %d\n", ev->event);
} while (ret > 0);
}
+static inline bool nvme_tcp_queue_more(struct nvme_tcp_queue *queue)
+{
+ return !list_empty(&queue->send_list) ||
+ !llist_empty(&queue->req_list) || queue->more_requests;
+}
+
static inline void nvme_tcp_queue_request(struct nvme_tcp_request *req,
bool sync, bool last)
{
nvme_tcp_send_all(queue);
queue->more_requests = false;
mutex_unlock(&queue->send_mutex);
- } else if (last) {
- queue_work_on(queue->io_cpu, nvme_tcp_wq, &queue->io_work);
}
+
+ if (last && nvme_tcp_queue_more(queue))
+ queue_work_on(queue->io_cpu, nvme_tcp_wq, &queue->io_work);
}
static void nvme_tcp_process_req_list(struct nvme_tcp_queue *queue)
cpu_to_le32(data->hdr.hlen + hdgst + req->pdu_len + ddgst);
data->ttag = pdu->ttag;
data->command_id = nvme_cid(rq);
- data->data_offset = cpu_to_le32(req->data_sent);
+ data->data_offset = pdu->r2t_offset;
data->data_length = cpu_to_le32(req->pdu_len);
return 0;
}
read_unlock_bh(&sk->sk_callback_lock);
}
-static inline bool nvme_tcp_queue_more(struct nvme_tcp_queue *queue)
-{
- return !list_empty(&queue->send_list) ||
- !llist_empty(&queue->req_list) || queue->more_requests;
-}
-
static inline void nvme_tcp_done_send_req(struct nvme_tcp_queue *queue)
{
queue->request = NULL;
nvme_tcp_ddgst_update(queue->snd_hash, page,
offset, ret);
- /* fully successful last write*/
+ /*
+ * update the request iterator except for the last payload send
+ * in the request where we don't want to modify it as we may
+ * compete with the RX path completing the request.
+ */
+ if (req->data_sent + ret < req->data_len)
+ nvme_tcp_advance_req(req, ret);
+
+ /* fully successful last send in current PDU */
if (last && ret == len) {
if (queue->data_digest) {
nvme_tcp_ddgst_final(queue->snd_hash,
}
return 1;
}
- nvme_tcp_advance_req(req, ret);
}
return -EAGAIN;
}
pending = true;
else if (unlikely(result < 0))
break;
- } else
- pending = !llist_empty(&queue->req_list);
+ }
result = nvme_tcp_try_recv(queue);
if (result > 0)
{
struct nvmet_subsys *subsys = to_subsys(item);
- return snprintf(page, PAGE_SIZE, "%*s\n",
+ return snprintf(page, PAGE_SIZE, "%.*s\n",
NVMET_SN_MAX_SIZE, subsys->serial);
}
config NVMEM_NINTENDO_OTP
tristate "Nintendo Wii and Wii U OTP Support"
+ depends on WII || COMPILE_TEST
help
This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
break;
}
- if (i != count && of_reserved_mem_device_init_by_idx(dev, of_node, i))
+ /*
+ * Attempt to initialize a restricted-dma-pool region if one was found.
+ * Note that count can hold a negative error code.
+ */
+ if (i < count && of_reserved_mem_device_init_by_idx(dev, of_node, i))
dev_warn(dev, "failed to initialise \"restricted-dma-pool\" memory node\n");
}
DEFINE_SIMPLE_PROP(resets, "resets", "#reset-cells")
DEFINE_SIMPLE_PROP(leds, "leds", NULL)
DEFINE_SIMPLE_PROP(backlight, "backlight", NULL)
-DEFINE_SIMPLE_PROP(phy_handle, "phy-handle", NULL)
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
{ .parse_prop = parse_resets, },
{ .parse_prop = parse_leds, },
{ .parse_prop = parse_backlight, },
- { .parse_prop = parse_phy_handle, },
{ .parse_prop = parse_gpio_compat, },
{ .parse_prop = parse_interrupts, },
{ .parse_prop = parse_regulators, },
config XEN_PCIDEV_FRONTEND
tristate "Xen PCI Frontend"
- depends on X86 && XEN
+ depends on XEN_PV
select PCI_XEN
select XEN_XENBUS_FRONTEND
default y
void pci_set_acpi_fwnode(struct pci_dev *dev)
{
- if (!ACPI_COMPANION(&dev->dev) && !pci_dev_is_added(dev))
+ if (!dev_fwnode(&dev->dev) && !pci_dev_is_added(dev))
ACPI_COMPANION_SET(&dev->dev,
acpi_pci_find_companion(&dev->dev));
}
PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
/*
- * Create device link for NVIDIA GPU with integrated USB xHCI Host
+ * Create device link for GPUs with integrated USB xHCI Host
* controller to VGA.
*/
static void quirk_gpu_usb(struct pci_dev *usb)
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
+ PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
/*
- * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
+ * Create device link for GPUs with integrated Type-C UCSI controller
* to VGA. Currently there is no class code defined for UCSI device over PCI
* so using UNKNOWN class for now and it will be updated when UCSI
* over PCI gets a class code.
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
PCI_CLASS_SERIAL_UNKNOWN, 8,
quirk_gpu_usb_typec_ucsi);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
+ PCI_CLASS_SERIAL_UNKNOWN, 8,
+ quirk_gpu_usb_typec_ucsi);
/*
* Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
return off ?: PCI_VPD_SZ_INVALID;
}
+static bool pci_vpd_available(struct pci_dev *dev)
+{
+ struct pci_vpd *vpd = &dev->vpd;
+
+ if (!vpd->cap)
+ return false;
+
+ if (vpd->len == 0) {
+ vpd->len = pci_vpd_size(dev);
+ if (vpd->len == PCI_VPD_SZ_INVALID) {
+ vpd->cap = 0;
+ return false;
+ }
+ }
+
+ return true;
+}
+
/*
* Wait for last operation to complete.
* This code has to spin since there is no other notification from the PCI
loff_t end = pos + count;
u8 *buf = arg;
- if (!vpd->cap)
+ if (!pci_vpd_available(dev))
return -ENODEV;
if (pos < 0)
loff_t end = pos + count;
int ret = 0;
- if (!vpd->cap)
+ if (!pci_vpd_available(dev))
return -ENODEV;
if (pos < 0 || (pos & 3) || (count & 3))
void pci_vpd_init(struct pci_dev *dev)
{
+ if (dev->vpd.len == PCI_VPD_SZ_INVALID)
+ return;
+
dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
mutex_init(&dev->vpd.lock);
-
- if (!dev->vpd.len)
- dev->vpd.len = pci_vpd_size(dev);
-
- if (dev->vpd.len == PCI_VPD_SZ_INVALID)
- dev->vpd.cap = 0;
}
static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size)
{
- unsigned int len = dev->vpd.len;
+ unsigned int len;
void *buf;
int cnt;
- if (!dev->vpd.cap)
+ if (!pci_vpd_available(dev))
return ERR_PTR(-ENODEV);
+ len = dev->vpd.len;
buf = kmalloc(len, GFP_KERNEL);
if (!buf)
return ERR_PTR(-ENOMEM);
#define AMD_CPU_ID_YC 0x14B5
#define PMC_MSG_DELAY_MIN_US 100
-#define RESPONSE_REGISTER_LOOP_MAX 200
+#define RESPONSE_REGISTER_LOOP_MAX 20000
#define SOC_SUBSYSTEM_IP_MAX 12
#define DELAY_MIN_US 2000
config DELL_WMI_PRIVACY
bool "Dell WMI Hardware Privacy Support"
- depends on DELL_WMI
- depends on LEDS_TRIGGER_AUDIO
+ depends on LEDS_TRIGGER_AUDIO = y || DELL_WMI = LEDS_TRIGGER_AUDIO
help
This option adds integration with the "Dell Hardware Privacy"
feature of Dell laptops to the dell-wmi driver.
DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 AORUS ELITE"),
DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 AORUS ELITE V2"),
DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550 GAMING X V2"),
+ DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550I AORUS PRO AX"),
DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M AORUS PRO-P"),
DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("B550M DS3H"),
DMI_EXACT_MATCH_GIGABYTE_BOARD_NAME("Z390 I AORUS PRO WIFI-CF"),
{ }
};
+/*
+ * Some devices, even non convertible ones, can send incorrect SW_TABLET_MODE
+ * reports. Accept such reports only from devices in this list.
+ */
+static const struct dmi_system_id dmi_auto_add_switch[] = {
+ {
+ .matches = {
+ DMI_EXACT_MATCH(DMI_CHASSIS_TYPE, "31" /* Convertible */),
+ },
+ },
+ {
+ .matches = {
+ DMI_EXACT_MATCH(DMI_CHASSIS_TYPE, "32" /* Detachable */),
+ },
+ },
+ {} /* Array terminator */
+};
+
struct intel_hid_priv {
struct input_dev *input_dev;
struct input_dev *array;
struct input_dev *switches;
bool wakeup_mode;
- bool dual_accel;
+ bool auto_add_switch;
};
#define HID_EVENT_FILTER_UUID "eeec56b3-4442-408f-a792-4edd4d758054"
* Some convertible have unreliable VGBS return which could cause incorrect
* SW_TABLET_MODE report, in these cases we enable support when receiving
* the first event instead of during driver setup.
- *
- * See dual_accel_detect.h for more info on the dual_accel check.
*/
- if (!priv->switches && !priv->dual_accel && (event == 0xcc || event == 0xcd)) {
+ if (!priv->switches && priv->auto_add_switch && (event == 0xcc || event == 0xcd)) {
dev_info(&device->dev, "switch event received, enable switches supports\n");
err = intel_hid_switches_setup(device);
if (err)
return -ENOMEM;
dev_set_drvdata(&device->dev, priv);
- priv->dual_accel = dual_accel_detect();
+ /* See dual_accel_detect.h for more info on the dual_accel check. */
+ priv->auto_add_switch = dmi_check_system(dmi_auto_add_switch) && !dual_accel_detect();
err = intel_hid_input_setup(device);
if (err) {
* which provide mailbox interface for power management usage.
*/
-#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/device.h>
.remove = intel_punit_ipc_remove,
.driver = {
.name = "intel_punit_ipc",
- .acpi_match_table = ACPI_PTR(punit_ipc_acpi_ids),
+ .acpi_match_table = punit_ipc_acpi_ids,
},
};
goto out_platform_registered;
}
product = dmi_get_system_info(DMI_PRODUCT_NAME);
- if (strlen(product) > 4)
+ if (product && strlen(product) > 4)
switch (product[4]) {
case '5':
case '6':
};
static const struct property_entry chuwi_hi10_plus_props[] = {
- PROPERTY_ENTRY_U32("touchscreen-min-x", 0),
- PROPERTY_ENTRY_U32("touchscreen-min-y", 5),
- PROPERTY_ENTRY_U32("touchscreen-size-x", 1914),
- PROPERTY_ENTRY_U32("touchscreen-size-y", 1283),
+ PROPERTY_ENTRY_U32("touchscreen-min-x", 12),
+ PROPERTY_ENTRY_U32("touchscreen-min-y", 10),
+ PROPERTY_ENTRY_U32("touchscreen-size-x", 1908),
+ PROPERTY_ENTRY_U32("touchscreen-size-y", 1270),
PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-chuwi-hi10plus.fw"),
PROPERTY_ENTRY_U32("silead,max-fingers", 10),
PROPERTY_ENTRY_BOOL("silead,home-button"),
};
static const struct ts_dmi_data chuwi_hi10_plus_data = {
+ .embedded_fw = {
+ .name = "silead/gsl1680-chuwi-hi10plus.fw",
+ .prefix = { 0xf0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00 },
+ .length = 34056,
+ .sha256 = { 0xfd, 0x0a, 0x08, 0x08, 0x3c, 0xa6, 0x34, 0x4e,
+ 0x2c, 0x49, 0x9c, 0xcd, 0x7d, 0x44, 0x9d, 0x38,
+ 0x10, 0x68, 0xb5, 0xbd, 0xb7, 0x2a, 0x63, 0xb5,
+ 0x67, 0x0b, 0x96, 0xbd, 0x89, 0x67, 0x85, 0x09 },
+ },
.acpi_name = "MSSL0017:00",
.properties = chuwi_hi10_plus_props,
};
.properties = chuwi_hi10_pro_props,
};
+static const struct property_entry chuwi_hibook_props[] = {
+ PROPERTY_ENTRY_U32("touchscreen-min-x", 30),
+ PROPERTY_ENTRY_U32("touchscreen-min-y", 4),
+ PROPERTY_ENTRY_U32("touchscreen-size-x", 1892),
+ PROPERTY_ENTRY_U32("touchscreen-size-y", 1276),
+ PROPERTY_ENTRY_BOOL("touchscreen-inverted-y"),
+ PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"),
+ PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-chuwi-hibook.fw"),
+ PROPERTY_ENTRY_U32("silead,max-fingers", 10),
+ PROPERTY_ENTRY_BOOL("silead,home-button"),
+ { }
+};
+
+static const struct ts_dmi_data chuwi_hibook_data = {
+ .embedded_fw = {
+ .name = "silead/gsl1680-chuwi-hibook.fw",
+ .prefix = { 0xf0, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00 },
+ .length = 40392,
+ .sha256 = { 0xf7, 0xc0, 0xe8, 0x5a, 0x6c, 0xf2, 0xeb, 0x8d,
+ 0x12, 0xc4, 0x45, 0xbf, 0x55, 0x13, 0x4c, 0x1a,
+ 0x13, 0x04, 0x31, 0x08, 0x65, 0x73, 0xf7, 0xa8,
+ 0x1b, 0x7d, 0x59, 0xc9, 0xe6, 0x97, 0xf7, 0x38 },
+ },
+ .acpi_name = "MSSL0017:00",
+ .properties = chuwi_hibook_props,
+};
+
static const struct property_entry chuwi_vi8_props[] = {
PROPERTY_ENTRY_U32("touchscreen-min-x", 4),
PROPERTY_ENTRY_U32("touchscreen-min-y", 6),
},
},
{
+ /* Chuwi HiBook (CWI514) */
+ .driver_data = (void *)&chuwi_hibook_data,
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Hampoo"),
+ DMI_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
+ /* Above matches are too generic, add bios-date match */
+ DMI_MATCH(DMI_BIOS_DATE, "05/07/2016"),
+ },
+ },
+ {
/* Chuwi Vi8 (CWI506) */
.driver_data = (void *)&chuwi_vi8_data,
.matches = {
depends on I2C && MTD
depends on SERIAL_8250
depends on !S390
+ depends on COMMON_CLK
select NET_DEVLINK
help
This driver adds support for an OpenCompute time card.
MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
MODULE_DESCRIPTION("Maxim 14577/77836 regulator driver");
MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:max14577-regulator");
-MODULE_ALIAS("platform:max77836-regulator");
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s6", &pmic5_pldo_lv, "vdd-l7"),
+ RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7"),
{}
};
* ACK the rtc irq here
*/
if (t_now >= cmos->alarm_expires && cmos_use_acpi_alarm()) {
+ local_irq_disable();
cmos_interrupt(0, (void *)cmos->rtc);
+ local_irq_enable();
return;
}
sclp.has_gisaf = !!(sccb->fac118 & 0x08);
sclp.has_hvs = !!(sccb->fac119 & 0x80);
sclp.has_kss = !!(sccb->fac98 & 0x01);
- sclp.has_sipl = !!(sccb->cbl & 0x4000);
if (sccb->fac85 & 0x02)
S390_lowcore.machine_flags |= MACHINE_FLAG_ESOP;
if (sccb->fac91 & 0x40)
S390_lowcore.machine_flags |= MACHINE_FLAG_TLB_GUEST;
if (sccb->cpuoff > 134)
sclp.has_diag318 = !!(sccb->byte_134 & 0x80);
+ if (sccb->cpuoff > 137)
+ sclp.has_sipl = !!(sccb->cbl & 0x4000);
sclp.rnmax = sccb->rnmax ? sccb->rnmax : sccb->rnmax2;
sclp.rzm = sccb->rnsize ? sccb->rnsize : sccb->rnsize2;
sclp.rzm <<= 20;
/**
* ccwgroup_set_offline() - disable a ccwgroup device
* @gdev: target ccwgroup device
+ * @call_gdrv: Call the registered gdrv set_offline function
*
* This function attempts to put the ccwgroup device into the offline state.
* Returns:
* %0 on success and a negative error value on failure.
*/
-int ccwgroup_set_offline(struct ccwgroup_device *gdev)
+int ccwgroup_set_offline(struct ccwgroup_device *gdev, bool call_gdrv)
{
struct ccwgroup_driver *gdrv = to_ccwgroupdrv(gdev->dev.driver);
int ret = -EINVAL;
return -EAGAIN;
if (gdev->state == CCWGROUP_OFFLINE)
goto out;
+ if (!call_gdrv) {
+ ret = 0;
+ goto offline;
+ }
if (gdrv->set_offline)
ret = gdrv->set_offline(gdev);
if (ret)
goto out;
+offline:
gdev->state = CCWGROUP_OFFLINE;
out:
atomic_set(&gdev->onoff, 0);
if (value == 1)
ret = ccwgroup_set_online(gdev);
else if (value == 0)
- ret = ccwgroup_set_offline(gdev);
+ ret = ccwgroup_set_offline(gdev, true);
else
ret = -EINVAL;
out:
* ap_init_qci_info(): Allocate and query qci config info.
* Does also update the static variables ap_max_domain_id
* and ap_max_adapter_id if this info is available.
-
*/
static void __init ap_init_qci_info(void)
{
/**
* ap_interrupt_handler() - Schedule ap_tasklet on interrupt
* @airq: pointer to adapter interrupt descriptor
+ * @floating: ignored
*/
static void ap_interrupt_handler(struct airq_struct *airq, bool floating)
{
/**
* ap_scan_bus(): Scan the AP bus for new devices
* Runs periodically, workqueue timer (ap_config_time)
+ * @unused: Unused pointer.
*/
static void ap_scan_bus(struct work_struct *unused)
{
/**
* ap_queue_enable_irq(): Enable interrupt support on this AP queue.
- * @qid: The AP queue number
+ * @aq: The AP queue
* @ind: the notification indicator byte
*
* Enables interruption on AP queue via ap_aqic(). Based on the return
/**
* ap_sm_reset(): Reset an AP queue.
- * @qid: The AP queue number
+ * @aq: The AP queue
*
* Submit the Reset command to an AP queue.
*/
struct napi_struct napi;
struct qeth_rx rx;
struct delayed_work buffer_reclaim_work;
- struct work_struct close_dev_work;
};
static inline bool qeth_card_hw_is_reachable(struct qeth_card *card)
static int qeth_qdio_establish(struct qeth_card *);
static void qeth_free_qdio_queues(struct qeth_card *card);
-static void qeth_close_dev_handler(struct work_struct *work)
-{
- struct qeth_card *card;
-
- card = container_of(work, struct qeth_card, close_dev_work);
- QETH_CARD_TEXT(card, 2, "cldevhdl");
- ccwgroup_set_offline(card->gdev);
-}
-
static const char *qeth_get_cardname(struct qeth_card *card)
{
if (IS_VM_NIC(card)) {
&card->qdio.in_buf_pool.entry_list, list)
list_del(&pool_entry->list);
+ if (!queue)
+ return;
+
for (i = 0; i < ARRAY_SIZE(queue->bufs); i++)
queue->bufs[i].pool_entry = NULL;
}
case IPA_CMD_STOPLAN:
if (cmd->hdr.return_code == IPA_RC_VEPA_TO_VEB_TRANSITION) {
dev_err(&card->gdev->dev,
- "Interface %s is down because the adjacent port is no longer in reflective relay mode\n",
+ "Adjacent port of interface %s is no longer in reflective relay mode, trigger recovery\n",
netdev_name(card->dev));
- schedule_work(&card->close_dev_work);
+ /* Set offline, then probably fail to set online: */
+ qeth_schedule_recovery(card);
} else {
+ /* stay online for subsequent STARTLAN */
dev_warn(&card->gdev->dev,
"The link for interface %s on CHPID 0x%X failed\n",
netdev_name(card->dev), card->info.chpid);
INIT_LIST_HEAD(&card->ipato.entries);
qeth_init_qdio_info(card);
INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
- INIT_WORK(&card->close_dev_work, qeth_close_dev_handler);
hash_init(card->rx_mode_addrs);
hash_init(card->local_addrs4);
hash_init(card->local_addrs6);
dev_info(&card->gdev->dev,
"Device successfully recovered!\n");
} else {
- ccwgroup_set_offline(card->gdev);
+ qeth_set_offline(card, disc, true);
+ ccwgroup_set_offline(card->gdev, false);
dev_warn(&card->gdev->dev,
"The qeth device driver failed to recover an error on the device\n");
}
if (gdev->state == CCWGROUP_ONLINE)
qeth_set_offline(card, card->discipline, false);
- cancel_work_sync(&card->close_dev_work);
if (card->dev->reg_state == NETREG_REGISTERED) {
priv = netdev_priv(card->dev);
if (priv->brport_features & BR_LEARNING_SYNC) {
if (cgdev->state == CCWGROUP_ONLINE)
qeth_set_offline(card, card->discipline, false);
- cancel_work_sync(&card->close_dev_work);
if (card->dev->reg_state == NETREG_REGISTERED)
unregister_netdev(card->dev);
This enables support for the Acorn SCSI card (aka30). If you have an
Acorn system with one of these, say Y. If unsure, say N.
-config SCSI_ACORNSCSI_TAGGED_QUEUE
- bool "Support SCSI 2 Tagged queueing"
- depends on SCSI_ACORNSCSI_3
- help
- Say Y here to enable tagged queuing support on the Acorn SCSI card.
-
- This is a feature of SCSI-2 which improves performance: the host
- adapter can send several SCSI commands to a device's queue even if
- previous commands haven't finished yet. Some SCSI devices don't
- implement this properly, so the safe answer is N.
-
config SCSI_ACORNSCSI_SYNC
bool "Support SCSI 2 Synchronous Transfers"
depends on SCSI_ACORNSCSI_3
* You can tell if you have a device that supports tagged queueing my
* cating (eg) /proc/scsi/acornscsi/0 and see if the SCSI revision is reported
* as '2 TAG'.
- *
- * Also note that CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE is normally set in the config
- * scripts, but disabled here. Once debugged, remove the #undef, otherwise to debug,
- * comment out the undef.
*/
-#undef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
+
/*
* SCSI-II Synchronous transfer support.
*
unsigned int result);
static int acornscsi_reconnect_finish(AS_Host *host);
static void acornscsi_dma_cleanup(AS_Host *host);
-static void acornscsi_abortcmd(AS_Host *host, unsigned char tag);
+static void acornscsi_abortcmd(AS_Host *host);
/* ====================================================================================
* Miscellaneous
#endif
if (from_queue) {
-#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
- /*
- * tagged queueing - allocate a new tag to this command
- */
- if (SCpnt->device->simple_tags) {
- SCpnt->device->current_tag += 1;
- if (SCpnt->device->current_tag == 0)
- SCpnt->device->current_tag = 1;
- SCpnt->tag = SCpnt->device->current_tag;
- } else
-#endif
set_bit(SCpnt->device->id * 8 +
(u8)(SCpnt->device->lun & 0x07), host->busyluns);
* the device recognises the attention.
*/
if (dmac_read(host, DMAC_STATUS) & STATUS_RQ0) {
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
dmac_write(host, DMAC_TXCNTLO, 0);
dmac_write(host, DMAC_TXCNTHI, 0);
acornscsi_sbic_issuecmd(host, CMND_ASSERTATN);
switch (host->scsi.last_message) {
-#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
- case HEAD_OF_QUEUE_TAG:
- case ORDERED_QUEUE_TAG:
- case SIMPLE_QUEUE_TAG:
- /*
- * ANSI standard says: (Section SCSI-2 Rev. 10c Sect 5.6.17)
- * If a target does not implement tagged queuing and a queue tag
- * message is received, it shall respond with a MESSAGE REJECT
- * message and accept the I/O process as if it were untagged.
- */
- printk(KERN_NOTICE "scsi%d.%c: disabling tagged queueing\n",
- host->host->host_no, acornscsi_target(host));
- host->SCpnt->device->simple_tags = 0;
- set_bit(host->SCpnt->device->id * 8 +
- (u8)(host->SCpnt->device->lun & 0x7), host->busyluns);
- break;
-#endif
case EXTENDED_MESSAGE | (EXTENDED_SDTR << 8):
/*
* Target can't handle synchronous transfers
#if 0
/* does the device need the current command aborted */
if (cmd_aborted) {
- acornscsi_abortcmd(host->SCpnt->tag);
+ acornscsi_abortcmd(host);
return;
}
#endif
-#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
- if (host->SCpnt->tag) {
- unsigned int tag_type;
-
- if (host->SCpnt->cmnd[0] == REQUEST_SENSE ||
- host->SCpnt->cmnd[0] == TEST_UNIT_READY ||
- host->SCpnt->cmnd[0] == INQUIRY)
- tag_type = HEAD_OF_QUEUE_TAG;
- else
- tag_type = SIMPLE_QUEUE_TAG;
- msgqueue_addmsg(&host->scsi.msgs, 2, tag_type, host->SCpnt->tag);
- }
-#endif
#ifdef CONFIG_SCSI_ACORNSCSI_SYNC
if (host->device[host->SCpnt->device->id].sync_state == SYNC_NEGOCIATE) {
"to reconnect with\n",
host->host->host_no, '0' + target);
acornscsi_dumplog(host, target);
- acornscsi_abortcmd(host, 0);
+ acornscsi_abortcmd(host);
if (host->SCpnt) {
queue_add_cmd_tail(&host->queues.disconnected, host->SCpnt);
host->SCpnt = NULL;
host->scsi.disconnectable = 0;
if (host->SCpnt->device->id == host->scsi.reconnected.target &&
host->SCpnt->device->lun == host->scsi.reconnected.lun &&
- host->SCpnt->tag == host->scsi.reconnected.tag) {
+ scsi_cmd_to_tag(host->SCpnt) == host->scsi.reconnected.tag) {
#if (DEBUG & (DEBUG_QUEUES|DEBUG_DISCON))
DBG(host->SCpnt, printk("scsi%d.%c: reconnected",
host->host->host_no, acornscsi_target(host)));
}
if (!host->SCpnt)
- acornscsi_abortcmd(host, host->scsi.reconnected.tag);
+ acornscsi_abortcmd(host);
else {
/*
* Restore data pointer from SAVED pointers.
* Function: void acornscsi_abortcmd(AS_host *host, unsigned char tag)
* Purpose : abort a currently executing command
* Params : host - host with connected command to abort
- * tag - tag to abort
*/
static
-void acornscsi_abortcmd(AS_Host *host, unsigned char tag)
+void acornscsi_abortcmd(AS_Host *host)
{
host->scsi.phase = PHASE_ABORTED;
sbic_arm_write(host, SBIC_CMND, CMND_ASSERTATN);
msgqueue_flush(&host->scsi.msgs);
-#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
- if (tag)
- msgqueue_addmsg(&host->scsi.msgs, 2, ABORT_TAG, tag);
- else
-#endif
- msgqueue_addmsg(&host->scsi.msgs, 1, ABORT);
+ msgqueue_addmsg(&host->scsi.msgs, 1, ABORT);
}
/* ==========================================================================================
printk(KERN_ERR "scsi%d.%c: PHASE_CONNECTING, SSR %02X?\n",
host->host->host_no, acornscsi_target(host), ssr);
acornscsi_dumplog(host, host->SCpnt ? host->SCpnt->device->id : 8);
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
}
return INTR_PROCESSING;
printk(KERN_ERR "scsi%d.%c: PHASE_CONNECTED, SSR %02X?\n",
host->host->host_no, acornscsi_target(host), ssr);
acornscsi_dumplog(host, host->SCpnt ? host->SCpnt->device->id : 8);
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
}
return INTR_PROCESSING;
case 0x18: /* -> PHASE_DATAOUT */
/* COMMAND -> DATA OUT */
if (host->scsi.SCp.sent_command != host->SCpnt->cmd_len)
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
acornscsi_dma_setup(host, DMA_OUT);
if (!acornscsi_starttransfer(host))
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
host->scsi.phase = PHASE_DATAOUT;
return INTR_IDLE;
case 0x19: /* -> PHASE_DATAIN */
/* COMMAND -> DATA IN */
if (host->scsi.SCp.sent_command != host->SCpnt->cmd_len)
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
acornscsi_dma_setup(host, DMA_IN);
if (!acornscsi_starttransfer(host))
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
host->scsi.phase = PHASE_DATAIN;
return INTR_IDLE;
/* MESSAGE IN -> DATA OUT */
acornscsi_dma_setup(host, DMA_OUT);
if (!acornscsi_starttransfer(host))
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
host->scsi.phase = PHASE_DATAOUT;
return INTR_IDLE;
/* MESSAGE IN -> DATA IN */
acornscsi_dma_setup(host, DMA_IN);
if (!acornscsi_starttransfer(host))
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
host->scsi.phase = PHASE_DATAIN;
return INTR_IDLE;
switch (ssr) {
case 0x19: /* -> PHASE_DATAIN */
case 0x89: /* -> PHASE_DATAIN */
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
return INTR_IDLE;
case 0x1b: /* -> PHASE_STATUSIN */
switch (ssr) {
case 0x18: /* -> PHASE_DATAOUT */
case 0x88: /* -> PHASE_DATAOUT */
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
return INTR_IDLE;
case 0x1b: /* -> PHASE_STATUSIN */
SCpnt->scsi_done = done;
SCpnt->host_scribble = NULL;
SCpnt->result = 0;
- SCpnt->tag = 0;
SCpnt->SCp.phase = (int)acornscsi_datadirection(SCpnt->cmnd[0]);
SCpnt->SCp.sent_command = 0;
SCpnt->SCp.scsi_xferred = 0;
break;
default:
- acornscsi_abortcmd(host, host->SCpnt->tag);
+ acornscsi_abortcmd(host);
res = res_snooze;
}
local_irq_restore(flags);
#ifdef CONFIG_SCSI_ACORNSCSI_SYNC
" SYNC"
#endif
-#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
- " TAG"
-#endif
#if (DEBUG & DEBUG_NO_WRITE)
" NOWRITE (" __stringify(NO_WRITE) ")"
#endif
#ifdef CONFIG_SCSI_ACORNSCSI_SYNC
" SYNC"
#endif
-#ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
- " TAG"
-#endif
#if (DEBUG & DEBUG_NO_WRITE)
" NOWRITE (" __stringify(NO_WRITE) ")"
#endif
seq_printf(m, "Device/Lun TaggedQ Sync\n");
seq_printf(m, " %d/%llu ", scd->id, scd->lun);
if (scd->tagged_supported)
- seq_printf(m, "%3sabled(%3d) ",
- scd->simple_tags ? "en" : "dis",
- scd->current_tag);
+ seq_printf(m, "%3sabled ",
+ scd->simple_tags ? "en" : "dis");
else
seq_printf(m, "unsupported ");
* I was thinking that this was a good chip until I found this restriction ;(
*/
#define SCSI2_SYNC
-#undef SCSI2_TAG
#undef DEBUG_CONNECT
#undef DEBUG_MESSAGES
info->scsi.disconnectable = 0;
if (info->SCpnt->device->id == target &&
info->SCpnt->device->lun == lun &&
- info->SCpnt->tag == tag) {
+ scsi_cmd_to_rq(info->SCpnt)->tag == tag) {
fas216_log(info, LOG_CONNECT, "reconnected previously executing command");
} else {
queue_add_cmd_tail(&info->queues.disconnected, info->SCpnt);
/*
* add tag message if required
*/
- if (SCpnt->tag)
- msgqueue_addmsg(&info->scsi.msgs, 2, SIMPLE_QUEUE_TAG, SCpnt->tag);
+ if (SCpnt->device->simple_tags)
+ msgqueue_addmsg(&info->scsi.msgs, 2, SIMPLE_QUEUE_TAG,
+ scsi_cmd_to_rq(SCpnt)->tag);
do {
#ifdef SCSI2_SYNC
static void fas216_allocate_tag(FAS216_Info *info, struct scsi_cmnd *SCpnt)
{
-#ifdef SCSI2_TAG
- /*
- * tagged queuing - allocate a new tag to this command
- */
- if (SCpnt->device->simple_tags && SCpnt->cmnd[0] != REQUEST_SENSE &&
- SCpnt->cmnd[0] != INQUIRY) {
- SCpnt->device->current_tag += 1;
- if (SCpnt->device->current_tag == 0)
- SCpnt->device->current_tag = 1;
- SCpnt->tag = SCpnt->device->current_tag;
- } else
-#endif
- set_bit(SCpnt->device->id * 8 +
- (u8)(SCpnt->device->lun & 0x7), info->busyluns);
+ set_bit(SCpnt->device->id * 8 +
+ (u8)(SCpnt->device->lun & 0x7), info->busyluns);
info->stats.removes += 1;
switch (SCpnt->cmnd[0]) {
init_SCp(SCpnt);
SCpnt->SCp.Message = 0;
SCpnt->SCp.Status = 0;
- SCpnt->tag = 0;
SCpnt->host_scribble = (void *)fas216_rq_sns_done;
/*
init_SCp(SCpnt);
info->stats.queues += 1;
- SCpnt->tag = 0;
spin_lock(&info->host_lock);
dev = &info->device[scd->id];
seq_printf(m, " %d/%llu ", scd->id, scd->lun);
if (scd->tagged_supported)
- seq_printf(m, "%3sabled(%3d) ",
- scd->simple_tags ? "en" : "dis",
- scd->current_tag);
+ seq_printf(m, "%3sabled ",
+ scd->simple_tags ? "en" : "dis");
else
seq_puts(m, "unsupported ");
list_for_each(l, &queue->head) {
QE_t *q = list_entry(l, QE_t, list);
if (q->SCpnt->device->id == target && q->SCpnt->device->lun == lun &&
- q->SCpnt->tag == tag) {
+ scsi_cmd_to_rq(q->SCpnt)->tag == tag) {
SCpnt = __queue_remove(queue, l);
break;
}
struct efct *efct = lio_vport->efct;
unsigned long flags = 0;
- spin_lock_irqsave(&efct->tgt_efct.efct_lio_lock, flags);
-
if (lio_vport->fc_vport)
fc_vport_terminate(lio_vport->fc_vport);
+ spin_lock_irqsave(&efct->tgt_efct.efct_lio_lock, flags);
+
list_for_each_entry_safe(vport, next_vport, &efct->tgt_efct.vport_list,
list_entry) {
if (vport->lio_vport == lio_vport) {
break;
case EFC_EVT_NPORT_TOPOLOGY_NOTIFY: {
- enum efc_nport_topology topology =
- (enum efc_nport_topology)arg;
+ enum efc_nport_topology *topology = arg;
WARN_ON(node->nport->domain->attached);
WARN_ON(node->send_ls_acc != EFC_NODE_SEND_LS_ACC_PLOGI);
node_printf(node, "topology notification, topology=%d\n",
- topology);
+ *topology);
/* At the time the PLOGI was received, the topology was unknown,
* so we didn't know which node would perform the domain attach:
* 1. The node from which the PLOGI was sent (p2p) or
* 2. The node to which the FLOGI was sent (fabric).
*/
- if (topology == EFC_NPORT_TOPO_P2P) {
+ if (*topology == EFC_NPORT_TOPO_P2P) {
/* if this is p2p, need to attach to the domain using
* the d_id from the PLOGI received
*/
efc_fabric_notify_topology(struct efc_node *node)
{
struct efc_node *tmp_node;
- enum efc_nport_topology topology = node->nport->topology;
unsigned long index;
/*
if (tmp_node != node) {
efc_node_post_event(tmp_node,
EFC_EVT_NPORT_TOPOLOGY_NOTIFY,
- (void *)topology);
+ &node->nport->topology);
}
}
}
"6312 Catching potential buffer "
"overflow > PAGE_SIZE = %lu bytes\n",
PAGE_SIZE);
- strscpy(buf + PAGE_SIZE - 1 -
- strnlen(LPFC_INFO_MORE_STR, PAGE_SIZE - 1),
- LPFC_INFO_MORE_STR,
- strnlen(LPFC_INFO_MORE_STR, PAGE_SIZE - 1)
- + 1);
+ strscpy(buf + PAGE_SIZE - 1 - sizeof(LPFC_INFO_MORE_STR),
+ LPFC_INFO_MORE_STR, sizeof(LPFC_INFO_MORE_STR) + 1);
}
return len;
}
len = scnprintf(buf, PAGE_SIZE, "SGL sz: %d total SGEs: %d\n",
phba->cfg_sg_dma_buf_size, phba->cfg_total_seg_cnt);
- len += scnprintf(buf + len, PAGE_SIZE, "Cfg: %d SCSI: %d NVME: %d\n",
+ len += scnprintf(buf + len, PAGE_SIZE - len,
+ "Cfg: %d SCSI: %d NVME: %d\n",
phba->cfg_sg_seg_cnt, phba->cfg_scsi_seg_cnt,
phba->cfg_nvme_seg_cnt);
return len;
be32_to_cpu(pcgd->desc_tag),
be32_to_cpu(pcgd->desc_len),
be32_to_cpu(pcgd->xmt_signal_capability),
- be32_to_cpu(pcgd->xmt_signal_frequency.count),
- be32_to_cpu(pcgd->xmt_signal_frequency.units),
+ be16_to_cpu(pcgd->xmt_signal_frequency.count),
+ be16_to_cpu(pcgd->xmt_signal_frequency.units),
be32_to_cpu(pcgd->rcv_signal_capability),
- be32_to_cpu(pcgd->rcv_signal_frequency.count),
- be32_to_cpu(pcgd->rcv_signal_frequency.units));
+ be16_to_cpu(pcgd->rcv_signal_frequency.count),
+ be16_to_cpu(pcgd->rcv_signal_frequency.units));
/* Compare driver and Fport capabilities and choose
* least common.
/* Extract the next WWPN from the payload */
wwn = *wwnlist++;
wwpn = be64_to_cpu(wwn);
- len += scnprintf(buf + len, LPFC_FPIN_WWPN_LINE_SZ,
+ len += scnprintf(buf + len, LPFC_FPIN_WWPN_LINE_SZ - len,
" %016llx", wwpn);
/* Log a message if we are on the last WWPN
#define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF
#define lpfc_mbx_rd_object_rlen_WORD word0
uint32_t rd_object_offset;
- uint32_t rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
+ __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
#define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */
uint32_t rd_object_cnt;
struct lpfc_mbx_host_buf rd_object_hbuf[4];
if (phba->cgn_fpin_frequency &&
phba->cgn_fpin_frequency != LPFC_FPIN_INIT_FREQ) {
value = LPFC_CGN_TIMER_TO_MIN / phba->cgn_fpin_frequency;
- cp->cgn_stat_npm = cpu_to_le32(value);
+ cp->cgn_stat_npm = value;
}
value = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ,
LPFC_CGN_CRC32_SEED);
uint32_t mbps;
uint32_t dvalue, wvalue, lvalue, avalue;
uint64_t latsum;
- uint16_t *ptr;
- uint32_t *lptr;
- uint16_t *mptr;
+ __le16 *ptr;
+ __le32 *lptr;
+ __le16 *mptr;
/* Make sure we have a congestion info buffer */
if (!phba->cgn_i)
if (phba->cgn_fpin_frequency &&
phba->cgn_fpin_frequency != LPFC_FPIN_INIT_FREQ) {
value = LPFC_CGN_TIMER_TO_MIN / phba->cgn_fpin_frequency;
- cp->cgn_stat_npm = cpu_to_le32(value);
+ cp->cgn_stat_npm = value;
}
/* Read and clear the latency counters for this minute */
dvalue += le32_to_cpu(cp->cgn_drvr_hr[i]);
wvalue += le32_to_cpu(cp->cgn_warn_hr[i]);
lvalue += le32_to_cpu(cp->cgn_latency_hr[i]);
- mbps += le32_to_cpu(cp->cgn_bw_hr[i]);
+ mbps += le16_to_cpu(cp->cgn_bw_hr[i]);
avalue += le32_to_cpu(cp->cgn_alarm_hr[i]);
}
if (lvalue) /* Avg of latency averages */
return 0;
out_free_hba_hdwq_info:
- free_percpu(phba->sli4_hba.c_stat);
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
+ free_percpu(phba->sli4_hba.c_stat);
out_free_hba_idle_stat:
- kfree(phba->sli4_hba.idle_stat);
#endif
+ kfree(phba->sli4_hba.idle_stat);
out_free_hba_eq_info:
free_percpu(phba->sli4_hba.eq_info);
out_free_hba_cpu_map:
/* last used Index initialized to 0xff already */
- cp->cgn_warn_freq = LPFC_FPIN_INIT_FREQ;
- cp->cgn_alarm_freq = LPFC_FPIN_INIT_FREQ;
+ cp->cgn_warn_freq = cpu_to_le16(LPFC_FPIN_INIT_FREQ);
+ cp->cgn_alarm_freq = cpu_to_le16(LPFC_FPIN_INIT_FREQ);
crc = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ, LPFC_CGN_CRC32_SEED);
cp->cgn_info_crc = cpu_to_le32(crc);
struct lpfc_nvme_qhandle *lpfc_queue_info;
struct lpfc_nvme_fcpreq_priv *freqpriv;
struct nvme_common_command *sqe;
-#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
uint64_t start = 0;
-#endif
/* Validate pointers. LLDD fault handling with transport does
* have timing races.
lpfc_bg_err_opcodes(struct lpfc_hba *phba, struct scsi_cmnd *sc,
uint8_t *txop, uint8_t *rxop)
{
- uint8_t ret = 0;
if (sc->prot_flags & SCSI_PROT_IP_CHECKSUM) {
switch (scsi_get_prot_op(sc)) {
}
}
- return ret;
+ return 0;
}
#endif
struct fc_rport *rport = starget_to_rport(scsi_target(cmnd->device));
int err, idx;
u8 *uuid = NULL;
-#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
- uint64_t start = 0L;
+ uint64_t start;
- if (phba->ktime_on)
- start = ktime_get_ns();
-#endif
start = ktime_get_ns();
rdata = lpfc_rport_data_from_scsi_device(cmnd->device);
uint32_t shdr_status, shdr_add_status;
union lpfc_sli4_cfg_shdr *shdr;
struct lpfc_dmabuf *pcmd;
+ u32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW] = {0};
/* sanity check on queue memory */
if (!datap)
memset((void *)read_object->u.request.rd_object_name, 0,
LPFC_OBJ_NAME_SZ);
- sprintf((uint8_t *)read_object->u.request.rd_object_name, rdobject);
+ scnprintf((char *)rd_object_name, sizeof(rd_object_name), rdobject);
for (j = 0; j < strlen(rdobject); j++)
read_object->u.request.rd_object_name[j] =
- cpu_to_le32(read_object->u.request.rd_object_name[j]);
+ cpu_to_le32(rd_object_name[j]);
pcmd = kmalloc(sizeof(*pcmd), GFP_KERNEL);
if (pcmd)
raid = MR_LdRaidGet(ld, local_map_ptr);
if (raid->capability.ldPiMode == MR_PROT_INFO_TYPE_CONTROLLER)
- blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
+ blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
mr_device_priv_data->is_tm_capable =
raid->capability.tmCapable;
if (instance->adapter_type != MFI_SERIES) {
megasas_release_fusion(instance);
- pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) +
+ pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) +
(sizeof(struct MR_PD_CFG_SEQ) *
(MAX_PHYSICAL_DEVICES - 1));
for (i = 0; i < 2 ; i++) {
if (event_type & SCAN_VD_CHANNEL) {
if (!instance->requestorId ||
- (instance->requestorId &&
- megasas_get_ld_vf_affiliation(instance, 0))) {
+ megasas_get_ld_vf_affiliation(instance, 0)) {
dcmd_ret = megasas_ld_list_query(instance,
MR_LD_QUERY_TYPE_EXPOSED_TO_HOST);
if (dcmd_ret != DCMD_SUCCESS)
* wait for current poll to complete.
*/
for (qid = 0; qid < iopoll_q_count; qid++) {
- while (atomic_read(&ioc->io_uring_poll_queues[qid].busy))
+ while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) {
+ cpu_relax();
udelay(500);
+ }
}
}
mpt3sas_check_cmd_timeout(ioc,
ioc->ctl_cmds.status, mpi_request,
sizeof(Mpi2DiagReleaseRequest_t)/4, reset_needed);
- *issue_reset = reset_needed;
+ *issue_reset = reset_needed;
rc = -EFAULT;
goto out;
}
case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
_scsih_pcie_topology_change_event(ioc, fw_event);
ioc->current_event = NULL;
- return;
- break;
+ return;
}
out:
fw_event_work_put(fw_event);
static void ncr_put_start_queue(struct ncb *np, struct ccb *cp);
static void insert_into_waiting_list(struct ncb *np, struct scsi_cmnd *cmd);
-static struct scsi_cmnd *retrieve_from_waiting_list(int to_remove, struct ncb *np, struct scsi_cmnd *cmd);
static void process_waiting_list(struct ncb *np, int sts);
-#define remove_from_waiting_list(np, cmd) \
- retrieve_from_waiting_list(1, (np), (cmd))
#define requeue_waiting_list(np) process_waiting_list((np), DID_OK)
#define reset_waiting_list(np) process_waiting_list((np), DID_RESET)
}
}
-static struct scsi_cmnd *retrieve_from_waiting_list(int to_remove, struct ncb *np, struct scsi_cmnd *cmd)
-{
- struct scsi_cmnd **pcmd = &np->waiting_list;
-
- while (*pcmd) {
- if (cmd == *pcmd) {
- if (to_remove) {
- *pcmd = (struct scsi_cmnd *) cmd->next_wcmd;
- cmd->next_wcmd = NULL;
- }
-#ifdef DEBUG_WAITING_LIST
- printk("%s: cmd %lx retrieved from waiting list\n", ncr_name(np), (u_long) cmd);
-#endif
- return cmd;
- }
- pcmd = (struct scsi_cmnd **) &(*pcmd)->next_wcmd;
- }
- return NULL;
-}
-
static void process_waiting_list(struct ncb *np, int sts)
{
struct scsi_cmnd *waiting_list, *wcmd;
return 0;
break;
case QLA2XXX_INI_MODE_DUAL:
- if (!qla_dual_mode_enabled(vha))
+ if (!qla_dual_mode_enabled(vha) &&
+ !qla_ini_mode_enabled(vha))
return 0;
break;
case QLA2XXX_INI_MODE_ENABLED:
struct iscsi_transport *t = iface->transport;
int param = -1;
- if (attr == &dev_attr_iface_enabled.attr)
- param = ISCSI_NET_PARAM_IFACE_ENABLE;
- else if (attr == &dev_attr_iface_def_taskmgmt_tmo.attr)
+ if (attr == &dev_attr_iface_def_taskmgmt_tmo.attr)
param = ISCSI_IFACE_PARAM_DEF_TASKMGMT_TMO;
else if (attr == &dev_attr_iface_header_digest.attr)
param = ISCSI_IFACE_PARAM_HDRDGST_EN;
if (param != -1)
return t->attr_is_visible(ISCSI_IFACE_PARAM, param);
- if (attr == &dev_attr_iface_vlan_id.attr)
+ if (attr == &dev_attr_iface_enabled.attr)
+ param = ISCSI_NET_PARAM_IFACE_ENABLE;
+ else if (attr == &dev_attr_iface_vlan_id.attr)
param = ISCSI_NET_PARAM_VLAN_ID;
else if (attr == &dev_attr_iface_vlan_priority.attr)
param = ISCSI_NET_PARAM_VLAN_PRIORITY;
retries = 0;
do {
+ bool media_was_present = sdkp->media_present;
+
cmd[0] = TEST_UNIT_READY;
memset((void *) &cmd[1], 0, 9);
* with any more polling.
*/
if (media_not_present(sdkp, &sshdr)) {
- sd_printk(KERN_NOTICE, sdkp, "Media removed, stopped polling\n");
+ if (media_was_present)
+ sd_printk(KERN_NOTICE, sdkp, "Media removed, stopped polling\n");
return;
}
}
device_initialize(&sdkp->dev);
- sdkp->dev.parent = dev;
+ sdkp->dev.parent = get_device(dev);
sdkp->dev.class = &sd_disk_class;
dev_set_name(&sdkp->dev, "%s", dev_name(dev));
error = device_add(&sdkp->dev);
- if (error)
- goto out_free_index;
+ if (error) {
+ put_device(&sdkp->dev);
+ goto out;
+ }
- get_device(dev);
dev_set_drvdata(dev, sdkp);
gd->major = sd_major((index & 0xf0) >> 4);
/*
* Report zone buffer size should be at most 64B times the number of
- * zones requested plus the 64B reply header, but should be at least
- * SECTOR_SIZE for ATA devices.
+ * zones requested plus the 64B reply header, but should be aligned
+ * to SECTOR_SIZE for ATA devices.
* Make sure that this size does not exceed the hardware capabilities.
* Furthermore, since the report zone command cannot be split, make
* sure that the allocated buffer can always be mapped by limiting the
*buflen = bufsize;
return buf;
}
- bufsize >>= 1;
+ bufsize = rounddown(bufsize >> 1, SECTOR_SIZE);
}
return NULL;
{
struct scsi_disk *sdkp;
unsigned long flags;
- unsigned int zno;
+ sector_t zno;
int ret;
sdkp = container_of(work, struct scsi_disk, zone_wp_offset_work);
0
};
unsigned char recv_page_code;
+ unsigned int retries = SES_RETRIES;
+ struct scsi_sense_hdr sshdr;
+
+ do {
+ ret = scsi_execute_req(sdev, cmd, DMA_FROM_DEVICE, buf, bufflen,
+ &sshdr, SES_TIMEOUT, 1, NULL);
+ } while (ret > 0 && --retries && scsi_sense_valid(&sshdr) &&
+ (sshdr.sense_key == NOT_READY ||
+ (sshdr.sense_key == UNIT_ATTENTION && sshdr.asc == 0x29)));
- ret = scsi_execute_req(sdev, cmd, DMA_FROM_DEVICE, buf, bufflen,
- NULL, SES_TIMEOUT, SES_RETRIES, NULL);
if (unlikely(ret))
return ret;
bufflen & 0xff,
0
};
+ struct scsi_sense_hdr sshdr;
+ unsigned int retries = SES_RETRIES;
+
+ do {
+ result = scsi_execute_req(sdev, cmd, DMA_TO_DEVICE, buf, bufflen,
+ &sshdr, SES_TIMEOUT, 1, NULL);
+ } while (result > 0 && --retries && scsi_sense_valid(&sshdr) &&
+ (sshdr.sense_key == NOT_READY ||
+ (sshdr.sense_key == UNIT_ATTENTION && sshdr.asc == 0x29)));
- result = scsi_execute_req(sdev, cmd, DMA_TO_DEVICE, buf, bufflen,
- NULL, SES_TIMEOUT, SES_RETRIES, NULL);
if (result)
sdev_printk(KERN_ERR, sdev, "SEND DIAGNOSTIC result: %8x\n",
result);
return rc;
cd->readcd_known = 0;
sr_printk(KERN_INFO, cd,
- "CDROM does'nt support READ CD (0xbe) command\n");
+ "CDROM doesn't support READ CD (0xbe) command\n");
/* fall & retry the other way */
}
/* ... if this fails, we switch the blocksize using MODE SELECT */
case CDROM_SEND_PACKET:
if (!capable(CAP_SYS_RAWIO))
return -EPERM;
+ break;
default:
break;
}
return err;
}
+static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes)
+{
+ struct ufs_pa_layer_attr pwr_info = hba->pwr_info;
+ int ret;
+
+ pwr_info.lane_rx = lanes;
+ pwr_info.lane_tx = lanes;
+ ret = ufshcd_config_pwr_mode(hba, &pwr_info);
+ if (ret)
+ dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n",
+ __func__, lanes, ret);
+ return ret;
+}
+
+static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status,
+ struct ufs_pa_layer_attr *dev_max_params,
+ struct ufs_pa_layer_attr *dev_req_params)
+{
+ int err = 0;
+
+ switch (status) {
+ case PRE_CHANGE:
+ if (ufshcd_is_hs_mode(dev_max_params) &&
+ (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2))
+ ufs_intel_set_lanes(hba, 2);
+ memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params));
+ break;
+ case POST_CHANGE:
+ if (ufshcd_is_hs_mode(dev_req_params)) {
+ u32 peer_granularity;
+
+ usleep_range(1000, 1250);
+ err = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
+ &peer_granularity);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return err;
+}
+
+static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba)
+{
+ u32 granularity, peer_granularity;
+ u32 pa_tactivate, peer_pa_tactivate;
+ int ret;
+
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &granularity);
+ if (ret)
+ goto out;
+
+ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &peer_granularity);
+ if (ret)
+ goto out;
+
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
+ if (ret)
+ goto out;
+
+ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &peer_pa_tactivate);
+ if (ret)
+ goto out;
+
+ if (granularity == peer_granularity) {
+ u32 new_peer_pa_tactivate = pa_tactivate + 2;
+
+ ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), new_peer_pa_tactivate);
+ }
+out:
+ return ret;
+}
+
#define INTEL_ACTIVELTR 0x804
#define INTEL_IDLELTR 0x808
struct ufs_host *ufs_host;
int err;
+ hba->nop_out_timeout = 200;
hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
hba->caps |= UFSHCD_CAP_CRYPTO;
err = ufs_intel_common_init(hba);
.exit = ufs_intel_common_exit,
.hce_enable_notify = ufs_intel_hce_enable_notify,
.link_startup_notify = ufs_intel_link_startup_notify,
+ .pwr_change_notify = ufs_intel_lkf_pwr_change_notify,
+ .apply_dev_quirks = ufs_intel_lkf_apply_dev_quirks,
.resume = ufs_intel_resume,
.device_reset = ufs_intel_device_reset,
};
#include <linux/blk-pm.h>
#include <linux/blkdev.h>
#include <scsi/scsi_driver.h>
-#include <scsi/scsi_transport.h>
-#include "../scsi_transport_api.h"
#include "ufshcd.h"
#include "ufs_quirks.h"
#include "unipro.h"
static irqreturn_t ufshcd_intr(int irq, void *__hba);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
+static void ufshcd_schedule_eh_work(struct ufs_hba *hba);
static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
out:
up_read(&hba->clk_scaling_lock);
- if (ufs_trigger_eh())
- scsi_schedule_eh(hba->host);
+ if (ufs_trigger_eh()) {
+ unsigned long flags;
+
+ spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_schedule_eh_work(hba);
+ spin_unlock_irqrestore(hba->host->host_lock, flags);
+ }
return err;
}
}
EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
-static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
-{
- lockdep_assert_held(hba->host->host_lock);
-
- return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
- (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
-}
-
-static void ufshcd_schedule_eh(struct ufs_hba *hba)
-{
- bool schedule_eh = false;
- unsigned long flags;
-
- spin_lock_irqsave(hba->host->host_lock, flags);
- /* handle fatal errors only when link is not in error state */
- if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
- if (hba->force_reset || ufshcd_is_link_broken(hba) ||
- ufshcd_is_saved_err_fatal(hba))
- hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
- else
- hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
- schedule_eh = true;
- }
- spin_unlock_irqrestore(hba->host->host_lock, flags);
-
- if (schedule_eh)
- scsi_schedule_eh(hba->host);
-}
-
/**
* ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
* state) and waits for it to take effect.
{
DECLARE_COMPLETION_ONSTACK(uic_async_done);
unsigned long flags;
- bool schedule_eh = false;
u8 status;
int ret;
bool reenable_intr = false;
ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
if (ret) {
ufshcd_set_link_broken(hba);
- schedule_eh = true;
+ ufshcd_schedule_eh_work(hba);
}
-
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
-
- if (schedule_eh)
- ufshcd_schedule_eh(hba);
mutex_unlock(&hba->uic_cmd_mutex);
return ret;
mutex_lock(&hba->dev_cmd.lock);
for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
- NOP_OUT_TIMEOUT);
+ hba->nop_out_timeout);
if (!err || err == -ETIMEDOUT)
break;
return err_handling;
}
+/* host lock must be held before calling this func */
+static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
+{
+ return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
+ (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
+}
+
+/* host lock must be held before calling this func */
+static inline void ufshcd_schedule_eh_work(struct ufs_hba *hba)
+{
+ /* handle fatal errors only when link is not in error state */
+ if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
+ if (hba->force_reset || ufshcd_is_link_broken(hba) ||
+ ufshcd_is_saved_err_fatal(hba))
+ hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
+ else
+ hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
+ queue_work(hba->eh_wq, &hba->eh_work);
+ }
+}
+
static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
{
down_write(&hba->clk_scaling_lock);
/**
* ufshcd_err_handler - handle UFS errors that require s/w attention
- * @host: SCSI host pointer
+ * @work: pointer to work structure
*/
-static void ufshcd_err_handler(struct Scsi_Host *host)
+static void ufshcd_err_handler(struct work_struct *work)
{
- struct ufs_hba *hba = shost_priv(host);
+ struct ufs_hba *hba;
unsigned long flags;
bool err_xfer = false;
bool err_tm = false;
int tag;
bool needs_reset = false, needs_restore = false;
+ hba = container_of(work, struct ufs_hba, eh_work);
+
down(&hba->host_sem);
spin_lock_irqsave(hba->host->host_lock, flags);
- hba->host->host_eh_scheduled = 0;
if (ufshcd_err_handling_should_stop(hba)) {
if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
"host_regs: ");
ufshcd_print_pwr_info(hba);
}
+ ufshcd_schedule_eh_work(hba);
retval |= IRQ_HANDLED;
}
/*
hba->errors = 0;
hba->uic_error = 0;
spin_unlock(hba->host->host_lock);
-
- if (queue_eh_work)
- ufshcd_schedule_eh(hba);
-
return retval;
}
err = ufshcd_clear_cmd(hba, pos);
if (err)
break;
- __ufshcd_transfer_req_compl(hba, pos, /*retry_requests=*/true);
+ __ufshcd_transfer_req_compl(hba, 1U << pos, false);
}
}
* will be to send LU reset which, again, is a spec violation.
* To avoid these unnecessary/illegal steps, first we clean up
* the lrb taken by this cmd and re-set it in outstanding_reqs,
- * then queue the error handler and bail.
+ * then queue the eh_work and bail.
*/
if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
spin_lock_irqsave(host->host_lock, flags);
hba->force_reset = true;
+ ufshcd_schedule_eh_work(hba);
spin_unlock_irqrestore(host->host_lock, flags);
-
- ufshcd_schedule_eh(hba);
-
goto release;
}
spin_lock_irqsave(hba->host->host_lock, flags);
hba->force_reset = true;
+ ufshcd_schedule_eh_work(hba);
dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
spin_unlock_irqrestore(hba->host->host_lock, flags);
- ufshcd_err_handler(hba->host);
+ flush_work(&hba->eh_work);
spin_lock_irqsave(hba->host->host_lock, flags);
if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
if (hba->is_powered) {
ufshcd_exit_clk_scaling(hba);
ufshcd_exit_clk_gating(hba);
+ if (hba->eh_wq)
+ destroy_workqueue(hba->eh_wq);
ufs_debugfs_hba_exit(hba);
ufshcd_variant_hba_exit(hba);
ufshcd_setup_vreg(hba, false);
return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
}
-static struct scsi_transport_template ufshcd_transport_template = {
- .eh_strategy_handler = ufshcd_err_handler,
-};
-
/**
* ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
* @dev: pointer to device handle
err = -ENOMEM;
goto out_error;
}
- host->transportt = &ufshcd_transport_template;
hba = shost_priv(host);
hba->host = host;
hba->dev = dev;
hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
+ hba->nop_out_timeout = NOP_OUT_TIMEOUT;
INIT_LIST_HEAD(&hba->clk_list_head);
spin_lock_init(&hba->outstanding_lock);
int err;
struct Scsi_Host *host = hba->host;
struct device *dev = hba->dev;
+ char eh_wq_name[sizeof("ufs_eh_wq_00")];
if (!mmio_base) {
dev_err(hba->dev,
hba->max_pwr_info.is_valid = false;
+ /* Initialize work queues */
+ snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
+ hba->host->host_no);
+ hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
+ if (!hba->eh_wq) {
+ dev_err(hba->dev, "%s: failed to create eh workqueue\n",
+ __func__);
+ err = -ENOMEM;
+ goto out_disable;
+ }
+ INIT_WORK(&hba->eh_work, ufshcd_err_handler);
INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
sema_init(&hba->host_sem, 1);
* @is_powered: flag to check if HBA is powered
* @shutting_down: flag to check if shutdown has been invoked
* @host_sem: semaphore used to serialize concurrent contexts
+ * @eh_wq: Workqueue that eh_work works on
+ * @eh_work: Worker to handle UFS errors that require s/w attention
* @eeh_work: Worker to handle exception events
* @errors: HBA errors
* @uic_error: UFS interconnect layer error status
struct semaphore host_sem;
/* Work Queues */
+ struct workqueue_struct *eh_wq;
+ struct work_struct eh_work;
struct work_struct eeh_work;
/* HBA Errors */
/* Device management request data */
struct ufs_dev_cmd dev_cmd;
ktime_t last_dme_cmd_tstamp;
+ int nop_out_timeout;
/* Keeps information of the UFS device connected to this host */
struct ufs_dev_info dev_info;
}
static void
-ufshpb_set_hpb_read_to_upiu(struct ufs_hba *hba, struct ufshpb_lu *hpb,
- struct ufshcd_lrb *lrbp, u32 lpn, __be64 ppn,
- u8 transfer_len, int read_id)
+ufshpb_set_hpb_read_to_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
+ __be64 ppn, u8 transfer_len, int read_id)
{
unsigned char *cdb = lrbp->cmd->cmnd;
__be64 ppn_tmp = ppn;
}
}
- ufshpb_set_hpb_read_to_upiu(hba, hpb, lrbp, lpn, ppn, transfer_len,
- read_id);
+ ufshpb_set_hpb_read_to_upiu(hba, lrbp, ppn, transfer_len, read_id);
hpb->stats.hit_cnt++;
return 0;
int ret;
bool use_dma;
+ /* Zero length transfers won't trigger an interrupt on completion */
+ if (!xfer->len) {
+ spi_finalize_current_transfer(ctlr);
+ return 1;
+ }
+
WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
struct dma_async_tx_descriptor *tx_dma_desc;
};
-static int tegra_slink_runtime_suspend(struct device *dev);
-static int tegra_slink_runtime_resume(struct device *dev);
-
static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
unsigned long reg)
{
}
#endif
+#ifdef CONFIG_PM
static int tegra_slink_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
}
return 0;
}
+#endif /* CONFIG_PM */
static const struct dev_pm_ops slink_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
const struct spi_device *spi = to_spi_device(dev);
int len;
- len = of_device_modalias(dev, buf, PAGE_SIZE);
- if (len != -ENODEV)
- return len;
-
len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1);
if (len != -ENODEV)
return len;
const struct spi_device *spi = to_spi_device(dev);
int rc;
- rc = of_device_uevent_modalias(dev, env);
- if (rc != -ENODEV)
- return rc;
-
rc = acpi_device_uevent_modalias(dev, env);
if (rc != -ENODEV)
return rc;
gbphy_runtime_put_autosuspend(gb_tty->gbphy_dev);
}
+static void gb_tty_port_destruct(struct tty_port *port)
+{
+ struct gb_tty *gb_tty = container_of(port, struct gb_tty, port);
+
+ if (gb_tty->minor != GB_NUM_MINORS)
+ release_minor(gb_tty);
+ kfifo_free(&gb_tty->write_fifo);
+ kfree(gb_tty->buffer);
+ kfree(gb_tty);
+}
+
static const struct tty_operations gb_ops = {
.install = gb_tty_install,
.open = gb_tty_open,
.dtr_rts = gb_tty_dtr_rts,
.activate = gb_tty_port_activate,
.shutdown = gb_tty_port_shutdown,
+ .destruct = gb_tty_port_destruct,
};
static int gb_uart_probe(struct gbphy_device *gbphy_dev,
int retval;
int minor;
- gb_tty = kzalloc(sizeof(*gb_tty), GFP_KERNEL);
- if (!gb_tty)
- return -ENOMEM;
-
connection = gb_connection_create(gbphy_dev->bundle,
le16_to_cpu(gbphy_dev->cport_desc->id),
gb_uart_request_handler);
- if (IS_ERR(connection)) {
- retval = PTR_ERR(connection);
- goto exit_tty_free;
- }
+ if (IS_ERR(connection))
+ return PTR_ERR(connection);
max_payload = gb_operation_get_payload_size_max(connection);
if (max_payload < sizeof(struct gb_uart_send_data_request)) {
goto exit_connection_destroy;
}
+ gb_tty = kzalloc(sizeof(*gb_tty), GFP_KERNEL);
+ if (!gb_tty) {
+ retval = -ENOMEM;
+ goto exit_connection_destroy;
+ }
+
+ tty_port_init(&gb_tty->port);
+ gb_tty->port.ops = &gb_port_ops;
+ gb_tty->minor = GB_NUM_MINORS;
+
gb_tty->buffer_payload_max = max_payload -
sizeof(struct gb_uart_send_data_request);
gb_tty->buffer = kzalloc(gb_tty->buffer_payload_max, GFP_KERNEL);
if (!gb_tty->buffer) {
retval = -ENOMEM;
- goto exit_connection_destroy;
+ goto exit_put_port;
}
INIT_WORK(&gb_tty->tx_work, gb_uart_tx_write_work);
retval = kfifo_alloc(&gb_tty->write_fifo, GB_UART_WRITE_FIFO_SIZE,
GFP_KERNEL);
if (retval)
- goto exit_buf_free;
+ goto exit_put_port;
gb_tty->credits = GB_UART_FIRMWARE_CREDITS;
init_completion(&gb_tty->credits_complete);
} else {
retval = minor;
}
- goto exit_kfifo_free;
+ goto exit_put_port;
}
gb_tty->minor = minor;
init_waitqueue_head(&gb_tty->wioctl);
mutex_init(&gb_tty->mutex);
- tty_port_init(&gb_tty->port);
- gb_tty->port.ops = &gb_port_ops;
-
gb_tty->connection = connection;
gb_tty->gbphy_dev = gbphy_dev;
gb_connection_set_data(connection, gb_tty);
retval = gb_connection_enable_tx(connection);
if (retval)
- goto exit_release_minor;
+ goto exit_put_port;
send_control(gb_tty, gb_tty->ctrlout);
exit_connection_disable:
gb_connection_disable(connection);
-exit_release_minor:
- release_minor(gb_tty);
-exit_kfifo_free:
- kfifo_free(&gb_tty->write_fifo);
-exit_buf_free:
- kfree(gb_tty->buffer);
+exit_put_port:
+ tty_port_put(&gb_tty->port);
exit_connection_destroy:
gb_connection_destroy(connection);
-exit_tty_free:
- kfree(gb_tty);
return retval;
}
gb_connection_disable_rx(connection);
tty_unregister_device(gb_tty_driver, gb_tty->minor);
- /* FIXME - free transmit / receive buffers */
-
gb_connection_disable(connection);
- tty_port_destroy(&gb_tty->port);
gb_connection_destroy(connection);
- release_minor(gb_tty);
- kfifo_free(&gb_tty->write_fifo);
- kfree(gb_tty->buffer);
- kfree(gb_tty);
+
+ tty_port_put(&gb_tty->port);
}
static int gb_tty_init(void)
pnext++;
if (*pnext != '\0') {
- strtout = simple_strtoul(pnext, &ptmp, 16);
- sprintf(extra, "%s %d", extra, strtout);
+ strtout = simple_strtoul(pnext, &ptmp, 16);
+ sprintf(extra + strlen(extra), " %d", strtout);
} else {
break;
}
pnext++;
if (*pnext != '\0') {
strtout = simple_strtoul(pnext, &ptmp, 16);
- sprintf(extra, "%s %d", extra, strtout);
+ sprintf(extra + strlen(extra), " %d", strtout);
} else {
break;
}
pnext++;
if (*pnext != '\0') {
strtou = simple_strtoul(pnext, &ptmp, 16);
- sprintf(extra, "%s %d", extra, strtou);
+ sprintf(extra + strlen(extra), " %d", strtou);
} else {
break;
}
{
struct se_dev_attrib *da = to_attrib(item);
struct se_device *dev = da->da_dev;
- bool flag;
+ bool flag, oldflag;
int ret;
+ ret = strtobool(page, &flag);
+ if (ret < 0)
+ return ret;
+
+ oldflag = !(dev->transport_flags & TRANSPORT_FLAG_PASSTHROUGH_ALUA);
+ if (flag == oldflag)
+ return count;
+
if (!(dev->transport->transport_flags_changeable &
TRANSPORT_FLAG_PASSTHROUGH_ALUA)) {
pr_err("dev[%p]: Unable to change SE Device alua_support:"
" alua_support has fixed value\n", dev);
- return -EINVAL;
+ return -ENOSYS;
}
- ret = strtobool(page, &flag);
- if (ret < 0)
- return ret;
-
if (flag)
dev->transport_flags &= ~TRANSPORT_FLAG_PASSTHROUGH_ALUA;
else
{
struct se_dev_attrib *da = to_attrib(item);
struct se_device *dev = da->da_dev;
- bool flag;
+ bool flag, oldflag;
int ret;
+ ret = strtobool(page, &flag);
+ if (ret < 0)
+ return ret;
+
+ oldflag = !(dev->transport_flags & TRANSPORT_FLAG_PASSTHROUGH_PGR);
+ if (flag == oldflag)
+ return count;
+
if (!(dev->transport->transport_flags_changeable &
TRANSPORT_FLAG_PASSTHROUGH_PGR)) {
pr_err("dev[%p]: Unable to change SE Device pgr_support:"
" pgr_support has fixed value\n", dev);
- return -EINVAL;
+ return -ENOSYS;
}
- ret = strtobool(page, &flag);
- if (ret < 0)
- return ret;
-
if (flag)
dev->transport_flags &= ~TRANSPORT_FLAG_PASSTHROUGH_PGR;
else
spin_lock(&dev->dev_reservation_lock);
if (dev->reservation_holder &&
dev->reservation_holder->se_node_acl != sess->se_node_acl) {
- pr_err("SCSI-2 RESERVATION CONFLIFT for %s fabric\n",
+ pr_err("SCSI-2 RESERVATION CONFLICT for %s fabric\n",
tpg->se_tpg_tfo->fabric_name);
pr_err("Original reserver LUN: %llu %s\n",
cmd->se_lun->unpacked_lun,
return 0;
}
-static unsigned int tcc_offset_save;
+static int tcc_offset_save = -1;
static ssize_t tcc_offset_degree_celsius_store(struct device *dev,
struct device_attribute *attr, const char *buf,
proc_dev = dev_get_drvdata(dev);
proc_thermal_read_ppcc(proc_dev);
- tcc_offset_update(tcc_offset_save);
+ if (tcc_offset_save >= 0)
+ tcc_offset_update(tcc_offset_save);
return 0;
}
const struct tsens_sensor *s = &priv->sensor[i];
u32 hw_id = s->hw_id;
- if (IS_ERR(s->tzd))
+ if (!s->tzd)
continue;
if (!tsens_threshold_violated(priv, hw_id, &d))
continue;
const struct tsens_sensor *s = &priv->sensor[i];
u32 hw_id = s->hw_id;
- if (IS_ERR(s->tzd))
+ if (!s->tzd)
continue;
if (!tsens_threshold_violated(priv, hw_id, &d))
continue;
{
struct thermal_governor *pos;
ssize_t count = 0;
- ssize_t size = PAGE_SIZE;
mutex_lock(&thermal_governor_lock);
list_for_each_entry(pos, &thermal_governor_list, governor_list) {
- size = PAGE_SIZE - count;
- count += scnprintf(buf + count, size, "%s ", pos->name);
+ count += scnprintf(buf + count, PAGE_SIZE - count, "%s ",
+ pos->name);
}
- count += scnprintf(buf + count, size, "\n");
+ count += scnprintf(buf + count, PAGE_SIZE - count, "\n");
mutex_unlock(&thermal_governor_lock);
#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
/* RX FIFO occupancy indicator */
-#define UART_OMAP_RX_LVL 0x64
+#define UART_OMAP_RX_LVL 0x19
struct omap8250_priv {
int line;
st = readl(port->membase + UART_STAT);
spin_unlock_irqrestore(&port->lock, flags);
- return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
+ return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
}
static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
static void tdma_reset(struct slgt_info *info);
static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
-static void get_signals(struct slgt_info *info);
-static void set_signals(struct slgt_info *info);
+static void get_gtsignals(struct slgt_info *info);
+static void set_gtsignals(struct slgt_info *info);
static void set_rate(struct slgt_info *info, u32 data_rate);
static void bh_transmit(struct slgt_info *info);
if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
spin_lock_irqsave(&info->lock,flags);
- set_signals(info);
+ set_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
}
if (!C_CRTSCTS(tty) || !tty_throttled(tty))
info->signals |= SerialSignal_RTS;
spin_lock_irqsave(&info->lock,flags);
- set_signals(info);
+ set_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
}
/* output current serial signal states */
spin_lock_irqsave(&info->lock,flags);
- get_signals(info);
+ get_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
stat_buf[0] = 0;
if (C_CRTSCTS(tty)) {
spin_lock_irqsave(&info->lock,flags);
info->signals &= ~SerialSignal_RTS;
- set_signals(info);
+ set_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
}
}
if (C_CRTSCTS(tty)) {
spin_lock_irqsave(&info->lock,flags);
info->signals |= SerialSignal_RTS;
- set_signals(info);
+ set_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
}
}
/* inform generic HDLC layer of current DCD status */
spin_lock_irqsave(&info->lock, flags);
- get_signals(info);
+ get_gtsignals(info);
spin_unlock_irqrestore(&info->lock, flags);
if (info->signals & SerialSignal_DCD)
netif_carrier_on(dev);
if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
info->signals &= ~SerialSignal_RTS;
info->drop_rts_on_tx_done = false;
- set_signals(info);
+ set_gtsignals(info);
}
#if SYNCLINK_GENERIC_HDLC
if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
- set_signals(info);
+ set_gtsignals(info);
}
flush_cond_wait(&info->gpio_wait_q);
else
async_mode(info);
- set_signals(info);
+ set_gtsignals(info);
info->dcd_chkcount = 0;
info->cts_chkcount = 0;
info->dsr_chkcount = 0;
slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
- get_signals(info);
+ get_gtsignals(info);
if (info->netcount ||
(info->port.tty && info->port.tty->termios.c_cflag & CREAD))
spin_lock_irqsave(&info->lock,flags);
/* return immediately if state matches requested events */
- get_signals(info);
+ get_gtsignals(info);
s = info->signals;
events = mask &
unsigned long flags;
spin_lock_irqsave(&info->lock,flags);
- get_signals(info);
+ get_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
info->signals &= ~SerialSignal_DTR;
spin_lock_irqsave(&info->lock,flags);
- set_signals(info);
+ set_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
return 0;
}
struct slgt_info *info = container_of(port, struct slgt_info, port);
spin_lock_irqsave(&info->lock,flags);
- get_signals(info);
+ get_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
return (info->signals & SerialSignal_DCD) ? 1 : 0;
}
info->signals |= SerialSignal_RTS | SerialSignal_DTR;
else
info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
- set_signals(info);
+ set_gtsignals(info);
spin_unlock_irqrestore(&info->lock,flags);
}
if (info->params.mode != MGSL_MODE_ASYNC) {
if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
- get_signals(info);
+ get_gtsignals(info);
if (!(info->signals & SerialSignal_RTS)) {
info->signals |= SerialSignal_RTS;
- set_signals(info);
+ set_gtsignals(info);
info->drop_rts_on_tx_done = true;
}
}
rx_stop(info);
info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
- set_signals(info);
+ set_gtsignals(info);
slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
}
/*
* get state of V24 status (input) signals
*/
-static void get_signals(struct slgt_info *info)
+static void get_gtsignals(struct slgt_info *info)
{
unsigned short status = rd_reg16(info, SSR);
/*
* set state of V24 control (output) signals
*/
-static void set_signals(struct slgt_info *info)
+static void set_gtsignals(struct slgt_info *info)
{
unsigned char val = rd_reg8(info, VCR);
if (info->signals & SerialSignal_DTR)
tty_ldisc_debug(tty, "released\n");
}
-EXPORT_SYMBOL_GPL(tty_ldisc_release);
/**
* tty_ldisc_init - ldisc setup for new tty
return 0;
}
+static void cdns3_rearm_drdy_if_needed(struct cdns3_endpoint *priv_ep)
+{
+ struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
+
+ if (priv_dev->dev_ver < DEV_VER_V3)
+ return;
+
+ if (readl(&priv_dev->regs->ep_sts) & EP_STS_TRBERR) {
+ writel(EP_STS_TRBERR, &priv_dev->regs->ep_sts);
+ writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
+ }
+}
+
/**
* cdns3_ep_run_transfer - start transfer on no-default endpoint hardware
* @priv_ep: endpoint object
/*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
+ cdns3_rearm_drdy_if_needed(priv_ep);
trace_cdns3_doorbell_epx(priv_ep->name,
readl(&priv_dev->regs->ep_traddr));
}
{
struct acm *acm = container_of(port, struct acm, port);
- acm_release_minor(acm);
+ if (acm->minor != ACM_MINOR_INVALID)
+ acm_release_minor(acm);
usb_put_intf(acm->control);
kfree(acm->country_codes);
kfree(acm);
usb_get_intf(acm->control); /* undone in destruct() */
minor = acm_alloc_minor(acm);
- if (minor < 0)
+ if (minor < 0) {
+ acm->minor = ACM_MINOR_INVALID;
goto err_put_port;
+ }
acm->minor = minor;
acm->dev = usb_dev;
#define ACM_TTY_MAJOR 166
#define ACM_TTY_MINORS 256
+#define ACM_MINOR_INVALID ACM_TTY_MINORS
+
/*
* Requests.
*/
}
/**
+ * usb_stop_hcd - Halt the HCD
+ * @hcd: the usb_hcd that has to be halted
+ *
+ * Stop the root-hub polling timer and invoke the HCD's ->stop callback.
+ */
+static void usb_stop_hcd(struct usb_hcd *hcd)
+{
+ hcd->rh_pollable = 0;
+ clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+ del_timer_sync(&hcd->rh_timer);
+
+ hcd->driver->stop(hcd);
+ hcd->state = HC_STATE_HALT;
+
+ /* In case the HCD restarted the timer, stop it again. */
+ clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+ del_timer_sync(&hcd->rh_timer);
+}
+
+/**
* usb_add_hcd - finish generic HCD structure initialization and register
* @hcd: the usb_hcd structure to initialize
* @irqnum: Interrupt line to allocate
{
int retval;
struct usb_device *rhdev;
+ struct usb_hcd *shared_hcd;
if (!hcd->skip_phy_initialization && usb_hcd_is_primary_hcd(hcd)) {
hcd->phy_roothub = usb_phy_roothub_alloc(hcd->self.sysdev);
goto err_hcd_driver_start;
}
+ /* starting here, usbcore will pay attention to the shared HCD roothub */
+ shared_hcd = hcd->shared_hcd;
+ if (!usb_hcd_is_primary_hcd(hcd) && shared_hcd && HCD_DEFER_RH_REGISTER(shared_hcd)) {
+ retval = register_root_hub(shared_hcd);
+ if (retval != 0)
+ goto err_register_root_hub;
+
+ if (shared_hcd->uses_new_polling && HCD_POLL_RH(shared_hcd))
+ usb_hcd_poll_rh_status(shared_hcd);
+ }
+
/* starting here, usbcore will pay attention to this root hub */
- retval = register_root_hub(hcd);
- if (retval != 0)
- goto err_register_root_hub;
+ if (!HCD_DEFER_RH_REGISTER(hcd)) {
+ retval = register_root_hub(hcd);
+ if (retval != 0)
+ goto err_register_root_hub;
- if (hcd->uses_new_polling && HCD_POLL_RH(hcd))
- usb_hcd_poll_rh_status(hcd);
+ if (hcd->uses_new_polling && HCD_POLL_RH(hcd))
+ usb_hcd_poll_rh_status(hcd);
+ }
return retval;
err_register_root_hub:
- hcd->rh_pollable = 0;
- clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- del_timer_sync(&hcd->rh_timer);
- hcd->driver->stop(hcd);
- hcd->state = HC_STATE_HALT;
- clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- del_timer_sync(&hcd->rh_timer);
+ usb_stop_hcd(hcd);
err_hcd_driver_start:
if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
free_irq(irqnum, hcd);
void usb_remove_hcd(struct usb_hcd *hcd)
{
struct usb_device *rhdev = hcd->self.root_hub;
+ bool rh_registered;
dev_info(hcd->self.controller, "remove, state %x\n", hcd->state);
dev_dbg(hcd->self.controller, "roothub graceful disconnect\n");
spin_lock_irq (&hcd_root_hub_lock);
+ rh_registered = hcd->rh_registered;
hcd->rh_registered = 0;
spin_unlock_irq (&hcd_root_hub_lock);
cancel_work_sync(&hcd->died_work);
mutex_lock(&usb_bus_idr_lock);
- usb_disconnect(&rhdev); /* Sets rhdev to NULL */
+ if (rh_registered)
+ usb_disconnect(&rhdev); /* Sets rhdev to NULL */
mutex_unlock(&usb_bus_idr_lock);
/*
* interrupt occurs), but usb_hcd_poll_rh_status() won't invoke
* the hub_status_data() callback.
*/
- hcd->rh_pollable = 0;
- clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- del_timer_sync(&hcd->rh_timer);
-
- hcd->driver->stop(hcd);
- hcd->state = HC_STATE_HALT;
-
- /* In case the HCD restarted the timer, stop it again. */
- clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- del_timer_sync(&hcd->rh_timer);
+ usb_stop_hcd(hcd);
if (usb_hcd_is_primary_hcd(hcd)) {
if (hcd->irq > 0)
*/
static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
{
+ struct dwc2_hsotg *hsotg = hs_ep->parent;
+ u16 limit = DSTS_SOFFN_LIMIT;
+
+ if (hsotg->gadget.speed != USB_SPEED_HIGH)
+ limit >>= 3;
+
hs_ep->target_frame += hs_ep->interval;
- if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
+ if (hs_ep->target_frame > limit) {
hs_ep->frame_overrun = true;
- hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
+ hs_ep->target_frame &= limit;
} else {
hs_ep->frame_overrun = false;
}
*/
static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
{
+ struct dwc2_hsotg *hsotg = hs_ep->parent;
+ u16 limit = DSTS_SOFFN_LIMIT;
+
+ if (hsotg->gadget.speed != USB_SPEED_HIGH)
+ limit >>= 3;
+
if (hs_ep->target_frame)
hs_ep->target_frame -= 1;
else
- hs_ep->target_frame = DSTS_SOFFN_LIMIT;
+ hs_ep->target_frame = limit;
}
/**
dwc2_writel(hsotg, ctrl, depctl);
}
+static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
+static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
+ struct dwc2_hsotg_ep *hs_ep,
+ struct dwc2_hsotg_req *hs_req,
+ int result);
+
/**
* dwc2_hsotg_start_req - start a USB request from an endpoint's queue
* @hsotg: The controller state.
}
}
- if (hs_ep->isochronous && hs_ep->interval == 1) {
- hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
- dwc2_gadget_incr_frame_num(hs_ep);
-
- if (hs_ep->target_frame & 0x1)
- ctrl |= DXEPCTL_SETODDFR;
- else
- ctrl |= DXEPCTL_SETEVENFR;
+ if (hs_ep->isochronous) {
+ if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
+ if (hs_ep->interval == 1) {
+ if (hs_ep->target_frame & 0x1)
+ ctrl |= DXEPCTL_SETODDFR;
+ else
+ ctrl |= DXEPCTL_SETEVENFR;
+ }
+ ctrl |= DXEPCTL_CNAK;
+ } else {
+ dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
+ return;
+ }
}
ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
u32 target_frame = hs_ep->target_frame;
u32 current_frame = hsotg->frame_number;
bool frame_overrun = hs_ep->frame_overrun;
+ u16 limit = DSTS_SOFFN_LIMIT;
+
+ if (hsotg->gadget.speed != USB_SPEED_HIGH)
+ limit >>= 3;
if (!frame_overrun && current_frame >= target_frame)
return true;
if (frame_overrun && current_frame >= target_frame &&
- ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
+ ((current_frame - target_frame) < limit / 2))
return true;
return false;
*/
static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
{
- u32 mask;
struct dwc2_hsotg *hsotg = hs_ep->parent;
int dir_in = hs_ep->dir_in;
struct dwc2_hsotg_req *hs_req;
- u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
if (!list_empty(&hs_ep->queue)) {
hs_req = get_ep_head(hs_ep);
} else {
dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
__func__);
- mask = dwc2_readl(hsotg, epmsk_reg);
- mask |= DOEPMSK_OUTTKNEPDISMSK;
- dwc2_writel(hsotg, mask, epmsk_reg);
}
}
dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
}
-static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
- u32 epctl_reg)
-{
- u32 ctrl;
-
- ctrl = dwc2_readl(hsotg, epctl_reg);
- if (ctrl & DXEPCTL_EOFRNUM)
- ctrl |= DXEPCTL_SETEVENFR;
- else
- ctrl |= DXEPCTL_SETODDFR;
- dwc2_writel(hsotg, ctrl, epctl_reg);
-}
-
/*
* dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
* @hs_ep - The endpoint on which transfer went
dwc2_hsotg_ep0_zlp(hsotg, true);
}
- /*
- * Slave mode OUT transfers do not go through XferComplete so
- * adjust the ISOC parity here.
- */
- if (!using_dma(hsotg)) {
- if (hs_ep->isochronous && hs_ep->interval == 1)
- dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
- else if (hs_ep->isochronous && hs_ep->interval > 1)
- dwc2_gadget_incr_frame_num(hs_ep);
- }
-
/* Set actual frame number for completed transfers */
- if (!using_desc_dma(hsotg) && hs_ep->isochronous)
- req->frame_number = hsotg->frame_number;
+ if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
+ req->frame_number = hs_ep->target_frame;
+ dwc2_gadget_incr_frame_num(hs_ep);
+ }
dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
}
return;
}
+ /* Set actual frame number for completed transfers */
+ if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
+ hs_req->req.frame_number = hs_ep->target_frame;
+ dwc2_gadget_incr_frame_num(hs_ep);
+ }
+
dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
}
dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
- if (hs_ep->isochronous) {
- dwc2_hsotg_complete_in(hsotg, hs_ep);
- return;
- }
-
if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
int dctl = dwc2_readl(hsotg, DCTL);
dctl |= DCTL_CGNPINNAK;
dwc2_writel(hsotg, dctl, DCTL);
}
- return;
- }
+ } else {
- if (dctl & DCTL_GOUTNAKSTS) {
- dctl |= DCTL_CGOUTNAK;
- dwc2_writel(hsotg, dctl, DCTL);
+ if (dctl & DCTL_GOUTNAKSTS) {
+ dctl |= DCTL_CGOUTNAK;
+ dwc2_writel(hsotg, dctl, DCTL);
+ }
}
if (!hs_ep->isochronous)
/* Update current frame number value. */
hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
} while (dwc2_gadget_target_frame_elapsed(hs_ep));
-
- dwc2_gadget_start_next_request(hs_ep);
}
/**
static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
{
struct dwc2_hsotg *hsotg = ep->parent;
+ struct dwc2_hsotg_req *hs_req;
int dir_in = ep->dir_in;
- u32 doepmsk;
if (dir_in || !ep->isochronous)
return;
return;
}
- if (ep->interval > 1 &&
- ep->target_frame == TARGET_FRAME_INITIAL) {
+ if (ep->target_frame == TARGET_FRAME_INITIAL) {
u32 ctrl;
ep->target_frame = hsotg->frame_number;
- dwc2_gadget_incr_frame_num(ep);
+ if (ep->interval > 1) {
+ ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
+ if (ep->target_frame & 0x1)
+ ctrl |= DXEPCTL_SETODDFR;
+ else
+ ctrl |= DXEPCTL_SETEVENFR;
- ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
- if (ep->target_frame & 0x1)
- ctrl |= DXEPCTL_SETODDFR;
- else
- ctrl |= DXEPCTL_SETEVENFR;
+ dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
+ }
+ }
+
+ while (dwc2_gadget_target_frame_elapsed(ep)) {
+ hs_req = get_ep_head(ep);
+ if (hs_req)
+ dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
- dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
+ dwc2_gadget_incr_frame_num(ep);
+ /* Update current frame number value. */
+ hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
}
- dwc2_gadget_start_next_request(ep);
- doepmsk = dwc2_readl(hsotg, DOEPMSK);
- doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
- dwc2_writel(hsotg, doepmsk, DOEPMSK);
+ if (!ep->req)
+ dwc2_gadget_start_next_request(ep);
+
}
+static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
+ struct dwc2_hsotg_ep *hs_ep);
+
/**
* dwc2_gadget_handle_nak - handle NAK interrupt
* @hs_ep: The endpoint on which interrupt is asserted.
static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
{
struct dwc2_hsotg *hsotg = hs_ep->parent;
+ struct dwc2_hsotg_req *hs_req;
int dir_in = hs_ep->dir_in;
+ u32 ctrl;
if (!dir_in || !hs_ep->isochronous)
return;
dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
}
-
- dwc2_hsotg_complete_request(hsotg, hs_ep,
- get_ep_head(hs_ep), 0);
}
- if (!using_desc_dma(hsotg))
+ if (using_desc_dma(hsotg))
+ return;
+
+ ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
+ if (ctrl & DXEPCTL_EPENA)
+ dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
+ else
+ dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
+
+ while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
+ hs_req = get_ep_head(hs_ep);
+ if (hs_req)
+ dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
+
dwc2_gadget_incr_frame_num(hs_ep);
+ /* Update current frame number value. */
+ hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
+ }
+
+ if (!hs_ep->req)
+ dwc2_gadget_start_next_request(hs_ep);
}
/**
/* In DDMA handle isochronous requests separately */
if (using_desc_dma(hsotg) && hs_ep->isochronous) {
- /* XferCompl set along with BNA */
- if (!(ints & DXEPINT_BNAINTR))
- dwc2_gadget_complete_isoc_request_ddma(hs_ep);
+ dwc2_gadget_complete_isoc_request_ddma(hs_ep);
} else if (dir_in) {
/*
* We get OutDone from the FIFO, so we only
* need to look at completing IN requests here
* if operating slave mode
*/
- if (hs_ep->isochronous && hs_ep->interval > 1)
- dwc2_gadget_incr_frame_num(hs_ep);
-
- dwc2_hsotg_complete_in(hsotg, hs_ep);
- if (ints & DXEPINT_NAKINTRPT)
- ints &= ~DXEPINT_NAKINTRPT;
+ if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
+ dwc2_hsotg_complete_in(hsotg, hs_ep);
if (idx == 0 && !hs_ep->req)
dwc2_hsotg_enqueue_setup(hsotg);
* We're using DMA, we need to fire an OutDone here
* as we ignore the RXFIFO.
*/
- if (hs_ep->isochronous && hs_ep->interval > 1)
- dwc2_gadget_incr_frame_num(hs_ep);
-
- dwc2_hsotg_handle_outdone(hsotg, idx);
+ if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
+ dwc2_hsotg_handle_outdone(hsotg, idx);
}
}
mask |= DIEPMSK_NAKMSK;
dwc2_writel(hsotg, mask, DIEPMSK);
} else {
+ epctrl |= DXEPCTL_SNAK;
mask = dwc2_readl(hsotg, DOEPMSK);
mask |= DOEPMSK_OUTTKNEPDISMSK;
dwc2_writel(hsotg, mask, DOEPMSK);
hcd->has_tt = 1;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ retval = -EINVAL;
+ goto error1;
+ }
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
{
u32 reg;
int retries = 1000;
- int ret;
-
- usb_phy_init(dwc->usb2_phy);
- usb_phy_init(dwc->usb3_phy);
- ret = phy_init(dwc->usb2_generic_phy);
- if (ret < 0)
- return ret;
-
- ret = phy_init(dwc->usb3_generic_phy);
- if (ret < 0) {
- phy_exit(dwc->usb2_generic_phy);
- return ret;
- }
/*
* We're resetting only the device side because, if we're in host mode,
udelay(1);
} while (--retries);
- phy_exit(dwc->usb3_generic_phy);
- phy_exit(dwc->usb2_generic_phy);
-
return -ETIMEDOUT;
done:
dwc->phys_ready = true;
}
+ usb_phy_init(dwc->usb2_phy);
+ usb_phy_init(dwc->usb3_phy);
+ ret = phy_init(dwc->usb2_generic_phy);
+ if (ret < 0)
+ goto err0a;
+
+ ret = phy_init(dwc->usb3_generic_phy);
+ if (ret < 0) {
+ phy_exit(dwc->usb2_generic_phy);
+ goto err0a;
+ }
+
ret = dwc3_core_soft_reset(dwc);
if (ret)
- goto err0a;
+ goto err1;
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
.bInterval = 4,
};
+static struct usb_ss_ep_comp_descriptor ss_epin_fback_desc_comp = {
+ .bLength = sizeof(ss_epin_fback_desc_comp),
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+ .bMaxBurst = 0,
+ .bmAttributes = 0,
+ .wBytesPerInterval = cpu_to_le16(4),
+};
+
/* Audio Streaming IN Interface - Alt0 */
static struct usb_interface_descriptor std_as_in_if0_desc = {
(struct usb_descriptor_header *)&ss_epout_desc_comp,
(struct usb_descriptor_header *)&as_iso_out_desc,
(struct usb_descriptor_header *)&ss_epin_fback_desc,
+ (struct usb_descriptor_header *)&ss_epin_fback_desc_comp,
(struct usb_descriptor_header *)&std_as_in_if0_desc,
(struct usb_descriptor_header *)&std_as_in_if1_desc,
{
struct usb_ss_ep_comp_descriptor *epout_desc_comp = NULL;
struct usb_ss_ep_comp_descriptor *epin_desc_comp = NULL;
+ struct usb_ss_ep_comp_descriptor *epin_fback_desc_comp = NULL;
struct usb_endpoint_descriptor *epout_desc;
struct usb_endpoint_descriptor *epin_desc;
struct usb_endpoint_descriptor *epin_fback_desc;
epout_desc_comp = &ss_epout_desc_comp;
epin_desc_comp = &ss_epin_desc_comp;
epin_fback_desc = &ss_epin_fback_desc;
+ epin_fback_desc_comp = &ss_epin_fback_desc_comp;
ep_int_desc = &ss_ep_int_desc;
}
headers[i++] = USBDHDR(&as_iso_out_desc);
- if (EPOUT_FBACK_IN_EN(opts))
+ if (EPOUT_FBACK_IN_EN(opts)) {
headers[i++] = USBDHDR(epin_fback_desc);
+ if (epin_fback_desc_comp)
+ headers[i++] = USBDHDR(epin_fback_desc_comp);
+ }
}
if (EPIN_EN(opts)) {
agdev->out_ep_maxpsize = max_t(u16, agdev->out_ep_maxpsize,
le16_to_cpu(ss_epout_desc.wMaxPacketSize));
+ ss_epin_desc_comp.wBytesPerInterval = ss_epin_desc.wMaxPacketSize;
+ ss_epout_desc_comp.wBytesPerInterval = ss_epout_desc.wMaxPacketSize;
+
// HS and SS endpoint addresses are copied from autoconfigured FS descriptors
hs_ep_int_desc.bEndpointAddress = fs_ep_int_desc.bEndpointAddress;
hs_epout_desc.bEndpointAddress = fs_epout_desc.bEndpointAddress;
};
static void u_audio_set_fback_frequency(enum usb_device_speed speed,
+ struct usb_ep *out_ep,
unsigned long long freq,
unsigned int pitch,
void *buf)
{
u32 ff = 0;
+ const struct usb_endpoint_descriptor *ep_desc;
/*
* Because the pitch base is 1000000, the final divider here
* byte fromat (that is Q16.16)
*
* ff = (freq << 16) / 8000
+ *
+ * Win10 and OSX UAC2 drivers require number of samples per packet
+ * in order to honor the feedback value.
+ * Linux snd-usb-audio detects the applied bit-shift automatically.
*/
- freq <<= 4;
+ ep_desc = out_ep->desc;
+ freq <<= 4 + (ep_desc->bInterval - 1);
}
ff = DIV_ROUND_CLOSEST_ULL((freq * pitch), 1953125);
pr_debug("%s: iso_complete status(%d) %d/%d\n",
__func__, status, req->actual, req->length);
- u_audio_set_fback_frequency(audio_dev->gadget->speed,
+ u_audio_set_fback_frequency(audio_dev->gadget->speed, audio_dev->out_ep,
params->c_srate, prm->pitch,
req->buf);
* be meauserd at start of playback
*/
prm->pitch = 1000000;
- u_audio_set_fback_frequency(audio_dev->gadget->speed,
+ u_audio_set_fback_frequency(audio_dev->gadget->speed, ep,
params->c_srate, prm->pitch,
req_fback->buf);
do {
tmp = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
udelay(1);
- } while (tmp != CS_IDST || timeout-- > 0);
+ } while (tmp != CS_IDST && timeout-- > 0);
if (tmp == CS_IDST)
r8a66597_bset(r8a66597,
return -ENOMEM;
usb_dev->core = core;
- if (core->dev.of_node) {
+ if (core->dev.of_node)
usb_dev->gpio_desc = devm_gpiod_get(&core->dev, "vcc",
GPIOD_OUT_HIGH);
- if (IS_ERR(usb_dev->gpio_desc))
- return PTR_ERR(usb_dev->gpio_desc);
- }
switch (core->id.id) {
case BCMA_CORE_USB20_HOST:
#include <linux/moduleparam.h>
#include <linux/dma-mapping.h>
#include <linux/debugfs.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#ifdef CONFIG_USB_EHCI_SH
#include "ehci-sh.c"
-#define PLATFORM_DRIVER ehci_hcd_sh_driver
#endif
#ifdef CONFIG_PPC_PS3
#include "ehci-ps3.c"
-#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
#endif
#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
#include "ehci-ppc-of.c"
-#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
#endif
#ifdef CONFIG_XPS_USB_HCD_XILINX
#include "ehci-xilinx-of.c"
-#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
#endif
#ifdef CONFIG_SPARC_LEON
#include "ehci-grlib.c"
-#define PLATFORM_DRIVER ehci_grlib_driver
#endif
+static struct platform_driver * const platform_drivers[] = {
+#ifdef CONFIG_USB_EHCI_SH
+ &ehci_hcd_sh_driver,
+#endif
+#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
+ &ehci_hcd_ppc_of_driver,
+#endif
+#ifdef CONFIG_XPS_USB_HCD_XILINX
+ &ehci_hcd_xilinx_of_driver,
+#endif
+#ifdef CONFIG_SPARC_LEON
+ &ehci_grlib_driver,
+#endif
+};
+
static int __init ehci_hcd_init(void)
{
int retval = 0;
ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
#endif
-#ifdef PLATFORM_DRIVER
- retval = platform_driver_register(&PLATFORM_DRIVER);
+ retval = platform_register_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
if (retval < 0)
goto clean0;
-#endif
-
-#ifdef PS3_SYSTEM_BUS_DRIVER
- retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
- if (retval < 0)
- goto clean2;
-#endif
-#ifdef OF_PLATFORM_DRIVER
- retval = platform_driver_register(&OF_PLATFORM_DRIVER);
+#ifdef CONFIG_PPC_PS3
+ retval = ps3_ehci_driver_register(&ps3_ehci_driver);
if (retval < 0)
- goto clean3;
+ goto clean1;
#endif
-#ifdef XILINX_OF_PLATFORM_DRIVER
- retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
- if (retval < 0)
- goto clean4;
-#endif
- return retval;
+ return 0;
-#ifdef XILINX_OF_PLATFORM_DRIVER
- /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
-clean4:
-#endif
-#ifdef OF_PLATFORM_DRIVER
- platform_driver_unregister(&OF_PLATFORM_DRIVER);
-clean3:
-#endif
-#ifdef PS3_SYSTEM_BUS_DRIVER
- ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
-clean2:
+#ifdef CONFIG_PPC_PS3
+clean1:
#endif
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
+ platform_unregister_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
clean0:
-#endif
#ifdef CONFIG_DYNAMIC_DEBUG
debugfs_remove(ehci_debug_root);
ehci_debug_root = NULL;
static void __exit ehci_hcd_cleanup(void)
{
-#ifdef XILINX_OF_PLATFORM_DRIVER
- platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
-#endif
-#ifdef OF_PLATFORM_DRIVER
- platform_driver_unregister(&OF_PLATFORM_DRIVER);
-#endif
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
-#endif
-#ifdef PS3_SYSTEM_BUS_DRIVER
- ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
+#ifdef CONFIG_PPC_PS3
+ ps3_ehci_driver_unregister(&ps3_ehci_driver);
#endif
+ platform_unregister_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
#ifdef CONFIG_DYNAMIC_DEBUG
debugfs_remove(ehci_debug_root);
#endif
if (ret)
xhci_free_command(xhci, command);
}
+ set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
"Finished xhci_run for USB2 roothub");
}
if (len > 0) {
/* Write the rest 1 - 3 bytes to FIFO */
+ val = 0;
memcpy(&val, buf, len);
musb_writel(fifo, 0, val);
}
{ USB_DEVICE(0x1FB9, 0x0602) }, /* Lake Shore Model 648 Magnet Power Supply */
{ USB_DEVICE(0x1FB9, 0x0700) }, /* Lake Shore Model 737 VSM Controller */
{ USB_DEVICE(0x1FB9, 0x0701) }, /* Lake Shore Model 776 Hall Matrix */
+ { USB_DEVICE(0x2184, 0x0030) }, /* GW Instek GDM-834x Digital Multimeter */
{ USB_DEVICE(0x2626, 0xEA60) }, /* Aruba Networks 7xxx USB Serial Console */
{ USB_DEVICE(0x3195, 0xF190) }, /* Link Instruments MSO-19 */
{ USB_DEVICE(0x3195, 0xF280) }, /* Link Instruments MSO-28 */
speed_t max_speed;
bool use_actual_rate;
bool no_flow_control;
+ bool no_event_mode;
};
enum cp210x_event_state {
static void cp210x_enable_event_mode(struct usb_serial_port *port)
{
+ struct cp210x_serial_private *priv = usb_get_serial_data(port->serial);
struct cp210x_port_private *port_priv = usb_get_serial_port_data(port);
int ret;
if (port_priv->event_mode)
return;
+ if (priv->no_event_mode)
+ return;
+
port_priv->event_state = ES_DATA;
port_priv->event_mode = true;
priv->use_actual_rate = use_actual_rate;
}
+static void cp2102_determine_quirks(struct usb_serial *serial)
+{
+ struct cp210x_serial_private *priv = usb_get_serial_data(serial);
+ u8 *buf;
+ int ret;
+
+ buf = kmalloc(2, GFP_KERNEL);
+ if (!buf)
+ return;
+ /*
+ * Some (possibly counterfeit) CP2102 do not support event-insertion
+ * mode and respond differently to malformed vendor requests.
+ * Specifically, they return one instead of two bytes when sent a
+ * two-byte part-number request.
+ */
+ ret = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+ CP210X_VENDOR_SPECIFIC, REQTYPE_DEVICE_TO_HOST,
+ CP210X_GET_PARTNUM, 0, buf, 2, USB_CTRL_GET_TIMEOUT);
+ if (ret == 1) {
+ dev_dbg(&serial->interface->dev,
+ "device does not support event-insertion mode\n");
+ priv->no_event_mode = true;
+ }
+
+ kfree(buf);
+}
+
static int cp210x_get_fw_version(struct usb_serial *serial, u16 value)
{
struct cp210x_serial_private *priv = usb_get_serial_data(serial);
return;
}
+ dev_dbg(&serial->interface->dev, "partnum = 0x%02x\n", priv->partnum);
+
switch (priv->partnum) {
+ case CP210X_PARTNUM_CP2102:
+ cp2102_determine_quirks(serial);
+ break;
case CP210X_PARTNUM_CP2105:
case CP210X_PARTNUM_CP2108:
cp210x_get_fw_version(serial, CP210X_GET_FW_VER);
#define BANDB_DEVICE_ID_USOPTL4_2P 0xBC02
#define BANDB_DEVICE_ID_USOPTL4_4 0xAC44
#define BANDB_DEVICE_ID_USOPTL4_4P 0xBC03
-#define BANDB_DEVICE_ID_USOPTL2_4 0xAC24
/* Interrupt Routine Defines */
{ USB_DEVICE(USB_VENDOR_ID_BANDB, BANDB_DEVICE_ID_USOPTL4_2P) },
{ USB_DEVICE(USB_VENDOR_ID_BANDB, BANDB_DEVICE_ID_USOPTL4_4) },
{ USB_DEVICE(USB_VENDOR_ID_BANDB, BANDB_DEVICE_ID_USOPTL4_4P) },
- { USB_DEVICE(USB_VENDOR_ID_BANDB, BANDB_DEVICE_ID_USOPTL2_4) },
{} /* terminating entry */
};
MODULE_DEVICE_TABLE(usb, id_table);
.driver_info = NCTRL(0) | RSVD(1) },
{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1056, 0xff), /* Telit FD980 */
.driver_info = NCTRL(2) | RSVD(3) },
+ { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1060, 0xff), /* Telit LN920 (rmnet) */
+ .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
+ { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1061, 0xff), /* Telit LN920 (MBIM) */
+ .driver_info = NCTRL(0) | RSVD(1) },
+ { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1062, 0xff), /* Telit LN920 (RNDIS) */
+ .driver_info = NCTRL(2) | RSVD(3) },
+ { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1063, 0xff), /* Telit LN920 (ECM) */
+ .driver_info = NCTRL(0) | RSVD(1) },
{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910),
.driver_info = NCTRL(0) | RSVD(1) | RSVD(3) },
{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910_DUAL_MODEM),
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0060, 0xff, 0xff, 0xff) },
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0070, 0xff, 0xff, 0xff) },
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0073, 0xff, 0xff, 0xff) },
- { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0094, 0xff, 0xff, 0xff) },
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0130, 0xff, 0xff, 0xff),
.driver_info = RSVD(1) },
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0133, 0xff, 0xff, 0xff),
.driver_info = RSVD(0) | RSVD(1) | RSVD(6) },
{ USB_DEVICE(0x0489, 0xe0b5), /* Foxconn T77W968 ESIM */
.driver_info = RSVD(0) | RSVD(1) | RSVD(6) },
+ { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0db, 0xff), /* Foxconn T99W265 MBIM */
+ .driver_info = RSVD(3) },
{ USB_DEVICE(0x1508, 0x1001), /* Fibocom NL668 (IOT version) */
.driver_info = RSVD(4) | RSVD(5) | RSVD(6) },
{ USB_DEVICE(0x2cb7, 0x0104), /* Fibocom NL678 series */
USB_SC_UFI, USB_PR_DEVICE, NULL, US_FL_FIX_INQUIRY | US_FL_SINGLE_LUN),
/*
- * Reported by Ondrej Zary <linux@rainbow-software.org>
+ * Reported by Ondrej Zary <linux@zary.sk>
* The device reports one sector more and breaks when that sector is accessed
+ * Firmwares older than 2.6c (the latest one and the only that claims Linux
+ * support) have also broken tag handling
*/
+UNUSUAL_DEV( 0x04ce, 0x0002, 0x0000, 0x026b,
+ "ScanLogic",
+ "SL11R-IDE",
+ USB_SC_DEVICE, USB_PR_DEVICE, NULL,
+ US_FL_FIX_CAPACITY | US_FL_BULK_IGNORE_TAG),
UNUSUAL_DEV( 0x04ce, 0x0002, 0x026c, 0x026c,
"ScanLogic",
"SL11R-IDE",
"LaCie",
"Rugged USB3-FW",
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
- US_FL_IGNORE_UAS),
+ US_FL_NO_REPORT_OPCODES | US_FL_NO_SAME),
/*
* Apricorn USB3 dongle sometimes returns "USBSUSBSUSBS" in response to SCSI
.num = nvq->batched_xdp,
.ptr = nvq->xdp,
};
- int err;
+ int i, err;
if (nvq->batched_xdp == 0)
goto signal_used;
err = sock->ops->sendmsg(sock, msghdr, 0);
if (unlikely(err < 0)) {
vq_err(&nvq->vq, "Fail to batch sending packets\n");
+
+ /* free pages owned by XDP; since this is an unlikely error path,
+ * keep it simple and avoid more complex bulk update for the
+ * used pages
+ */
+ for (i = 0; i < nvq->batched_xdp; ++i)
+ put_page(virt_to_head_page(nvq->xdp[i].data));
+ nvq->batched_xdp = 0;
+ nvq->done_idx = 0;
return;
}
config FB_TGA
tristate "TGA/SFB+ framebuffer support"
- depends on FB && (ALPHA || TC)
+ depends on FB
+ depends on PCI || TC
+ depends on ALPHA || TC
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
* Based on sunxi_wdt.c
*/
-#include <dt-bindings/reset-controller/mt2712-resets.h>
-#include <dt-bindings/reset-controller/mt8183-resets.h>
-#include <dt-bindings/reset-controller/mt8192-resets.h>
+#include <dt-bindings/reset/mt2712-resets.h>
+#include <dt-bindings/reset/mt8183-resets.h>
+#include <dt-bindings/reset/mt8192-resets.h>
#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/delay.h>
#include <linux/err.h>
config SWIOTLB_XEN
def_bool y
+ depends on XEN_PV || ARM || ARM64
select DMA_OPS
select SWIOTLB
implements them.
config XEN_PVCALLS_BACKEND
- bool "XEN PV Calls backend driver"
+ tristate "XEN PV Calls backend driver"
depends on INET && XEN && XEN_BACKEND
help
Experimental backend for the Xen PV Calls protocol
#include <linux/sched.h>
#include <linux/cred.h>
#include <linux/errno.h>
+#include <linux/freezer.h>
+#include <linux/kthread.h>
#include <linux/mm.h>
#include <linux/memblock.h>
#include <linux/pagemap.h>
#define EXTENT_ORDER (fls(XEN_PFN_PER_PAGE) - 1)
/*
- * balloon_process() state:
+ * balloon_thread() state:
*
* BP_DONE: done or nothing to do,
* BP_WAIT: wait to be rescheduled,
BP_ECANCELED
};
+/* Main waiting point for xen-balloon thread. */
+static DECLARE_WAIT_QUEUE_HEAD(balloon_thread_wq);
static DEFINE_MUTEX(balloon_mutex);
static LIST_HEAD(ballooned_pages);
static DECLARE_WAIT_QUEUE_HEAD(balloon_wq);
-/* Main work function, always executed in process context. */
-static void balloon_process(struct work_struct *work);
-static DECLARE_DELAYED_WORK(balloon_worker, balloon_process);
-
/* When ballooning out (allocating memory to return to Xen) we don't really
want the kernel to try too hard since that can trigger the oom killer. */
#define GFP_BALLOON \
static int xen_memory_notifier(struct notifier_block *nb, unsigned long val, void *v)
{
if (val == MEM_ONLINE)
- schedule_delayed_work(&balloon_worker, 0);
+ wake_up(&balloon_thread_wq);
return NOTIFY_OK;
}
}
/*
- * As this is a work item it is guaranteed to run as a single instance only.
+ * Stop waiting if either state is not BP_EAGAIN and ballooning action is
+ * needed, or if the credit has changed while state is BP_EAGAIN.
+ */
+static bool balloon_thread_cond(enum bp_state state, long credit)
+{
+ if (state != BP_EAGAIN)
+ credit = 0;
+
+ return current_credit() != credit || kthread_should_stop();
+}
+
+/*
+ * As this is a kthread it is guaranteed to run as a single instance only.
* We may of course race updates of the target counts (which are protected
* by the balloon lock), or with changes to the Xen hard limit, but we will
* recover from these in time.
*/
-static void balloon_process(struct work_struct *work)
+static int balloon_thread(void *unused)
{
enum bp_state state = BP_DONE;
long credit;
+ unsigned long timeout;
+
+ set_freezable();
+ for (;;) {
+ if (state == BP_EAGAIN)
+ timeout = balloon_stats.schedule_delay * HZ;
+ else
+ timeout = 3600 * HZ;
+ credit = current_credit();
+ wait_event_freezable_timeout(balloon_thread_wq,
+ balloon_thread_cond(state, credit), timeout);
+
+ if (kthread_should_stop())
+ return 0;
- do {
mutex_lock(&balloon_mutex);
credit = current_credit();
mutex_unlock(&balloon_mutex);
cond_resched();
-
- } while (credit && state == BP_DONE);
-
- /* Schedule more work if there is some still to be done. */
- if (state == BP_EAGAIN)
- schedule_delayed_work(&balloon_worker, balloon_stats.schedule_delay * HZ);
+ }
}
/* Resets the Xen limit, sets new target, and kicks off processing. */
{
/* No need for lock. Not read-modify-write updates. */
balloon_stats.target_pages = target;
- schedule_delayed_work(&balloon_worker, 0);
+ wake_up(&balloon_thread_wq);
}
EXPORT_SYMBOL_GPL(balloon_set_new_target);
/* The balloon may be too large now. Shrink it if needed. */
if (current_credit())
- schedule_delayed_work(&balloon_worker, 0);
+ wake_up(&balloon_thread_wq);
mutex_unlock(&balloon_mutex);
}
static int __init balloon_init(void)
{
+ struct task_struct *task;
+
if (!xen_domain())
return -ENODEV;
}
#endif
+ task = kthread_run(balloon_thread, NULL, "xen-balloon");
+ if (IS_ERR(task)) {
+ pr_err("xen-balloon thread could not be started, ballooning will not work!\n");
+ return PTR_ERR(task);
+ }
+
/* Init the xen-balloon driver. */
xen_balloon_init();
map->unmap_ops[offset+i].handle,
map->unmap_ops[offset+i].status);
map->unmap_ops[offset+i].handle = INVALID_GRANT_HANDLE;
+ if (use_ptemod) {
+ if (map->kunmap_ops[offset+i].status)
+ err = -EINVAL;
+ pr_debug("kunmap handle=%u st=%d\n",
+ map->kunmap_ops[offset+i].handle,
+ map->kunmap_ops[offset+i].status);
+ map->kunmap_ops[offset+i].handle = INVALID_GRANT_HANDLE;
+ }
}
return err;
}
static int xen_swiotlb_fixup(void *buf, unsigned long nslabs)
{
- int i, rc;
- int dma_bits;
+ int rc;
+ unsigned int order = get_order(IO_TLB_SEGSIZE << IO_TLB_SHIFT);
+ unsigned int i, dma_bits = order + PAGE_SHIFT;
dma_addr_t dma_handle;
phys_addr_t p = virt_to_phys(buf);
- dma_bits = get_order(IO_TLB_SEGSIZE << IO_TLB_SHIFT) + PAGE_SHIFT;
+ BUILD_BUG_ON(IO_TLB_SEGSIZE & (IO_TLB_SEGSIZE - 1));
+ BUG_ON(nslabs % IO_TLB_SEGSIZE);
i = 0;
do {
- int slabs = min(nslabs - i, (unsigned long)IO_TLB_SEGSIZE);
-
do {
rc = xen_create_contiguous_region(
- p + (i << IO_TLB_SHIFT),
- get_order(slabs << IO_TLB_SHIFT),
+ p + (i << IO_TLB_SHIFT), order,
dma_bits, &dma_handle);
} while (rc && dma_bits++ < MAX_DMA_BITS);
if (rc)
return rc;
- i += slabs;
+ i += IO_TLB_SEGSIZE;
} while (i < nslabs);
return 0;
}
return "";
}
-#define DEFAULT_NSLABS ALIGN(SZ_64M >> IO_TLB_SHIFT, IO_TLB_SEGSIZE)
-
-int __ref xen_swiotlb_init(void)
+int xen_swiotlb_init(void)
{
enum xen_swiotlb_err m_ret = XEN_SWIOTLB_UNKNOWN;
unsigned long bytes = swiotlb_size_or_default();
order--;
}
if (!start)
- goto error;
+ goto exit;
if (order != get_order(bytes)) {
pr_warn("Warning: only able to allocate %ld MB for software IO TLB\n",
(PAGE_SIZE << order) >> 20);
swiotlb_set_max_segment(PAGE_SIZE);
return 0;
error:
- if (repeat--) {
+ if (nslabs > 1024 && repeat--) {
/* Min is 2MB */
- nslabs = max(1024UL, (nslabs >> 1));
- pr_info("Lowering to %luMB\n",
- (nslabs << IO_TLB_SHIFT) >> 20);
+ nslabs = max(1024UL, ALIGN(nslabs >> 1, IO_TLB_SEGSIZE));
+ bytes = nslabs << IO_TLB_SHIFT;
+ pr_info("Lowering to %luMB\n", bytes >> 20);
goto retry;
}
+exit:
pr_err("%s (rc:%d)\n", xen_swiotlb_error(m_ret), rc);
- free_pages((unsigned long)start, order);
return rc;
}
/*
* Get IO TLB memory from any location.
*/
- start = memblock_alloc(PAGE_ALIGN(bytes), PAGE_SIZE);
+ start = memblock_alloc(PAGE_ALIGN(bytes),
+ IO_TLB_SEGSIZE << IO_TLB_SHIFT);
if (!start)
- panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
- __func__, PAGE_ALIGN(bytes), PAGE_SIZE);
+ panic("%s: Failed to allocate %lu bytes\n",
+ __func__, PAGE_ALIGN(bytes));
/*
* And replace that memory with pages under 4GB.
rc = xen_swiotlb_fixup(start, nslabs);
if (rc) {
memblock_free(__pa(start), PAGE_ALIGN(bytes));
- if (repeat--) {
+ if (nslabs > 1024 && repeat--) {
/* Min is 2MB */
- nslabs = max(1024UL, (nslabs >> 1));
+ nslabs = max(1024UL, ALIGN(nslabs >> 1, IO_TLB_SEGSIZE));
bytes = nslabs << IO_TLB_SHIFT;
pr_info("Lowering to %luMB\n", bytes >> 20);
goto retry;
panic("%s (rc:%d)", xen_swiotlb_error(XEN_SWIOTLB_EFIXUP), rc);
}
- if (swiotlb_init_with_tbl(start, nslabs, false))
+ if (swiotlb_init_with_tbl(start, nslabs, true))
panic("Cannot allocate SWIOTLB buffer");
swiotlb_set_max_segment(PAGE_SIZE);
}
#include "internal.h"
/*
+ * Handle invalidation of an mmap'd file. We invalidate all the PTEs referring
+ * to the pages in this file's pagecache, forcing the kernel to go through
+ * ->fault() or ->page_mkwrite() - at which point we can handle invalidation
+ * more fully.
+ */
+void afs_invalidate_mmap_work(struct work_struct *work)
+{
+ struct afs_vnode *vnode = container_of(work, struct afs_vnode, cb_work);
+
+ unmap_mapping_pages(vnode->vfs_inode.i_mapping, 0, 0, false);
+}
+
+void afs_server_init_callback_work(struct work_struct *work)
+{
+ struct afs_server *server = container_of(work, struct afs_server, initcb_work);
+ struct afs_vnode *vnode;
+ struct afs_cell *cell = server->cell;
+
+ down_read(&cell->fs_open_mmaps_lock);
+
+ list_for_each_entry(vnode, &cell->fs_open_mmaps, cb_mmap_link) {
+ if (vnode->cb_server == server) {
+ clear_bit(AFS_VNODE_CB_PROMISED, &vnode->flags);
+ queue_work(system_unbound_wq, &vnode->cb_work);
+ }
+ }
+
+ up_read(&cell->fs_open_mmaps_lock);
+}
+
+/*
* Allow the fileserver to request callback state (re-)initialisation.
* Unfortunately, UUIDs are not guaranteed unique.
*/
rcu_read_lock();
do {
server->cb_s_break++;
- server = rcu_dereference(server->uuid_next);
- } while (0);
+ atomic_inc(&server->cell->fs_s_break);
+ if (!list_empty(&server->cell->fs_open_mmaps))
+ queue_work(system_unbound_wq, &server->initcb_work);
+
+ } while ((server = rcu_dereference(server->uuid_next)));
rcu_read_unlock();
}
clear_bit(AFS_VNODE_NEW_CONTENT, &vnode->flags);
if (test_and_clear_bit(AFS_VNODE_CB_PROMISED, &vnode->flags)) {
vnode->cb_break++;
+ vnode->cb_v_break = vnode->volume->cb_v_break;
afs_clear_permits(vnode);
if (vnode->lock_state == AFS_VNODE_LOCK_WAITING_FOR_CB)
afs_lock_may_be_available(vnode);
+ if (reason != afs_cb_break_for_deleted &&
+ vnode->status.type == AFS_FTYPE_FILE &&
+ atomic_read(&vnode->cb_nr_mmap))
+ queue_work(system_unbound_wq, &vnode->cb_work);
+
trace_afs_cb_break(&vnode->fid, vnode->cb_break, reason, true);
} else {
trace_afs_cb_break(&vnode->fid, vnode->cb_break, reason, false);
seqlock_init(&cell->volume_lock);
cell->fs_servers = RB_ROOT;
seqlock_init(&cell->fs_lock);
+ INIT_LIST_HEAD(&cell->fs_open_mmaps);
+ init_rwsem(&cell->fs_open_mmaps_lock);
rwlock_init(&cell->vl_servers_lock);
cell->flags = (1 << AFS_CELL_FL_CHECK_ALIAS);
*/
static int afs_d_revalidate_rcu(struct dentry *dentry)
{
- struct afs_vnode *dvnode, *vnode;
+ struct afs_vnode *dvnode;
struct dentry *parent;
- struct inode *dir, *inode;
+ struct inode *dir;
long dir_version, de_version;
_enter("%p", dentry);
return -ECHILD;
}
- /* Check to see if the vnode referred to by the dentry still
- * has a callback.
- */
- if (d_really_is_positive(dentry)) {
- inode = d_inode_rcu(dentry);
- if (inode) {
- vnode = AFS_FS_I(inode);
- if (!afs_check_validity(vnode))
- return -ECHILD;
- }
- }
-
return 1; /* Still valid */
}
if (IS_ERR(key))
key = NULL;
- if (d_really_is_positive(dentry)) {
- inode = d_inode(dentry);
- if (inode) {
- vnode = AFS_FS_I(inode);
- afs_validate(vnode, key);
- if (test_bit(AFS_VNODE_DELETED, &vnode->flags))
- goto out_bad;
- }
- }
-
- /* lock down the parent dentry so we can peer at it */
+ /* Hold the parent dentry so we can peer at it */
parent = dget_parent(dentry);
dir = AFS_FS_I(d_inode(parent));
if (test_bit(AFS_VNODE_DELETED, &dir->flags)) {
_debug("%pd: parent dir deleted", dentry);
- goto out_bad_parent;
+ goto not_found;
}
/* We only need to invalidate a dentry if the server's copy changed
case 0:
/* the filename maps to something */
if (d_really_is_negative(dentry))
- goto out_bad_parent;
+ goto not_found;
inode = d_inode(dentry);
if (is_bad_inode(inode)) {
printk("kAFS: afs_d_revalidate: %pd2 has bad inode\n",
dentry);
- goto out_bad_parent;
+ goto not_found;
}
vnode = AFS_FS_I(inode);
dentry, fid.unique,
vnode->fid.unique,
vnode->vfs_inode.i_generation);
- write_seqlock(&vnode->cb_lock);
- set_bit(AFS_VNODE_DELETED, &vnode->flags);
- write_sequnlock(&vnode->cb_lock);
goto not_found;
}
goto out_valid;
default:
_debug("failed to iterate dir %pd: %d",
parent, ret);
- goto out_bad_parent;
+ goto not_found;
}
out_valid:
_leave(" = 1 [valid]");
return 1;
- /* the dirent, if it exists, now points to a different vnode */
not_found:
- spin_lock(&dentry->d_lock);
- dentry->d_flags |= DCACHE_NFSFS_RENAMED;
- spin_unlock(&dentry->d_lock);
-
-out_bad_parent:
_debug("dropping dentry %pd2", dentry);
dput(parent);
-out_bad:
key_put(key);
_leave(" = 0 [bad]");
goto error;
}
+ ret = afs_validate(vnode, op->key);
+ if (ret < 0)
+ goto error_op;
+
afs_op_set_vnode(op, 0, dvnode);
afs_op_set_vnode(op, 1, vnode);
op->file[0].dv_delta = 1;
op->create.reason = afs_edit_dir_for_link;
return afs_do_sync_operation(op);
+error_op:
+ afs_put_operation(op);
error:
d_drop(dentry);
_leave(" = %d", ret);
if (IS_ERR(op))
return PTR_ERR(op);
+ ret = afs_validate(vnode, op->key);
+ op->error = ret;
+ if (ret < 0)
+ goto error;
+
afs_op_set_vnode(op, 0, orig_dvnode);
afs_op_set_vnode(op, 1, new_dvnode); /* May be same as orig_dvnode */
op->file[0].dv_delta = 1;
if (b == nr_blocks) {
_debug("init %u", b);
afs_edit_init_block(meta, block, b);
- i_size_write(&vnode->vfs_inode, (b + 1) * AFS_DIR_BLOCK_SIZE);
+ afs_set_i_size(vnode, (b + 1) * AFS_DIR_BLOCK_SIZE);
}
/* Only lower dir pages have a counter in the header. */
new_directory:
afs_edit_init_block(meta, meta, 0);
i_size = AFS_DIR_BLOCK_SIZE;
- i_size_write(&vnode->vfs_inode, i_size);
+ afs_set_i_size(vnode, i_size);
slot = AFS_DIR_RESV_BLOCKS0;
page = page0;
block = meta;
static int afs_releasepage(struct page *page, gfp_t gfp_flags);
static void afs_readahead(struct readahead_control *ractl);
+static ssize_t afs_file_read_iter(struct kiocb *iocb, struct iov_iter *iter);
+static void afs_vm_open(struct vm_area_struct *area);
+static void afs_vm_close(struct vm_area_struct *area);
+static vm_fault_t afs_vm_map_pages(struct vm_fault *vmf, pgoff_t start_pgoff, pgoff_t end_pgoff);
const struct file_operations afs_file_operations = {
.open = afs_open,
.release = afs_release,
.llseek = generic_file_llseek,
- .read_iter = generic_file_read_iter,
+ .read_iter = afs_file_read_iter,
.write_iter = afs_file_write,
.mmap = afs_file_mmap,
.splice_read = generic_file_splice_read,
};
static const struct vm_operations_struct afs_vm_ops = {
+ .open = afs_vm_open,
+ .close = afs_vm_close,
.fault = filemap_fault,
- .map_pages = filemap_map_pages,
+ .map_pages = afs_vm_map_pages,
.page_mkwrite = afs_page_mkwrite,
};
fsreq->subreq = subreq;
fsreq->pos = subreq->start + subreq->transferred;
fsreq->len = subreq->len - subreq->transferred;
- fsreq->key = subreq->rreq->netfs_priv;
+ fsreq->key = key_get(subreq->rreq->netfs_priv);
fsreq->vnode = vnode;
fsreq->iter = &fsreq->def_iter;
fsreq->pos, fsreq->len);
afs_fetch_data(fsreq->vnode, fsreq);
+ afs_put_read(fsreq);
}
static int afs_symlink_readpage(struct page *page)
return 1;
}
+static void afs_add_open_mmap(struct afs_vnode *vnode)
+{
+ if (atomic_inc_return(&vnode->cb_nr_mmap) == 1) {
+ down_write(&vnode->volume->cell->fs_open_mmaps_lock);
+
+ list_add_tail(&vnode->cb_mmap_link,
+ &vnode->volume->cell->fs_open_mmaps);
+
+ up_write(&vnode->volume->cell->fs_open_mmaps_lock);
+ }
+}
+
+static void afs_drop_open_mmap(struct afs_vnode *vnode)
+{
+ if (!atomic_dec_and_test(&vnode->cb_nr_mmap))
+ return;
+
+ down_write(&vnode->volume->cell->fs_open_mmaps_lock);
+
+ if (atomic_read(&vnode->cb_nr_mmap) == 0)
+ list_del_init(&vnode->cb_mmap_link);
+
+ up_write(&vnode->volume->cell->fs_open_mmaps_lock);
+ flush_work(&vnode->cb_work);
+}
+
/*
* Handle setting up a memory mapping on an AFS file.
*/
static int afs_file_mmap(struct file *file, struct vm_area_struct *vma)
{
+ struct afs_vnode *vnode = AFS_FS_I(file_inode(file));
int ret;
+ afs_add_open_mmap(vnode);
+
ret = generic_file_mmap(file, vma);
if (ret == 0)
vma->vm_ops = &afs_vm_ops;
+ else
+ afs_drop_open_mmap(vnode);
return ret;
}
+
+static void afs_vm_open(struct vm_area_struct *vma)
+{
+ afs_add_open_mmap(AFS_FS_I(file_inode(vma->vm_file)));
+}
+
+static void afs_vm_close(struct vm_area_struct *vma)
+{
+ afs_drop_open_mmap(AFS_FS_I(file_inode(vma->vm_file)));
+}
+
+static vm_fault_t afs_vm_map_pages(struct vm_fault *vmf, pgoff_t start_pgoff, pgoff_t end_pgoff)
+{
+ struct afs_vnode *vnode = AFS_FS_I(file_inode(vmf->vma->vm_file));
+ struct afs_file *af = vmf->vma->vm_file->private_data;
+
+ switch (afs_validate(vnode, af->key)) {
+ case 0:
+ return filemap_map_pages(vmf, start_pgoff, end_pgoff);
+ case -ENOMEM:
+ return VM_FAULT_OOM;
+ case -EINTR:
+ case -ERESTARTSYS:
+ return VM_FAULT_RETRY;
+ case -ESTALE:
+ default:
+ return VM_FAULT_SIGBUS;
+ }
+}
+
+static ssize_t afs_file_read_iter(struct kiocb *iocb, struct iov_iter *iter)
+{
+ struct afs_vnode *vnode = AFS_FS_I(file_inode(iocb->ki_filp));
+ struct afs_file *af = iocb->ki_filp->private_data;
+ int ret;
+
+ ret = afs_validate(vnode, af->key);
+ if (ret < 0)
+ return ret;
+
+ return generic_file_read_iter(iocb, iter);
+}
#include <linux/slab.h>
#include "afs_fs.h"
#include "internal.h"
+#include "protocol_afs.h"
#include "protocol_yfs.h"
static unsigned int afs_fs_probe_fast_poll_interval = 30 * HZ;
struct afs_addr_list *alist = call->alist;
struct afs_server *server = call->server;
unsigned int index = call->addr_ix;
- unsigned int rtt_us = 0;
+ unsigned int rtt_us = 0, cap0;
int ret = call->error;
_enter("%pU,%u", &server->uuid, index);
clear_bit(AFS_SERVER_FL_IS_YFS, &server->flags);
alist->addrs[index].srx_service = call->service_id;
}
+ cap0 = ntohl(call->tmp);
+ if (cap0 & AFS3_VICED_CAPABILITY_64BITFILES)
+ set_bit(AFS_SERVER_FL_HAS_FS64, &server->flags);
+ else
+ clear_bit(AFS_SERVER_FL_HAS_FS64, &server->flags);
}
if (rxrpc_kernel_get_srtt(call->net->socket, call->rxcall, &rtt_us) &&
struct afs_read *req = op->fetch.req;
__be32 *bp;
- if (upper_32_bits(req->pos) ||
- upper_32_bits(req->len) ||
- upper_32_bits(req->pos + req->len))
+ if (test_bit(AFS_SERVER_FL_HAS_FS64, &op->server->flags))
return afs_fs_fetch_data64(op);
_enter("");
(unsigned long long)op->store.pos,
(unsigned long long)op->store.i_size);
- if (upper_32_bits(op->store.pos) ||
- upper_32_bits(op->store.size) ||
- upper_32_bits(op->store.i_size))
+ if (test_bit(AFS_SERVER_FL_HAS_FS64, &op->server->flags))
return afs_fs_store_data64(op);
call = afs_alloc_flat_call(op->net, &afs_RXFSStoreData,
key_serial(op->key), vp->fid.vid, vp->fid.vnode);
ASSERT(attr->ia_valid & ATTR_SIZE);
- if (upper_32_bits(attr->ia_size))
+ if (test_bit(AFS_SERVER_FL_HAS_FS64, &op->server->flags))
return afs_fs_setattr_size64(op);
call = afs_alloc_flat_call(op->net, &afs_RXFSStoreData_as_Status,
return ret;
count = ntohl(call->tmp);
-
call->count = count;
call->count2 = count;
- afs_extract_discard(call, count * sizeof(__be32));
+ if (count == 0) {
+ call->unmarshall = 4;
+ call->tmp = 0;
+ break;
+ }
+
+ /* Extract the first word of the capabilities to call->tmp */
+ afs_extract_to_tmp(call);
call->unmarshall++;
fallthrough;
- /* Extract capabilities words */
case 2:
ret = afs_extract_data(call, false);
if (ret < 0)
return ret;
- /* TODO: Examine capabilities */
+ afs_extract_discard(call, (count - 1) * sizeof(__be32));
+ call->unmarshall++;
+ fallthrough;
+
+ /* Extract remaining capabilities words */
+ case 3:
+ ret = afs_extract_data(call, false);
+ if (ret < 0)
+ return ret;
call->unmarshall++;
break;
}
/*
- * Set the file size and block count. Estimate the number of 512 bytes blocks
- * used, rounded up to nearest 1K for consistency with other AFS clients.
- */
-static void afs_set_i_size(struct afs_vnode *vnode, u64 size)
-{
- i_size_write(&vnode->vfs_inode, size);
- vnode->vfs_inode.i_blocks = ((size + 1023) >> 10) << 1;
-}
-
-/*
* Initialise an inode from the vnode status.
*/
static int afs_inode_init_from_status(struct afs_operation *op,
}
/*
- * Get the server reinit counter for a vnode's current server.
+ * Check to see if we have a server currently serving this volume and that it
+ * hasn't been reinitialised or dropped from the list.
*/
-static bool afs_get_s_break_rcu(struct afs_vnode *vnode, unsigned int *_s_break)
+static bool afs_check_server_good(struct afs_vnode *vnode)
{
- struct afs_server_list *slist = rcu_dereference(vnode->volume->servers);
+ struct afs_server_list *slist;
struct afs_server *server;
+ bool good;
int i;
+ if (vnode->cb_fs_s_break == atomic_read(&vnode->volume->cell->fs_s_break))
+ return true;
+
+ rcu_read_lock();
+
+ slist = rcu_dereference(vnode->volume->servers);
for (i = 0; i < slist->nr_servers; i++) {
server = slist->servers[i].server;
if (server == vnode->cb_server) {
- *_s_break = READ_ONCE(server->cb_s_break);
- return true;
+ good = (vnode->cb_s_break == server->cb_s_break);
+ rcu_read_unlock();
+ return good;
}
}
+ rcu_read_unlock();
return false;
}
*/
bool afs_check_validity(struct afs_vnode *vnode)
{
- struct afs_volume *volume = vnode->volume;
enum afs_cb_break_reason need_clear = afs_cb_break_no_break;
time64_t now = ktime_get_real_seconds();
- bool valid;
- unsigned int cb_break, cb_s_break, cb_v_break;
+ unsigned int cb_break;
int seq = 0;
do {
read_seqbegin_or_lock(&vnode->cb_lock, &seq);
- cb_v_break = READ_ONCE(volume->cb_v_break);
cb_break = vnode->cb_break;
- if (test_bit(AFS_VNODE_CB_PROMISED, &vnode->flags) &&
- afs_get_s_break_rcu(vnode, &cb_s_break)) {
- if (vnode->cb_s_break != cb_s_break ||
- vnode->cb_v_break != cb_v_break) {
- vnode->cb_s_break = cb_s_break;
- vnode->cb_v_break = cb_v_break;
- need_clear = afs_cb_break_for_vsbreak;
- valid = false;
- } else if (test_bit(AFS_VNODE_ZAP_DATA, &vnode->flags)) {
+ if (test_bit(AFS_VNODE_CB_PROMISED, &vnode->flags)) {
+ if (vnode->cb_v_break != vnode->volume->cb_v_break)
+ need_clear = afs_cb_break_for_v_break;
+ else if (!afs_check_server_good(vnode))
+ need_clear = afs_cb_break_for_s_reinit;
+ else if (test_bit(AFS_VNODE_ZAP_DATA, &vnode->flags))
need_clear = afs_cb_break_for_zap;
- valid = false;
- } else if (vnode->cb_expires_at - 10 <= now) {
+ else if (vnode->cb_expires_at - 10 <= now)
need_clear = afs_cb_break_for_lapsed;
- valid = false;
- } else {
- valid = true;
- }
} else if (test_bit(AFS_VNODE_DELETED, &vnode->flags)) {
- valid = true;
+ ;
} else {
- vnode->cb_v_break = cb_v_break;
- valid = false;
+ need_clear = afs_cb_break_no_promise;
}
} while (need_seqretry(&vnode->cb_lock, seq));
done_seqretry(&vnode->cb_lock, seq);
- if (need_clear != afs_cb_break_no_break) {
- write_seqlock(&vnode->cb_lock);
- if (cb_break == vnode->cb_break)
- __afs_break_callback(vnode, need_clear);
- else
- trace_afs_cb_miss(&vnode->fid, need_clear);
- write_sequnlock(&vnode->cb_lock);
- valid = false;
- }
+ if (need_clear == afs_cb_break_no_break)
+ return true;
- return valid;
+ write_seqlock(&vnode->cb_lock);
+ if (need_clear == afs_cb_break_no_promise)
+ vnode->cb_v_break = vnode->volume->cb_v_break;
+ else if (cb_break == vnode->cb_break)
+ __afs_break_callback(vnode, need_clear);
+ else
+ trace_afs_cb_miss(&vnode->fid, need_clear);
+ write_sequnlock(&vnode->cb_lock);
+ return false;
}
/*
*/
int afs_validate(struct afs_vnode *vnode, struct key *key)
{
- bool valid;
int ret;
_enter("{v={%llx:%llu} fl=%lx},%x",
vnode->fid.vid, vnode->fid.vnode, vnode->flags,
key_serial(key));
- rcu_read_lock();
- valid = afs_check_validity(vnode);
- rcu_read_unlock();
-
- if (test_bit(AFS_VNODE_DELETED, &vnode->flags))
- clear_nlink(&vnode->vfs_inode);
+ if (unlikely(test_bit(AFS_VNODE_DELETED, &vnode->flags))) {
+ if (vnode->vfs_inode.i_nlink)
+ clear_nlink(&vnode->vfs_inode);
+ goto valid;
+ }
- if (valid)
+ if (test_bit(AFS_VNODE_CB_PROMISED, &vnode->flags) &&
+ afs_check_validity(vnode))
goto valid;
down_write(&vnode->validate_lock);
/* Active fileserver interaction state. */
struct rb_root fs_servers; /* afs_server (by server UUID) */
seqlock_t fs_lock; /* For fs_servers */
+ struct rw_semaphore fs_open_mmaps_lock;
+ struct list_head fs_open_mmaps; /* List of vnodes that are mmapped */
+ atomic_t fs_s_break; /* Counter of CB.InitCallBackState messages */
/* VL server list. */
rwlock_t vl_servers_lock; /* Lock on vl_servers */
struct hlist_node addr4_link; /* Link in net->fs_addresses4 */
struct hlist_node addr6_link; /* Link in net->fs_addresses6 */
struct hlist_node proc_link; /* Link in net->fs_proc */
+ struct work_struct initcb_work; /* Work for CB.InitCallBackState* */
struct afs_server *gc_next; /* Next server in manager's list */
time64_t unuse_time; /* Time at which last unused */
unsigned long flags;
#define AFS_SERVER_FL_IS_YFS 16 /* Server is YFS not AFS */
#define AFS_SERVER_FL_NO_IBULK 17 /* Fileserver doesn't support FS.InlineBulkStatus */
#define AFS_SERVER_FL_NO_RM2 18 /* Fileserver doesn't support YFS.RemoveFile2 */
+#define AFS_SERVER_FL_HAS_FS64 19 /* Fileserver supports FS.{Fetch,Store}Data64 */
atomic_t ref; /* Object refcount */
atomic_t active; /* Active user count */
u32 addr_version; /* Address list version */
afs_lock_type_t lock_type : 8;
/* outstanding callback notification on this file */
+ struct work_struct cb_work; /* Work for mmap'd files */
+ struct list_head cb_mmap_link; /* Link in cell->fs_open_mmaps */
void *cb_server; /* Server with callback/filelock */
+ atomic_t cb_nr_mmap; /* Number of mmaps */
+ unsigned int cb_fs_s_break; /* Mass server break counter (cell->fs_s_break) */
unsigned int cb_s_break; /* Mass break counter on ->server */
unsigned int cb_v_break; /* Mass break counter on ->volume */
unsigned int cb_break; /* Break counter on vnode */
/*
* callback.c
*/
+extern void afs_invalidate_mmap_work(struct work_struct *);
+extern void afs_server_init_callback_work(struct work_struct *work);
extern void afs_init_callback_state(struct afs_server *);
extern void __afs_break_callback(struct afs_vnode *, enum afs_cb_break_reason);
extern void afs_break_callback(struct afs_vnode *, enum afs_cb_break_reason);
}
/*
+ * Set the file size and block count. Estimate the number of 512 bytes blocks
+ * used, rounded up to nearest 1K for consistency with other AFS clients.
+ */
+static inline void afs_set_i_size(struct afs_vnode *vnode, u64 size)
+{
+ i_size_write(&vnode->vfs_inode, size);
+ vnode->vfs_inode.i_blocks = ((size + 1023) >> 10) << 1;
+}
+
+/*
* Check for a conflicting operation on a directory that we just unlinked from.
* If someone managed to sneak a link or an unlink in on the file we just
* unlinked, we won't be able to trust nlink on an AFS file (but not YFS).
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* AFS protocol bits
+ *
+ * Copyright (C) 2021 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ */
+
+
+#define AFSCAPABILITIESMAX 196 /* Maximum number of words in a capability set */
+
+/* AFS3 Fileserver capabilities word 0 */
+#define AFS3_VICED_CAPABILITY_ERRORTRANS 0x0001 /* Uses UAE errors */
+#define AFS3_VICED_CAPABILITY_64BITFILES 0x0002 /* FetchData64 & StoreData64 supported */
+#define AFS3_VICED_CAPABILITY_WRITELOCKACL 0x0004 /* Can lock a file even without lock perm */
+#define AFS3_VICED_CAPABILITY_SANEACLS 0x0008 /* ACLs reviewed for sanity - don't use */
yfs_LockMandatoryWrite = 0x101,
yfs_LockMandatoryExtend = 0x102,
};
+
+/* RXYFS Viced Capability Flags */
+#define YFS_VICED_CAPABILITY_ERRORTRANS 0x0001 /* Deprecated v0.195 */
+#define YFS_VICED_CAPABILITY_64BITFILES 0x0002 /* Deprecated v0.195 */
+#define YFS_VICED_CAPABILITY_WRITELOCKACL 0x0004 /* Can lock a file even without lock perm */
+#define YFS_VICED_CAPABILITY_SANEACLS 0x0008 /* Deprecated v0.195 */
if (vnode->cb_server != server) {
vnode->cb_server = server;
vnode->cb_s_break = server->cb_s_break;
+ vnode->cb_fs_s_break = atomic_read(&server->cell->fs_s_break);
vnode->cb_v_break = vnode->volume->cb_v_break;
clear_bit(AFS_VNODE_CB_PROMISED, &vnode->flags);
}
server->addr_version = alist->version;
server->uuid = *uuid;
rwlock_init(&server->fs_lock);
+ INIT_WORK(&server->initcb_work, afs_server_init_callback_work);
init_waitqueue_head(&server->probe_wq);
INIT_LIST_HEAD(&server->probe_link);
spin_lock_init(&server->probe_lock);
if (test_bit(AFS_SERVER_FL_MAY_HAVE_CB, &server->flags))
afs_give_up_callbacks(net, server);
+ flush_work(&server->initcb_work);
afs_put_server(net, server, afs_server_trace_destroy);
}
vnode->lock_state = AFS_VNODE_LOCK_NONE;
init_rwsem(&vnode->rmdir_lock);
+ INIT_WORK(&vnode->cb_work, afs_invalidate_mmap_work);
_leave(" = %p", &vnode->vfs_inode);
return &vnode->vfs_inode;
write_seqlock(&vnode->cb_lock);
i_size = i_size_read(&vnode->vfs_inode);
if (maybe_i_size > i_size)
- i_size_write(&vnode->vfs_inode, maybe_i_size);
+ afs_set_i_size(vnode, maybe_i_size);
write_sequnlock(&vnode->cb_lock);
}
}
/* Has the page moved or been split? */
- if (unlikely(page != xas_reload(&xas)))
+ if (unlikely(page != xas_reload(&xas))) {
+ put_page(page);
break;
+ }
- if (!trylock_page(page))
+ if (!trylock_page(page)) {
+ put_page(page);
break;
+ }
if (!PageDirty(page) || PageWriteback(page)) {
unlock_page(page);
+ put_page(page);
break;
}
t = afs_page_dirty_to(page, priv);
if (f != 0 && !new_content) {
unlock_page(page);
+ put_page(page);
break;
}
ssize_t afs_file_write(struct kiocb *iocb, struct iov_iter *from)
{
struct afs_vnode *vnode = AFS_FS_I(file_inode(iocb->ki_filp));
+ struct afs_file *af = iocb->ki_filp->private_data;
ssize_t result;
size_t count = iov_iter_count(from);
if (!count)
return 0;
+ result = afs_validate(vnode, af->key);
+ if (result < 0)
+ return result;
+
result = generic_file_write_iter(iocb, from);
_leave(" = %zd", result);
*/
int afs_fsync(struct file *file, loff_t start, loff_t end, int datasync)
{
- struct inode *inode = file_inode(file);
- struct afs_vnode *vnode = AFS_FS_I(inode);
+ struct afs_vnode *vnode = AFS_FS_I(file_inode(file));
+ struct afs_file *af = file->private_data;
+ int ret;
_enter("{%llx:%llu},{n=%pD},%d",
vnode->fid.vid, vnode->fid.vnode, file,
datasync);
+ ret = afs_validate(vnode, af->key);
+ if (ret < 0)
+ return ret;
+
return file_write_and_wait_range(file, start, end);
}
struct file *file = vmf->vma->vm_file;
struct inode *inode = file_inode(file);
struct afs_vnode *vnode = AFS_FS_I(inode);
+ struct afs_file *af = file->private_data;
unsigned long priv;
vm_fault_t ret = VM_FAULT_RETRY;
_enter("{{%llx:%llu}},{%lx}", vnode->fid.vid, vnode->fid.vnode, page->index);
+ afs_validate(vnode, af->key);
+
sb_start_pagefault(inode->i_sb);
/* Wait for the page to be written to the cache before we allow it to
if (!ordered) {
ordered = btrfs_lookup_ordered_extent(inode, offset);
- BUG_ON(!ordered); /* Logic error */
+ /*
+ * The bio range is not covered by any ordered extent,
+ * must be a code logic error.
+ */
+ if (unlikely(!ordered)) {
+ WARN(1, KERN_WARNING
+ "no ordered extent for root %llu ino %llu offset %llu\n",
+ inode->root->root_key.objectid,
+ btrfs_ino(inode), offset);
+ kvfree(sums);
+ return BLK_STS_IOERR;
+ }
}
nr_sectors = BTRFS_BYTES_TO_BLKS(fs_info,
{
lockdep_assert_held(&info->lock);
- btrfs_info(fs_info, "space_info %llu has %llu free, is %sfull",
+ /* The free space could be negative in case of overcommit */
+ btrfs_info(fs_info, "space_info %llu has %lld free, is %sfull",
info->flags,
- info->total_bytes - btrfs_space_info_used(info, true),
+ (s64)(info->total_bytes - btrfs_space_info_used(info, true)),
info->full ? "" : "not ");
btrfs_info(fs_info,
"space_info total=%llu, used=%llu, pinned=%llu, reserved=%llu, may_use=%llu, readonly=%llu zone_unusable=%llu",
*/
static int rollback_verity(struct btrfs_inode *inode)
{
- struct btrfs_trans_handle *trans;
+ struct btrfs_trans_handle *trans = NULL;
struct btrfs_root *root = inode->root;
int ret;
trans = btrfs_start_transaction(root, 2);
if (IS_ERR(trans)) {
ret = PTR_ERR(trans);
+ trans = NULL;
btrfs_handle_fs_error(root->fs_info, ret,
"failed to start transaction in verity rollback %llu",
(u64)inode->vfs_inode.i_ino);
btrfs_abort_transaction(trans, ret);
goto out;
}
- btrfs_end_transaction(trans);
out:
+ if (trans)
+ btrfs_end_transaction(trans);
return ret;
}
atomic_set(&device->dev_stats_ccnt, 0);
extent_io_tree_release(&device->alloc_state);
+ /*
+ * Reset the flush error record. We might have a transient flush error
+ * in this mount, and if so we aborted the current transaction and set
+ * the fs to an error state, guaranteeing no super blocks can be further
+ * committed. However that error might be transient and if we unmount the
+ * filesystem and mount it again, we should allow the mount to succeed
+ * (btrfs_check_rw_degradable() should not fail) - if after mounting the
+ * filesystem again we still get flush errors, then we will again abort
+ * any transaction and set the error state, guaranteeing no commits of
+ * unsafe super blocks.
+ */
+ device->last_flush_error = 0;
+
/* Verify the device is back in a pristine state */
ASSERT(!test_bit(BTRFS_DEV_STATE_FLUSH_SENT, &device->dev_state));
ASSERT(!test_bit(BTRFS_DEV_STATE_REPLACE_TGT, &device->dev_state));
}
EXPORT_SYMBOL_GPL(invalidate_bh_lrus);
-void invalidate_bh_lrus_cpu(int cpu)
+/*
+ * It's called from workqueue context so we need a bh_lru_lock to close
+ * the race with preemption/irq.
+ */
+void invalidate_bh_lrus_cpu(void)
{
struct bh_lru *b;
bh_lru_lock();
- b = per_cpu_ptr(&bh_lrus, cpu);
+ b = this_cpu_ptr(&bh_lrus);
__invalidate_bh_lrus(b);
bh_lru_unlock();
}
list_for_each_entry(req, &ci->i_unsafe_dirops,
r_unsafe_dir_item) {
s = req->r_session;
- if (unlikely(s->s_mds > max)) {
+ if (unlikely(s->s_mds >= max)) {
spin_unlock(&ci->i_unsafe_lock);
goto retry;
}
list_for_each_entry(req, &ci->i_unsafe_iops,
r_unsafe_target_item) {
s = req->r_session;
- if (unlikely(s->s_mds > max)) {
+ if (unlikely(s->s_mds >= max)) {
spin_unlock(&ci->i_unsafe_lock);
goto retry;
}
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/cache.c - CIFS filesystem cache index structure definitions
+ * CIFS filesystem cache index structure definitions
*
* Copyright (c) 2010 Novell, Inc.
* Authors(s): Suresh Jayaraman (sjayaraman@suse.de>
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * fs/cifs_debug.c
*
* Copyright (C) International Business Machines Corp., 2000,2005
*
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifs_fs_sb.h
*
* Copyright (c) International Business Machines Corp., 2002,2004
* Author(s): Steve French (sfrench@us.ibm.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifs_ioctl.h
*
* Structure definitions for io control for cifs/smb3
*
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/cifs_spnego.c -- SPNEGO upcall management for CIFS
+ * SPNEGO upcall management for CIFS
*
* Copyright (c) 2007 Red Hat, Inc.
* Author(s): Jeff Layton (jlayton@redhat.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifs_spnego.h -- SPNEGO upcall management for CIFS
+ * SPNEGO upcall management for CIFS
*
* Copyright (c) 2007 Red Hat, Inc.
* Author(s): Jeff Layton (jlayton@redhat.com)
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * fs/cifs/cifs_unicode.c
*
* Copyright (c) International Business Machines Corp., 2000,2009
* Modified by Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/cifsacl.c
*
* Copyright (C) International Business Machines Corp., 2007,2008
* Author(s): Steve French (sfrench@us.ibm.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifsacl.h
*
* Copyright (c) International Business Machines Corp., 2007
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/cifsencrypt.c
*
* Encryption and hashing operations relating to NTLM, NTLMv2. See MS-NLMP
* for more detailed information
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/cifsfs.c
*
* Copyright (C) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifsfs.h
*
* Copyright (c) International Business Machines Corp., 2002, 2007
* Author(s): Steve French (sfrench@us.ibm.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifsglob.h
*
* Copyright (C) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
#define CIFS_INO_INVALID_MAPPING (4) /* pagecache is invalid */
#define CIFS_INO_LOCK (5) /* lock bit for synchronization */
#define CIFS_INO_MODIFIED_ATTR (6) /* Indicate change in mtime/ctime */
+#define CIFS_INO_CLOSE_ON_LOCK (7) /* Not to defer the close when lock is set */
unsigned long flags;
spinlock_t writers_lock;
unsigned int writers; /* Number of writers on this inode */
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifspdu.h
*
* Copyright (c) International Business Machines Corp., 2002,2009
* Author(s): Steve French (sfrench@us.ibm.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/cifsproto.h
*
* Copyright (c) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
extern void cifs_close_all_deferred_files(struct cifs_tcon *cifs_tcon);
+extern void cifs_close_deferred_file_under_dentry(struct cifs_tcon *cifs_tcon,
+ const char *path);
+
extern struct TCP_Server_Info *cifs_get_tcp_session(struct smb3_fs_context *ctx);
extern void cifs_put_tcp_session(struct TCP_Server_Info *server,
int from_reconnect);
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/cifssmb.c
*
* Copyright (C) International Business Machines Corp., 2002,2010
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/connect.c
*
* Copyright (C) International Business Machines Corp., 2002,2011
* Author(s): Steve French (sfrench@us.ibm.com)
module_put_and_exit(0);
}
-/**
+/*
* Returns true if srcaddr isn't specified and rhs isn't specified, or
* if srcaddr is specified and matches the IP address of the rhs argument
*/
/**
* cifs_setup_ipc - helper to setup the IPC tcon for the session
+ * @ses: smb session to issue the request on
+ * @ctx: the superblock configuration context to use for building the
+ * new tree connection for the IPC (interprocess communication RPC)
*
* A new IPC connection is made and stored in the session
* tcon_ipc. The IPC tcon has the same lifetime as the session.
/**
* cifs_free_ipc - helper to release the session IPC tcon
+ * @ses: smb session to unmount the IPC from
*
* Needs to be called everytime a session is destroyed.
*
/**
* cifs_get_smb_ses - get a session matching @ctx data from @server
+ * @server: server to setup the session to
+ * @ctx: superblock configuration context to use to setup the session
*
* This function assumes it is being called from cifs_mount() where we
* already got a server reference (server refcount +1). See
/**
* cifs_get_tcon - get a tcon matching @ctx data from @ses
+ * @ses: smb session to issue the request on
+ * @ctx: the superblock configuration context to use for building the
*
* - tcon refcount is the number of mount points using the tcon.
* - ses refcount is the number of tcon using the session.
spin_lock(&cifs_tcp_ses_lock);
cifs_sb = CIFS_SB(sb);
tlink = cifs_get_tlink(cifs_sb_master_tlink(cifs_sb));
- if (IS_ERR(tlink)) {
+ if (tlink == NULL) {
+ /* can not match superblock if tlink were ever null */
spin_unlock(&cifs_tcp_ses_lock);
- return rc;
+ return 0;
}
tcon = tlink_tcon(tlink);
ses = tcon->ses;
return full_path;
}
-/**
+/*
* expand_dfs_referral - Perform a dfs referral query and update the cifs_sb
*
* If a referral is found, cifs_sb->ctx->mount_options will be (re-)allocated
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/dir.c
*
* vfs operations that deal with dentries
*
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/dns_resolve.c
*
* Copyright (c) 2007 Igor Mammedov
* Author(s): Igor Mammedov (niallain@gmail.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/dns_resolve.h -- DNS Resolver upcall management for CIFS DFS
- * Handles host name to IP address resolution
+ * DNS Resolver upcall management for CIFS DFS
+ * Handles host name to IP address resolution
*
* Copyright (c) International Business Machines Corp., 2008
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/export.c
*
* Copyright (C) International Business Machines Corp., 2007
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/file.c
*
* vfs operations that deal with files
*
dclose = kmalloc(sizeof(struct cifs_deferred_close), GFP_KERNEL);
if ((cinode->oplock == CIFS_CACHE_RHW_FLG) &&
cinode->lease_granted &&
+ !test_bit(CIFS_INO_CLOSE_ON_LOCK, &cinode->flags) &&
dclose) {
- if (test_bit(CIFS_INO_MODIFIED_ATTR, &cinode->flags)) {
+ if (test_and_clear_bit(CIFS_INO_MODIFIED_ATTR, &cinode->flags)) {
inode->i_ctime = inode->i_mtime = current_time(inode);
cifs_fscache_update_inode_cookie(inode);
}
cifs_read_flock(flock, &type, &lock, &unlock, &wait_flag,
tcon->ses->server);
cifs_sb = CIFS_FILE_SB(file);
+ set_bit(CIFS_INO_CLOSE_ON_LOCK, &CIFS_I(d_inode(cfile->dentry))->flags);
if (cap_unix(tcon->ses) &&
(CIFS_UNIX_FCNTL_CAP & le64_to_cpu(tcon->fsUnixInfo.Capability)) &&
struct cifs_tcon *tcon;
struct cifs_sb_info *cifs_sb;
struct dentry *dentry = ctx->cfile->dentry;
- int rc;
+ ssize_t rc;
tcon = tlink_tcon(ctx->cfile->tlink);
cifs_sb = CIFS_SB(dentry->d_sb);
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/fscache.c - CIFS filesystem cache interface
+ * CIFS filesystem cache interface
*
* Copyright (c) 2010 Novell, Inc.
* Author(s): Suresh Jayaraman <sjayaraman@suse.de>
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/fscache.h - CIFS filesystem cache interface definitions
+ * CIFS filesystem cache interface definitions
*
* Copyright (c) 2010 Novell, Inc.
* Authors(s): Suresh Jayaraman (sjayaraman@suse.de>
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/inode.c
*
* Copyright (C) International Business Machines Corp., 2002,2010
* Author(s): Steve French (sfrench@us.ibm.com)
goto unlink_out;
}
- cifs_close_deferred_file(CIFS_I(inode));
+ cifs_close_deferred_file_under_dentry(tcon, full_path);
if (cap_unix(tcon->ses) && (CIFS_UNIX_POSIX_PATH_OPS_CAP &
le64_to_cpu(tcon->fsUnixInfo.Capability))) {
rc = CIFSPOSIXDelFile(xid, tcon, full_path,
goto cifs_rename_exit;
}
- cifs_close_deferred_file(CIFS_I(d_inode(source_dentry)));
+ cifs_close_deferred_file_under_dentry(tcon, from_name);
if (d_inode(target_dentry) != NULL)
- cifs_close_deferred_file(CIFS_I(d_inode(target_dentry)));
+ cifs_close_deferred_file_under_dentry(tcon, to_name);
rc = cifs_do_rename(xid, source_dentry, from_name, target_dentry,
to_name);
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/ioctl.c
*
* vfs operations that deal with io control
*
if (pSMBFile == NULL)
break;
tcon = tlink_tcon(pSMBFile->tlink);
- caps = le64_to_cpu(tcon->fsUnixInfo.Capability);
+ /* caps = le64_to_cpu(tcon->fsUnixInfo.Capability); */
if (get_user(ExtAttrBits, (int __user *)arg)) {
rc = -EFAULT;
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/link.c
*
* Copyright (C) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/misc.c
*
* Copyright (C) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
/* Uid is not converted */
buffer->Uid = treeCon->ses->Suid;
- buffer->Mid = get_next_mid(treeCon->ses->server);
+ if (treeCon->ses->server)
+ buffer->Mid = get_next_mid(treeCon->ses->server);
}
if (treeCon->Flags & SMB_SHARE_IS_IN_DFS)
buffer->Flags2 |= SMBFLG2_DFS;
/**
* cifs_queue_oplock_break - queue the oplock break handler for cfile
+ * @cfile: The file to break the oplock on
*
* This function is called from the demultiplex thread when it
* receives an oplock break for @cfile.
if (cancel_delayed_work(&cfile->deferred)) {
tmp_list = kmalloc(sizeof(struct file_list), GFP_ATOMIC);
if (tmp_list == NULL)
- continue;
+ break;
tmp_list->cfile = cfile;
list_add_tail(&tmp_list->list, &file_head);
}
if (cancel_delayed_work(&cfile->deferred)) {
tmp_list = kmalloc(sizeof(struct file_list), GFP_ATOMIC);
if (tmp_list == NULL)
- continue;
+ break;
tmp_list->cfile = cfile;
list_add_tail(&tmp_list->list, &file_head);
}
kfree(tmp_list);
}
}
+void
+cifs_close_deferred_file_under_dentry(struct cifs_tcon *tcon, const char *path)
+{
+ struct cifsFileInfo *cfile;
+ struct list_head *tmp;
+ struct file_list *tmp_list, *tmp_next_list;
+ struct list_head file_head;
+ void *page;
+ const char *full_path;
+
+ INIT_LIST_HEAD(&file_head);
+ page = alloc_dentry_path();
+ spin_lock(&tcon->open_file_lock);
+ list_for_each(tmp, &tcon->openFileList) {
+ cfile = list_entry(tmp, struct cifsFileInfo, tlist);
+ full_path = build_path_from_dentry(cfile->dentry, page);
+ if (strstr(full_path, path)) {
+ if (delayed_work_pending(&cfile->deferred)) {
+ if (cancel_delayed_work(&cfile->deferred)) {
+ tmp_list = kmalloc(sizeof(struct file_list), GFP_ATOMIC);
+ if (tmp_list == NULL)
+ break;
+ tmp_list->cfile = cfile;
+ list_add_tail(&tmp_list->list, &file_head);
+ }
+ }
+ }
+ }
+ spin_unlock(&tcon->open_file_lock);
+
+ list_for_each_entry_safe(tmp_list, tmp_next_list, &file_head, list) {
+ _cifsFileInfo_put(tmp_list->cfile, true, false);
+ list_del(&tmp_list->list);
+ kfree(tmp_list);
+ }
+ free_dentry_path(page);
+}
/* parses DFS refferal V3 structure
* caller is responsible for freeing target_nodes
/**
* cifs_alloc_hash - allocate hash and hash context together
+ * @name: The name of the crypto hash algo
+ * @shash: Where to put the pointer to the hash algo
+ * @sdesc: Where to put the pointer to the hash descriptor
*
* The caller has to make sure @sdesc is initialized to either NULL or
* a valid context. Both can be freed via cifs_free_hash().
/**
* cifs_free_hash - free hash and hash context together
+ * @shash: Where to find the pointer to the hash algo
+ * @sdesc: Where to find the pointer to the hash descriptor
*
* Freeing a NULL hash or context is safe.
*/
/**
* rqst_page_get_length - obtain the length and offset for a page in smb_rqst
- * Input: rqst - a smb_rqst, page - a page index for rqst
- * Output: *len - the length for this page, *offset - the offset for this page
+ * @rqst: The request descriptor
+ * @page: The index of the page to query
+ * @len: Where to store the length for this page:
+ * @offset: Where to store the offset for this page
*/
void rqst_page_get_length(struct smb_rqst *rqst, unsigned int page,
unsigned int *len, unsigned int *offset)
/**
* copy_path_name - copy src path to dst, possibly truncating
+ * @dst: The destination buffer
+ * @src: The source name
*
* returns number of bytes written (including trailing nul)
*/
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * fs/cifs/netmisc.c
*
* Copyright (c) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/ntlmssp.h
*
* Copyright (c) International Business Machines Corp., 2002,2007
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/readdir.c
*
* Directory search handling
*
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/rfc1002pdu.h
*
* Protocol Data Unit definitions for RFC 1001/1002 support
*
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/sess.c
*
* SMB/CIFS session setup handling routines
*
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/smb2file.c
*
* Copyright (C) International Business Machines Corp., 2002, 2011
* Author(s): Steve French (sfrench@us.ibm.com),
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/smb2glob.h
*
* Definitions for various global variables and structures
*
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/smb2inode.c
*
* Copyright (C) International Business Machines Corp., 2002, 2011
* Etersoft, 2012
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/smb2misc.c
*
* Copyright (C) International Business Machines Corp., 2002,2011
* Etersoft, 2012
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/smb2pdu.c
*
* Copyright (C) International Business Machines Corp., 2009, 2013
* Etersoft, 2012
buf->sd.OffsetDacl = cpu_to_le32(ptr - (__u8 *)&buf->sd);
/* Ship the ACL for now. we will copy it into buf later. */
aclptr = ptr;
- ptr += sizeof(struct cifs_acl);
+ ptr += sizeof(struct smb3_acl);
/* create one ACE to hold the mode embedded in reserved special SID */
acelen = setup_special_mode_ACE((struct cifs_ace *)ptr, (__u64)mode);
acl.AclRevision = ACL_REVISION; /* See 2.4.4.1 of MS-DTYP */
acl.AclSize = cpu_to_le16(acl_size);
acl.AceCount = cpu_to_le16(ace_count);
- memcpy(aclptr, &acl, sizeof(struct cifs_acl));
+ memcpy(aclptr, &acl, sizeof(struct smb3_acl));
buf->ccontext.DataLength = cpu_to_le32(ptr - (__u8 *)&buf->sd);
*len = roundup(ptr - (__u8 *)buf, 8);
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/smb2pdu.h
*
* Copyright (c) International Business Machines Corp., 2009, 2013
* Etersoft, 2012
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/smb2proto.h
*
* Copyright (c) International Business Machines Corp., 2002, 2011
* Etersoft, 2012
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/smb2status.h
*
* SMB2 Status code (network error) definitions
* Definitions are from MS-ERREF
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/smb2transport.c
*
* Copyright (C) International Business Machines Corp., 2002, 2011
* Etersoft, 2012
/* SPDX-License-Identifier: LGPL-2.1 */
/*
- * fs/cifs/smberr.h
*
* Copyright (c) International Business Machines Corp., 2002,2004
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/transport.c
*
* Copyright (C) International Business Machines Corp., 2002,2008
* Author(s): Steve French (sfrench@us.ibm.com)
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * fs/cifs/winucase.c
*
* Copyright (c) Jeffrey Layton <jlayton@redhat.com>, 2013
*
// SPDX-License-Identifier: LGPL-2.1
/*
- * fs/cifs/xattr.c
*
* Copyright (c) International Business Machines Corp., 2003, 2007
* Author(s): Steve French (sfrench@us.ibm.com)
}
if (vi->datalayout == EROFS_INODE_CHUNK_BASED) {
- if (!(vi->chunkformat & EROFS_CHUNK_FORMAT_ALL)) {
+ if (vi->chunkformat & ~EROFS_CHUNK_FORMAT_ALL) {
erofs_err(inode->i_sb,
"unsupported chunk format %x of nid %llu",
vi->chunkformat, vi->nid);
if (compacted_4b_initial == 32 / 4)
compacted_4b_initial = 0;
- if (vi->z_advise & Z_EROFS_ADVISE_COMPACTED_2B)
+ if ((vi->z_advise & Z_EROFS_ADVISE_COMPACTED_2B) &&
+ compacted_4b_initial < totalidx)
compacted_2b = rounddown(totalidx - compacted_4b_initial, 16);
else
compacted_2b = 0;
struct ext2_sb_info *sbi = EXT2_SB(sb);
if (block_group >= sbi->s_groups_count) {
- ext2_error (sb, "ext2_get_group_desc",
- "block_group >= groups_count - "
- "block_group = %d, groups_count = %lu",
- block_group, sbi->s_groups_count);
+ WARN(1, "block_group >= groups_count - "
+ "block_group = %d, groups_count = %lu",
+ block_group, sbi->s_groups_count);
return NULL;
}
group_desc = block_group >> EXT2_DESC_PER_BLOCK_BITS(sb);
offset = block_group & (EXT2_DESC_PER_BLOCK(sb) - 1);
if (!sbi->s_group_desc[group_desc]) {
- ext2_error (sb, "ext2_get_group_desc",
- "Group descriptor not loaded - "
- "block_group = %d, group_desc = %lu, desc = %lu",
- block_group, group_desc, offset);
+ WARN(1, "Group descriptor not loaded - "
+ "block_group = %d, group_desc = %lu, desc = %lu",
+ block_group, group_desc, offset);
return NULL;
}
mapping_set_gfp_mask(mapping, GFP_HIGHUSER_MOVABLE);
mapping->private_data = NULL;
mapping->writeback_index = 0;
- __init_rwsem(&mapping->invalidate_lock, "mapping.invalidate_lock",
- &sb->s_type->invalidate_lock_key);
+ init_rwsem(&mapping->invalidate_lock);
+ lockdep_set_class_and_name(&mapping->invalidate_lock,
+ &sb->s_type->invalidate_lock_key,
+ "mapping.invalidate_lock");
inode->i_private = NULL;
inode->i_mapping = mapping;
INIT_HLIST_HEAD(&inode->i_dentry); /* buggered by rcu freeing */
#include <linux/rculist_nulls.h>
#include <linux/cpu.h>
#include <linux/tracehook.h>
+#include <uapi/linux/io_uring.h>
#include "io-wq.h"
static void io_worker_exit(struct io_worker *worker)
{
struct io_wqe *wqe = worker->wqe;
- struct io_wqe_acct *acct = io_wqe_get_acct(worker);
if (refcount_dec_and_test(&worker->ref))
complete(&worker->ref_done);
if (worker->flags & IO_WORKER_F_FREE)
hlist_nulls_del_rcu(&worker->nulls_node);
list_del_rcu(&worker->all_list);
- acct->nr_workers--;
preempt_disable();
io_wqe_dec_running(worker);
worker->flags = 0;
*/
static bool io_wqe_create_worker(struct io_wqe *wqe, struct io_wqe_acct *acct)
{
- bool do_create = false;
-
/*
* Most likely an attempt to queue unbounded work on an io_wq that
* wasn't setup with any unbounded workers.
pr_warn_once("io-wq is not configured for unbound workers");
raw_spin_lock(&wqe->lock);
- if (acct->nr_workers < acct->max_workers) {
- acct->nr_workers++;
- do_create = true;
+ if (acct->nr_workers == acct->max_workers) {
+ raw_spin_unlock(&wqe->lock);
+ return true;
}
+ acct->nr_workers++;
raw_spin_unlock(&wqe->lock);
- if (do_create) {
- atomic_inc(&acct->nr_running);
- atomic_inc(&wqe->wq->worker_refs);
- return create_io_worker(wqe->wq, wqe, acct->index);
- }
-
- return true;
+ atomic_inc(&acct->nr_running);
+ atomic_inc(&wqe->wq->worker_refs);
+ return create_io_worker(wqe->wq, wqe, acct->index);
}
static void io_wqe_inc_running(struct io_worker *worker)
}
/* timed out, exit unless we're the last worker */
if (last_timeout && acct->nr_workers > 1) {
+ acct->nr_workers--;
raw_spin_unlock(&wqe->lock);
__set_current_state(TASK_RUNNING);
break;
if (!get_signal(&ksig))
continue;
- if (fatal_signal_pending(current))
+ if (fatal_signal_pending(current) ||
+ signal_group_exit(current->signal))
break;
continue;
}
{
int i, node, prev = 0;
+ BUILD_BUG_ON((int) IO_WQ_ACCT_BOUND != (int) IO_WQ_BOUND);
+ BUILD_BUG_ON((int) IO_WQ_ACCT_UNBOUND != (int) IO_WQ_UNBOUND);
+ BUILD_BUG_ON((int) IO_WQ_ACCT_NR != 2);
+
for (i = 0; i < 2; i++) {
if (new_count[i] > task_rlimit(current, RLIMIT_NPROC))
new_count[i] = task_rlimit(current, RLIMIT_NPROC);
struct io_close {
struct file *file;
int fd;
+ u32 file_slot;
};
struct io_timeout_data {
struct iovec fast_iov[UIO_FASTIOV];
const struct iovec *free_iovec;
struct iov_iter iter;
+ struct iov_iter_state iter_state;
size_t bytes_done;
struct wait_page_queue wpq;
};
REQ_F_BUFFER_SELECTED_BIT,
REQ_F_COMPLETE_INLINE_BIT,
REQ_F_REISSUE_BIT,
- REQ_F_DONT_REISSUE_BIT,
REQ_F_CREDS_BIT,
REQ_F_REFCOUNT_BIT,
REQ_F_ARM_LTIMEOUT_BIT,
REQ_F_COMPLETE_INLINE = BIT(REQ_F_COMPLETE_INLINE_BIT),
/* caller should reissue async */
REQ_F_REISSUE = BIT(REQ_F_REISSUE_BIT),
- /* don't attempt request reissue, see io_rw_reissue() */
- REQ_F_DONT_REISSUE = BIT(REQ_F_DONT_REISSUE_BIT),
/* supports async reads */
REQ_F_NOWAIT_READ = BIT(REQ_F_NOWAIT_READ_BIT),
/* supports async writes */
static int io_install_fixed_file(struct io_kiocb *req, struct file *file,
unsigned int issue_flags, u32 slot_index);
+static int io_close_fixed(struct io_kiocb *req, unsigned int issue_flags);
+
static enum hrtimer_restart io_link_timeout_fn(struct hrtimer *timer);
static struct kmem_cache *req_cachep;
req = list_first_entry(done, struct io_kiocb, inflight_entry);
list_del(&req->inflight_entry);
- if (READ_ONCE(req->result) == -EAGAIN &&
- !(req->flags & REQ_F_DONT_REISSUE)) {
- req->iopoll_completed = 0;
- io_req_task_queue_reissue(req);
- continue;
- }
-
__io_cqring_fill_event(ctx, req->user_data, req->result,
io_put_rw_kbuf(req));
(*nr_events)++;
if (!rw)
return !io_req_prep_async(req);
- /* may have left rw->iter inconsistent on -EIOCBQUEUED */
- iov_iter_revert(&rw->iter, req->result - iov_iter_count(&rw->iter));
+ iov_iter_restore(&rw->iter, &rw->iter_state);
return true;
}
if (kiocb->ki_flags & IOCB_WRITE)
kiocb_end_write(req);
if (unlikely(res != req->result)) {
- if (!(res == -EAGAIN && io_rw_should_reissue(req) &&
- io_resubmit_prep(req))) {
- req_set_fail(req);
- req->flags |= REQ_F_DONT_REISSUE;
+ if (res == -EAGAIN && io_rw_should_reissue(req)) {
+ req->flags |= REQ_F_REISSUE;
+ return;
}
}
return __io_file_supports_nowait(req->file, rw);
}
-static int io_prep_rw(struct io_kiocb *req, const struct io_uring_sqe *sqe)
+static int io_prep_rw(struct io_kiocb *req, const struct io_uring_sqe *sqe,
+ int rw)
{
struct io_ring_ctx *ctx = req->ctx;
struct kiocb *kiocb = &req->rw.kiocb;
if (unlikely(ret))
return ret;
- /* don't allow async punt for O_NONBLOCK or RWF_NOWAIT */
- if ((kiocb->ki_flags & IOCB_NOWAIT) || (file->f_flags & O_NONBLOCK))
+ /*
+ * If the file is marked O_NONBLOCK, still allow retry for it if it
+ * supports async. Otherwise it's impossible to use O_NONBLOCK files
+ * reliably. If not, or it IOCB_NOWAIT is set, don't retry.
+ */
+ if ((kiocb->ki_flags & IOCB_NOWAIT) ||
+ ((file->f_flags & O_NONBLOCK) && !io_file_supports_nowait(req, rw)))
req->flags |= REQ_F_NOWAIT;
ioprio = READ_ONCE(sqe->ioprio);
{
struct io_kiocb *req = container_of(kiocb, struct io_kiocb, rw.kiocb);
struct io_async_rw *io = req->async_data;
- bool check_reissue = kiocb->ki_complete == io_complete_rw;
/* add previously done IO, if any */
if (io && io->bytes_done > 0) {
if (req->flags & REQ_F_CUR_POS)
req->file->f_pos = kiocb->ki_pos;
- if (ret >= 0 && check_reissue)
+ if (ret >= 0 && (kiocb->ki_complete == io_complete_rw))
__io_complete_rw(req, ret, 0, issue_flags);
else
io_rw_done(kiocb, ret);
- if (check_reissue && (req->flags & REQ_F_REISSUE)) {
+ if (req->flags & REQ_F_REISSUE) {
req->flags &= ~REQ_F_REISSUE;
if (io_resubmit_prep(req)) {
io_req_task_queue_reissue(req);
} else {
+ unsigned int cflags = io_put_rw_kbuf(req);
+ struct io_ring_ctx *ctx = req->ctx;
+
req_set_fail(req);
- __io_req_complete(req, issue_flags, ret,
- io_put_rw_kbuf(req));
+ if (issue_flags & IO_URING_F_NONBLOCK) {
+ mutex_lock(&ctx->uring_lock);
+ __io_req_complete(req, issue_flags, ret, cflags);
+ mutex_unlock(&ctx->uring_lock);
+ } else {
+ __io_req_complete(req, issue_flags, ret, cflags);
+ }
}
}
}
ret = nr;
break;
}
+ if (!iov_iter_is_bvec(iter)) {
+ iov_iter_advance(iter, nr);
+ } else {
+ req->rw.len -= nr;
+ req->rw.addr += nr;
+ }
ret += nr;
if (nr != iovec.iov_len)
break;
- req->rw.len -= nr;
- req->rw.addr += nr;
- iov_iter_advance(iter, nr);
}
return ret;
if (!force && !io_op_defs[req->opcode].needs_async_setup)
return 0;
if (!req->async_data) {
+ struct io_async_rw *iorw;
+
if (io_alloc_async_data(req)) {
kfree(iovec);
return -ENOMEM;
}
io_req_map_rw(req, iovec, fast_iov, iter);
+ iorw = req->async_data;
+ /* we've copied and mapped the iter, ensure state is saved */
+ iov_iter_save_state(&iorw->iter, &iorw->iter_state);
}
return 0;
}
iorw->free_iovec = iov;
if (iov)
req->flags |= REQ_F_NEED_CLEANUP;
+ iov_iter_save_state(&iorw->iter, &iorw->iter_state);
return 0;
}
{
if (unlikely(!(req->file->f_mode & FMODE_READ)))
return -EBADF;
- return io_prep_rw(req, sqe);
+ return io_prep_rw(req, sqe, READ);
}
/*
struct kiocb *kiocb = &req->rw.kiocb;
struct iov_iter __iter, *iter = &__iter;
struct io_async_rw *rw = req->async_data;
- ssize_t io_size, ret, ret2;
bool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;
+ struct iov_iter_state __state, *state;
+ ssize_t ret, ret2;
if (rw) {
iter = &rw->iter;
+ state = &rw->iter_state;
+ /*
+ * We come here from an earlier attempt, restore our state to
+ * match in case it doesn't. It's cheap enough that we don't
+ * need to make this conditional.
+ */
+ iov_iter_restore(iter, state);
iovec = NULL;
} else {
ret = io_import_iovec(READ, req, &iovec, iter, !force_nonblock);
if (ret < 0)
return ret;
+ state = &__state;
+ iov_iter_save_state(iter, state);
}
- io_size = iov_iter_count(iter);
- req->result = io_size;
+ req->result = iov_iter_count(iter);
/* Ensure we clear previously set non-block flag */
if (!force_nonblock)
return ret ?: -EAGAIN;
}
- ret = rw_verify_area(READ, req->file, io_kiocb_ppos(kiocb), io_size);
+ ret = rw_verify_area(READ, req->file, io_kiocb_ppos(kiocb), req->result);
if (unlikely(ret)) {
kfree(iovec);
return ret;
/* no retry on NONBLOCK nor RWF_NOWAIT */
if (req->flags & REQ_F_NOWAIT)
goto done;
- /* some cases will consume bytes even on error returns */
- iov_iter_reexpand(iter, iter->count + iter->truncated);
- iov_iter_revert(iter, io_size - iov_iter_count(iter));
ret = 0;
} else if (ret == -EIOCBQUEUED) {
goto out_free;
- } else if (ret <= 0 || ret == io_size || !force_nonblock ||
+ } else if (ret <= 0 || ret == req->result || !force_nonblock ||
(req->flags & REQ_F_NOWAIT) || !need_read_all(req)) {
/* read all, failed, already did sync or don't want to retry */
goto done;
}
+ /*
+ * Don't depend on the iter state matching what was consumed, or being
+ * untouched in case of error. Restore it and we'll advance it
+ * manually if we need to.
+ */
+ iov_iter_restore(iter, state);
+
ret2 = io_setup_async_rw(req, iovec, inline_vecs, iter, true);
if (ret2)
return ret2;
iovec = NULL;
rw = req->async_data;
- /* now use our persistent iterator, if we aren't already */
- iter = &rw->iter;
+ /*
+ * Now use our persistent iterator and state, if we aren't already.
+ * We've restored and mapped the iter to match.
+ */
+ if (iter != &rw->iter) {
+ iter = &rw->iter;
+ state = &rw->iter_state;
+ }
do {
- io_size -= ret;
+ /*
+ * We end up here because of a partial read, either from
+ * above or inside this loop. Advance the iter by the bytes
+ * that were consumed.
+ */
+ iov_iter_advance(iter, ret);
+ if (!iov_iter_count(iter))
+ break;
rw->bytes_done += ret;
+ iov_iter_save_state(iter, state);
+
/* if we can retry, do so with the callbacks armed */
if (!io_rw_should_retry(req)) {
kiocb->ki_flags &= ~IOCB_WAITQ;
return 0;
/* we got some bytes, but not all. retry. */
kiocb->ki_flags &= ~IOCB_WAITQ;
- } while (ret > 0 && ret < io_size);
+ iov_iter_restore(iter, state);
+ } while (ret > 0);
done:
kiocb_done(kiocb, ret, issue_flags);
out_free:
{
if (unlikely(!(req->file->f_mode & FMODE_WRITE)))
return -EBADF;
- return io_prep_rw(req, sqe);
+ return io_prep_rw(req, sqe, WRITE);
}
static int io_write(struct io_kiocb *req, unsigned int issue_flags)
struct kiocb *kiocb = &req->rw.kiocb;
struct iov_iter __iter, *iter = &__iter;
struct io_async_rw *rw = req->async_data;
- ssize_t ret, ret2, io_size;
bool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;
+ struct iov_iter_state __state, *state;
+ ssize_t ret, ret2;
if (rw) {
iter = &rw->iter;
+ state = &rw->iter_state;
+ iov_iter_restore(iter, state);
iovec = NULL;
} else {
ret = io_import_iovec(WRITE, req, &iovec, iter, !force_nonblock);
if (ret < 0)
return ret;
+ state = &__state;
+ iov_iter_save_state(iter, state);
}
- io_size = iov_iter_count(iter);
- req->result = io_size;
+ req->result = iov_iter_count(iter);
/* Ensure we clear previously set non-block flag */
if (!force_nonblock)
(req->flags & REQ_F_ISREG))
goto copy_iov;
- ret = rw_verify_area(WRITE, req->file, io_kiocb_ppos(kiocb), io_size);
+ ret = rw_verify_area(WRITE, req->file, io_kiocb_ppos(kiocb), req->result);
if (unlikely(ret))
goto out_free;
kiocb_done(kiocb, ret2, issue_flags);
} else {
copy_iov:
- /* some cases will consume bytes even on error returns */
- iov_iter_reexpand(iter, iter->count + iter->truncated);
- iov_iter_revert(iter, io_size - iov_iter_count(iter));
+ iov_iter_restore(iter, state);
ret = io_setup_async_rw(req, iovec, inline_vecs, iter, false);
return ret ?: -EAGAIN;
}
int i, bid = pbuf->bid;
for (i = 0; i < pbuf->nbufs; i++) {
- buf = kmalloc(sizeof(*buf), GFP_KERNEL);
+ buf = kmalloc(sizeof(*buf), GFP_KERNEL_ACCOUNT);
if (!buf)
break;
if (unlikely(req->ctx->flags & IORING_SETUP_IOPOLL))
return -EINVAL;
if (sqe->ioprio || sqe->off || sqe->addr || sqe->len ||
- sqe->rw_flags || sqe->buf_index || sqe->splice_fd_in)
+ sqe->rw_flags || sqe->buf_index)
return -EINVAL;
if (req->flags & REQ_F_FIXED_FILE)
return -EBADF;
req->close.fd = READ_ONCE(sqe->fd);
+ req->close.file_slot = READ_ONCE(sqe->file_index);
+ if (req->close.file_slot && req->close.fd)
+ return -EINVAL;
+
return 0;
}
struct file *file = NULL;
int ret = -EBADF;
+ if (req->close.file_slot) {
+ ret = io_close_fixed(req, issue_flags);
+ goto err;
+ }
+
spin_lock(&files->file_lock);
fdt = files_fdtable(files);
if (close->fd >= fdt->max_fds) {
if (req->poll.events & EPOLLONESHOT)
flags = 0;
if (!io_cqring_fill_event(ctx, req->user_data, error, flags)) {
- req->poll.done = true;
+ req->poll.events |= EPOLLONESHOT;
flags = 0;
}
if (flags & IORING_CQE_F_MORE)
} else {
bool done;
+ if (req->poll.done) {
+ spin_unlock(&ctx->completion_lock);
+ return;
+ }
done = __io_poll_complete(req, req->result);
if (done) {
io_poll_remove_double(req);
hash_del(&req->hash_node);
+ req->poll.done = true;
} else {
req->result = 0;
add_wait_queue(req->poll.head, &req->poll.wait);
hash_del(&req->hash_node);
io_poll_remove_double(req);
+ apoll->poll.done = true;
spin_unlock(&ctx->completion_lock);
if (!READ_ONCE(apoll->poll.canceled))
struct io_ring_ctx *ctx = req->ctx;
struct io_poll_table ipt;
__poll_t mask;
+ bool done;
ipt.pt._qproc = io_poll_queue_proc;
if (mask) { /* no async, we'd stolen it */
ipt.error = 0;
- io_poll_complete(req, mask);
+ done = io_poll_complete(req, mask);
}
spin_unlock(&ctx->completion_lock);
if (mask) {
io_cqring_ev_posted(ctx);
- if (poll->events & EPOLLONESHOT)
+ if (done)
io_put_req(req);
}
return ipt.error;
struct io_uring_rsrc_update2 up;
int ret;
- if (issue_flags & IO_URING_F_NONBLOCK)
- return -EAGAIN;
-
up.offset = req->rsrc_update.offset;
up.data = req->rsrc_update.arg;
up.nr = 0;
up.tags = 0;
up.resv = 0;
- mutex_lock(&ctx->uring_lock);
+ io_ring_submit_lock(ctx, !(issue_flags & IO_URING_F_NONBLOCK));
ret = __io_register_rsrc_update(ctx, IORING_RSRC_FILE,
&up, req->rsrc_update.nr_args);
- mutex_unlock(&ctx->uring_lock);
+ io_ring_submit_unlock(ctx, !(issue_flags & IO_URING_F_NONBLOCK));
if (ret < 0)
req_set_fail(req);
break;
} while (1);
+ if (uts) {
+ struct timespec64 ts;
+
+ if (get_timespec64(&ts, uts))
+ return -EFAULT;
+ timeout = timespec64_to_jiffies(&ts);
+ }
+
if (sig) {
#ifdef CONFIG_COMPAT
if (in_compat_syscall())
return ret;
}
- if (uts) {
- struct timespec64 ts;
-
- if (get_timespec64(&ts, uts))
- return -EFAULT;
- timeout = timespec64_to_jiffies(&ts);
- }
-
init_waitqueue_func_entry(&iowq.wq, io_wake_function);
iowq.wq.private = current;
INIT_LIST_HEAD(&iowq.wq.entry);
#endif
}
+static int io_queue_rsrc_removal(struct io_rsrc_data *data, unsigned idx,
+ struct io_rsrc_node *node, void *rsrc)
+{
+ struct io_rsrc_put *prsrc;
+
+ prsrc = kzalloc(sizeof(*prsrc), GFP_KERNEL);
+ if (!prsrc)
+ return -ENOMEM;
+
+ prsrc->tag = *io_get_tag_slot(data, idx);
+ prsrc->rsrc = rsrc;
+ list_add(&prsrc->list, &node->rsrc_list);
+ return 0;
+}
+
static int io_install_fixed_file(struct io_kiocb *req, struct file *file,
unsigned int issue_flags, u32 slot_index)
{
struct io_ring_ctx *ctx = req->ctx;
bool force_nonblock = issue_flags & IO_URING_F_NONBLOCK;
+ bool needs_switch = false;
struct io_fixed_file *file_slot;
int ret = -EBADF;
slot_index = array_index_nospec(slot_index, ctx->nr_user_files);
file_slot = io_fixed_file_slot(&ctx->file_table, slot_index);
- ret = -EBADF;
- if (file_slot->file_ptr)
- goto err;
+
+ if (file_slot->file_ptr) {
+ struct file *old_file;
+
+ ret = io_rsrc_node_switch_start(ctx);
+ if (ret)
+ goto err;
+
+ old_file = (struct file *)(file_slot->file_ptr & FFS_MASK);
+ ret = io_queue_rsrc_removal(ctx->file_data, slot_index,
+ ctx->rsrc_node, old_file);
+ if (ret)
+ goto err;
+ file_slot->file_ptr = 0;
+ needs_switch = true;
+ }
*io_get_tag_slot(ctx->file_data, slot_index) = 0;
io_fixed_file_set(file_slot, file);
ret = 0;
err:
+ if (needs_switch)
+ io_rsrc_node_switch(ctx, ctx->file_data);
io_ring_submit_unlock(ctx, !force_nonblock);
if (ret)
fput(file);
return ret;
}
-static int io_queue_rsrc_removal(struct io_rsrc_data *data, unsigned idx,
- struct io_rsrc_node *node, void *rsrc)
+static int io_close_fixed(struct io_kiocb *req, unsigned int issue_flags)
{
- struct io_rsrc_put *prsrc;
+ unsigned int offset = req->close.file_slot - 1;
+ struct io_ring_ctx *ctx = req->ctx;
+ struct io_fixed_file *file_slot;
+ struct file *file;
+ int ret, i;
- prsrc = kzalloc(sizeof(*prsrc), GFP_KERNEL);
- if (!prsrc)
- return -ENOMEM;
+ io_ring_submit_lock(ctx, !(issue_flags & IO_URING_F_NONBLOCK));
+ ret = -ENXIO;
+ if (unlikely(!ctx->file_data))
+ goto out;
+ ret = -EINVAL;
+ if (offset >= ctx->nr_user_files)
+ goto out;
+ ret = io_rsrc_node_switch_start(ctx);
+ if (ret)
+ goto out;
- prsrc->tag = *io_get_tag_slot(data, idx);
- prsrc->rsrc = rsrc;
- list_add(&prsrc->list, &node->rsrc_list);
- return 0;
+ i = array_index_nospec(offset, ctx->nr_user_files);
+ file_slot = io_fixed_file_slot(&ctx->file_table, i);
+ ret = -EBADF;
+ if (!file_slot->file_ptr)
+ goto out;
+
+ file = (struct file *)(file_slot->file_ptr & FFS_MASK);
+ ret = io_queue_rsrc_removal(ctx->file_data, offset, ctx->rsrc_node, file);
+ if (ret)
+ goto out;
+
+ file_slot->file_ptr = 0;
+ io_rsrc_node_switch(ctx, ctx->file_data);
+ ret = 0;
+out:
+ io_ring_submit_unlock(ctx, !(issue_flags & IO_URING_F_NONBLOCK));
+ return ret;
}
static int __io_sqe_files_update(struct io_ring_ctx *ctx,
struct io_buffer *buf;
unsigned long index;
- xa_for_each(&ctx->io_buffers, index, buf)
+ xa_for_each(&ctx->io_buffers, index, buf) {
__io_remove_buffers(ctx, buf, index, -1U);
+ cond_resched();
+ }
}
static void io_req_cache_free(struct list_head *list)
struct io_tctx_node *node;
unsigned long index;
- xa_for_each(&tctx->xa, index, node)
+ xa_for_each(&tctx->xa, index, node) {
io_uring_del_tctx_node(index);
+ cond_resched();
+ }
if (wq) {
/*
* Must be after io_uring_del_task_file() (removes nodes under
* ordering. Fine to drop uring_lock here, we hold
* a ref to the ctx.
*/
+ refcount_inc(&sqd->refs);
mutex_unlock(&ctx->uring_lock);
mutex_lock(&sqd->lock);
mutex_lock(&ctx->uring_lock);
- tctx = sqd->thread->io_uring;
+ if (sqd->thread)
+ tctx = sqd->thread->io_uring;
}
} else {
tctx = current->io_uring;
if (ret)
goto err;
- if (sqd)
+ if (sqd) {
mutex_unlock(&sqd->lock);
+ io_put_sq_data(sqd);
+ }
if (copy_to_user(arg, new_count, sizeof(new_count)))
return -EFAULT;
return 0;
err:
- if (sqd)
+ if (sqd) {
mutex_unlock(&sqd->lock);
+ io_put_sq_data(sqd);
+ }
return ret;
}
* Return : windows path string or error
*/
-char *convert_to_nt_pathname(char *filename, char *sharepath)
+char *convert_to_nt_pathname(char *filename)
{
char *ab_pathname;
- int len, name_len;
- name_len = strlen(filename);
- ab_pathname = kmalloc(name_len, GFP_KERNEL);
- if (!ab_pathname)
- return NULL;
-
- ab_pathname[0] = '\\';
- ab_pathname[1] = '\0';
+ if (strlen(filename) == 0) {
+ ab_pathname = kmalloc(2, GFP_KERNEL);
+ ab_pathname[0] = '\\';
+ ab_pathname[1] = '\0';
+ } else {
+ ab_pathname = kstrdup(filename, GFP_KERNEL);
+ if (!ab_pathname)
+ return NULL;
- len = strlen(sharepath);
- if (!strncmp(filename, sharepath, len) && name_len != len) {
- strscpy(ab_pathname, &filename[len], name_len);
ksmbd_conv_path_to_windows(ab_pathname);
}
-
return ab_pathname;
}
*
* Return: converted name on success, otherwise NULL
*/
-char *convert_to_unix_name(struct ksmbd_share_config *share, char *name)
+char *convert_to_unix_name(struct ksmbd_share_config *share, const char *name)
{
int no_slash = 0, name_len, path_len;
char *new_name;
int match_pattern(const char *str, size_t len, const char *pattern);
int ksmbd_validate_filename(char *filename);
int parse_stream_name(char *filename, char **stream_name, int *s_type);
-char *convert_to_nt_pathname(char *filename, char *sharepath);
+char *convert_to_nt_pathname(char *filename);
int get_nlink(struct kstat *st);
void ksmbd_conv_path_to_unix(char *path);
void ksmbd_strip_last_slash(char *path);
void ksmbd_conv_path_to_windows(char *path);
char *ksmbd_extract_sharename(char *treename);
-char *convert_to_unix_name(struct ksmbd_share_config *share, char *name);
+char *convert_to_unix_name(struct ksmbd_share_config *share, const char *name);
#define KSMBD_DIR_INFO_ALIGNMENT 8
struct ksmbd_dir_info;
ret = ksmbd_workqueue_init();
if (ret)
goto err_crypto_destroy;
+
+ pr_warn_once("The ksmbd server is experimental, use at your own risk.\n");
+
return 0;
err_crypto_destroy:
work->compound_pfid = KSMBD_NO_FID;
}
memset((char *)rsp_hdr + 4, 0, sizeof(struct smb2_hdr) + 2);
- rsp_hdr->ProtocolId = rcv_hdr->ProtocolId;
+ rsp_hdr->ProtocolId = SMB2_PROTO_NUMBER;
rsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE;
rsp_hdr->Command = rcv_hdr->Command;
smb2_get_name(struct ksmbd_share_config *share, const char *src,
const int maxlen, struct nls_table *local_nls)
{
- char *name, *unixname;
+ char *name;
name = smb_strndup_from_utf16(src, maxlen, 1, local_nls);
if (IS_ERR(name)) {
return name;
}
- /* change it to absolute unix name */
ksmbd_conv_path_to_unix(name);
ksmbd_strip_last_slash(name);
-
- unixname = convert_to_unix_name(share, name);
- kfree(name);
- if (!unixname) {
- pr_err("can not convert absolute name\n");
- return ERR_PTR(-ENOMEM);
- }
-
- ksmbd_debug(SMB, "absolute name = %s\n", unixname);
- return unixname;
+ return name;
}
int setup_async_work(struct ksmbd_work *work, void (*fn)(void **), void **arg)
return rc;
}
- rc = ksmbd_vfs_kern_path(name, 0, path, 0);
+ rc = ksmbd_vfs_kern_path(work, name, 0, path, 0);
if (rc) {
pr_err("cannot get linux path (%s), err = %d\n",
name, rc);
struct oplock_info *opinfo;
__le32 *next_ptr = NULL;
int req_op_level = 0, open_flags = 0, may_flags = 0, file_info = 0;
- int rc = 0, len = 0;
+ int rc = 0;
int contxt_cnt = 0, query_disk_id = 0;
int maximal_access_ctxt = 0, posix_ctxt = 0;
int s_type = 0;
goto err_out1;
}
} else {
- len = strlen(share->path);
- ksmbd_debug(SMB, "share path len %d\n", len);
- name = kmalloc(len + 1, GFP_KERNEL);
+ name = kstrdup("", GFP_KERNEL);
if (!name) {
- rsp->hdr.Status = STATUS_NO_MEMORY;
rc = -ENOMEM;
goto err_out1;
}
-
- memcpy(name, share->path, len);
- *(name + len) = '\0';
}
req_op_level = req->RequestedOplockLevel;
goto err_out1;
}
- if (req->CreateOptions & FILE_DELETE_ON_CLOSE_LE) {
- /*
- * On delete request, instead of following up, need to
- * look the current entity
- */
- rc = ksmbd_vfs_kern_path(name, 0, &path, 1);
- if (!rc) {
+ rc = ksmbd_vfs_kern_path(work, name, LOOKUP_NO_SYMLINKS, &path, 1);
+ if (!rc) {
+ if (req->CreateOptions & FILE_DELETE_ON_CLOSE_LE) {
/*
* If file exists with under flags, return access
* denied error.
path_put(&path);
goto err_out;
}
- }
- } else {
- if (test_share_config_flag(work->tcon->share_conf,
- KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS)) {
- /*
- * Use LOOKUP_FOLLOW to follow the path of
- * symlink in path buildup
- */
- rc = ksmbd_vfs_kern_path(name, LOOKUP_FOLLOW, &path, 1);
- if (rc) { /* Case for broken link ?*/
- rc = ksmbd_vfs_kern_path(name, 0, &path, 1);
- }
- } else {
- rc = ksmbd_vfs_kern_path(name, 0, &path, 1);
- if (!rc && d_is_symlink(path.dentry)) {
- rc = -EACCES;
- path_put(&path);
- goto err_out;
- }
+ } else if (d_is_symlink(path.dentry)) {
+ rc = -EACCES;
+ path_put(&path);
+ goto err_out;
}
}
if (rc) {
- if (rc == -EACCES) {
- ksmbd_debug(SMB,
- "User does not have right permission\n");
+ if (rc != -ENOENT)
goto err_out;
- }
ksmbd_debug(SMB, "can not get linux path for %s, rc = %d\n",
name, rc);
rc = 0;
rsp->hdr.Status = STATUS_INVALID_PARAMETER;
else if (rc == -EOPNOTSUPP)
rsp->hdr.Status = STATUS_NOT_SUPPORTED;
- else if (rc == -EACCES || rc == -ESTALE)
+ else if (rc == -EACCES || rc == -ESTALE || rc == -EXDEV)
rsp->hdr.Status = STATUS_ACCESS_DENIED;
else if (rc == -ENOENT)
rsp->hdr.Status = STATUS_OBJECT_NAME_INVALID;
path = &fp->filp->f_path;
/* single EA entry is requested with given user.* name */
if (req->InputBufferLength) {
+ if (le32_to_cpu(req->InputBufferLength) <
+ sizeof(struct smb2_ea_info_req))
+ return -EINVAL;
+
ea_req = (struct smb2_ea_info_req *)req->Buffer;
} else {
/* need to send all EAs, if no specific EA is requested*/
return -EACCES;
}
- filename = convert_to_nt_pathname(fp->filename,
- work->tcon->share_conf->path);
+ filename = convert_to_nt_pathname(fp->filename);
if (!filename)
return -ENOMEM;
file_info->NextEntryOffset = cpu_to_le32(next);
}
- if (nbytes) {
+ if (!S_ISDIR(stat.mode)) {
file_info = (struct smb2_file_stream_info *)
&rsp->Buffer[nbytes];
streamlen = smbConvertToUTF16((__le16 *)file_info->StreamName,
"::$DATA", 7, conn->local_nls, 0);
streamlen *= 2;
file_info->StreamNameLength = cpu_to_le32(streamlen);
- file_info->StreamSize = S_ISDIR(stat.mode) ? 0 :
- cpu_to_le64(stat.size);
- file_info->StreamAllocationSize = S_ISDIR(stat.mode) ? 0 :
- cpu_to_le64(stat.size);
+ file_info->StreamSize = 0;
+ file_info->StreamAllocationSize = 0;
nbytes += sizeof(struct smb2_file_stream_info) + streamlen;
}
struct path path;
int rc = 0, len;
int fs_infoclass_size = 0;
- int lookup_flags = 0;
-
- if (test_share_config_flag(share, KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS))
- lookup_flags = LOOKUP_FOLLOW;
- rc = ksmbd_vfs_kern_path(share->path, lookup_flags, &path, 0);
+ rc = kern_path(share->path, LOOKUP_NO_SYMLINKS, &path);
if (rc) {
pr_err("cannot create vfs path\n");
return -EIO;
goto out;
len = strlen(new_name);
- if (new_name[len - 1] != '/') {
+ if (len > 0 && new_name[len - 1] != '/') {
pr_err("not allow base filename in rename\n");
rc = -ESHARE;
goto out;
}
ksmbd_debug(SMB, "new name %s\n", new_name);
- rc = ksmbd_vfs_kern_path(new_name, 0, &path, 1);
- if (rc)
+ rc = ksmbd_vfs_kern_path(work, new_name, LOOKUP_NO_SYMLINKS, &path, 1);
+ if (rc) {
+ if (rc != -ENOENT)
+ goto out;
file_present = false;
- else
+ } else {
path_put(&path);
+ }
if (ksmbd_share_veto_filename(share, new_name)) {
rc = -ENOENT;
}
ksmbd_debug(SMB, "target name is %s\n", target_name);
- rc = ksmbd_vfs_kern_path(link_name, 0, &path, 0);
- if (rc)
+ rc = ksmbd_vfs_kern_path(work, link_name, LOOKUP_NO_SYMLINKS, &path, 0);
+ if (rc) {
+ if (rc != -ENOENT)
+ goto out;
file_present = false;
- else
+ } else {
path_put(&path);
+ }
if (file_info->ReplaceIfExists) {
if (file_present) {
* inode size is retained by backup inode size.
*/
size = i_size_read(inode);
- rc = ksmbd_vfs_truncate(work, NULL, fp, alloc_blks * 512);
+ rc = ksmbd_vfs_truncate(work, fp, alloc_blks * 512);
if (rc) {
pr_err("truncate failed! filename : %s, err %d\n",
fp->filename, rc);
if (inode->i_sb->s_magic != MSDOS_SUPER_MAGIC) {
ksmbd_debug(SMB, "filename : %s truncated to newsize %lld\n",
fp->filename, newsize);
- rc = ksmbd_vfs_truncate(work, NULL, fp, newsize);
+ rc = ksmbd_vfs_truncate(work, fp, newsize);
if (rc) {
ksmbd_debug(SMB, "truncate failed! filename : %s err %d\n",
fp->filename, rc);
return 0;
err_out:
- if (rc == -EACCES || rc == -EPERM)
+ if (rc == -EACCES || rc == -EPERM || rc == -EXDEV)
rsp->hdr.Status = STATUS_ACCESS_DENIED;
else if (rc == -EINVAL)
rsp->hdr.Status = STATUS_INVALID_PARAMETER;
*
* check for valid smb signature and packet direction(request/response)
*
- * Return: 0 on success, otherwise 1
+ * Return: 0 on success, otherwise -EINVAL
*/
int ksmbd_verify_smb_message(struct ksmbd_work *work)
{
- struct smb2_hdr *smb2_hdr = work->request_buf;
+ struct smb2_hdr *smb2_hdr = work->request_buf + work->next_smb2_rcv_hdr_off;
+ struct smb_hdr *hdr;
if (smb2_hdr->ProtocolId == SMB2_PROTO_NUMBER)
return ksmbd_smb2_check_message(work);
- return 0;
+ hdr = work->request_buf;
+ if (*(__le32 *)hdr->Protocol == SMB1_PROTO_NUMBER &&
+ hdr->Command == SMB_COM_NEGOTIATE)
+ return 0;
+
+ return -EINVAL;
}
/**
return BAD_PROT_ID;
}
-#define SMB_COM_NEGOTIATE 0x72
int ksmbd_init_smb_server(struct ksmbd_work *work)
{
struct ksmbd_conn *conn = work->conn;
FILE_READ_ATTRIBUTES | FILE_WRITE_ATTRIBUTES)
#define SMB1_PROTO_NUMBER cpu_to_le32(0x424d53ff)
+#define SMB_COM_NEGOTIATE 0x72
#define SMB1_CLIENT_GUID_SIZE (16)
struct smb_hdr {
#define SUBMOD_NAME "smb_direct"
#include <linux/kthread.h>
-#include <linux/rwlock.h>
#include <linux/list.h>
#include <linux/mempool.h>
#include <linux/highmem.h>
#include <linux/sched/xacct.h>
#include <linux/crc32c.h>
+#include "../internal.h" /* for vfs_path_lookup */
+
#include "glob.h"
#include "oplock.h"
#include "connection.h"
p++;
} else {
p = NULL;
- pr_err("Invalid path %s\n", path);
}
return p;
}
/**
* ksmbd_vfs_create() - vfs helper for smb create file
* @work: work
- * @name: file name
+ * @name: file name that is relative to share
* @mode: file create mode
*
* Return: 0 on success, otherwise error
struct dentry *dentry;
int err;
- dentry = kern_path_create(AT_FDCWD, name, &path, 0);
+ dentry = ksmbd_vfs_kern_path_create(work, name,
+ LOOKUP_NO_SYMLINKS, &path);
if (IS_ERR(dentry)) {
err = PTR_ERR(dentry);
if (err != -ENOENT)
/**
* ksmbd_vfs_mkdir() - vfs helper for smb create directory
* @work: work
- * @name: directory name
+ * @name: directory name that is relative to share
* @mode: directory create mode
*
* Return: 0 on success, otherwise error
struct dentry *dentry;
int err;
- dentry = kern_path_create(AT_FDCWD, name, &path, LOOKUP_DIRECTORY);
+ dentry = ksmbd_vfs_kern_path_create(work, name,
+ LOOKUP_NO_SYMLINKS | LOOKUP_DIRECTORY,
+ &path);
if (IS_ERR(dentry)) {
err = PTR_ERR(dentry);
if (err != -EEXIST)
/**
* ksmbd_vfs_remove_file() - vfs helper for smb rmdir or unlink
- * @name: absolute directory or file name
+ * @name: directory or file name that is relative to share
*
* Return: 0 on success, otherwise error
*/
struct path path;
struct dentry *parent;
int err;
- int flags = 0;
if (ksmbd_override_fsids(work))
return -ENOMEM;
- if (test_share_config_flag(work->tcon->share_conf,
- KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS))
- flags = LOOKUP_FOLLOW;
-
- err = kern_path(name, flags, &path);
+ err = ksmbd_vfs_kern_path(work, name, LOOKUP_NO_SYMLINKS, &path, false);
if (err) {
ksmbd_debug(VFS, "can't get %s, err %d\n", name, err);
ksmbd_revert_fsids(work);
/**
* ksmbd_vfs_link() - vfs helper for creating smb hardlink
* @oldname: source file name
- * @newname: hardlink name
+ * @newname: hardlink name that is relative to share
*
* Return: 0 on success, otherwise error
*/
struct path oldpath, newpath;
struct dentry *dentry;
int err;
- int flags = 0;
if (ksmbd_override_fsids(work))
return -ENOMEM;
- if (test_share_config_flag(work->tcon->share_conf,
- KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS))
- flags = LOOKUP_FOLLOW;
-
- err = kern_path(oldname, flags, &oldpath);
+ err = kern_path(oldname, LOOKUP_NO_SYMLINKS, &oldpath);
if (err) {
pr_err("cannot get linux path for %s, err = %d\n",
oldname, err);
goto out1;
}
- dentry = kern_path_create(AT_FDCWD, newname, &newpath,
- flags | LOOKUP_REVAL);
+ dentry = ksmbd_vfs_kern_path_create(work, newname,
+ LOOKUP_NO_SYMLINKS | LOOKUP_REVAL,
+ &newpath);
if (IS_ERR(dentry)) {
err = PTR_ERR(dentry);
pr_err("path create err for %s, err %d\n", newname, err);
struct dentry *src_dent, *trap_dent, *src_child;
char *dst_name;
int err;
- int flags;
dst_name = extract_last_component(newname);
- if (!dst_name)
- return -EINVAL;
+ if (!dst_name) {
+ dst_name = newname;
+ newname = "";
+ }
src_dent_parent = dget_parent(fp->filp->f_path.dentry);
src_dent = fp->filp->f_path.dentry;
- flags = LOOKUP_DIRECTORY;
- if (test_share_config_flag(work->tcon->share_conf,
- KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS))
- flags |= LOOKUP_FOLLOW;
-
- err = kern_path(newname, flags, &dst_path);
+ err = ksmbd_vfs_kern_path(work, newname,
+ LOOKUP_NO_SYMLINKS | LOOKUP_DIRECTORY,
+ &dst_path, false);
if (err) {
ksmbd_debug(VFS, "Cannot get path for %s [%d]\n", newname, err);
goto out;
/**
* ksmbd_vfs_truncate() - vfs helper for smb file truncate
* @work: work
- * @name: old filename
* @fid: file id of old file
* @size: truncate to given size
*
* Return: 0 on success, otherwise error
*/
-int ksmbd_vfs_truncate(struct ksmbd_work *work, const char *name,
+int ksmbd_vfs_truncate(struct ksmbd_work *work,
struct ksmbd_file *fp, loff_t size)
{
- struct path path;
int err = 0;
+ struct file *filp;
- if (name) {
- err = kern_path(name, 0, &path);
- if (err) {
- pr_err("cannot get linux path for %s, err %d\n",
- name, err);
- return err;
- }
- err = vfs_truncate(&path, size);
- if (err)
- pr_err("truncate failed for %s err %d\n",
- name, err);
- path_put(&path);
- } else {
- struct file *filp;
-
- filp = fp->filp;
-
- /* Do we need to break any of a levelII oplock? */
- smb_break_all_levII_oplock(work, fp, 1);
+ filp = fp->filp;
- if (!work->tcon->posix_extensions) {
- struct inode *inode = file_inode(filp);
+ /* Do we need to break any of a levelII oplock? */
+ smb_break_all_levII_oplock(work, fp, 1);
- if (size < inode->i_size) {
- err = check_lock_range(filp, size,
- inode->i_size - 1, WRITE);
- } else {
- err = check_lock_range(filp, inode->i_size,
- size - 1, WRITE);
- }
+ if (!work->tcon->posix_extensions) {
+ struct inode *inode = file_inode(filp);
- if (err) {
- pr_err("failed due to lock\n");
- return -EAGAIN;
- }
+ if (size < inode->i_size) {
+ err = check_lock_range(filp, size,
+ inode->i_size - 1, WRITE);
+ } else {
+ err = check_lock_range(filp, inode->i_size,
+ size - 1, WRITE);
}
- err = vfs_truncate(&filp->f_path, size);
- if (err)
- pr_err("truncate failed for filename : %s err %d\n",
- fp->filename, err);
+ if (err) {
+ pr_err("failed due to lock\n");
+ return -EAGAIN;
+ }
}
+ err = vfs_truncate(&filp->f_path, size);
+ if (err)
+ pr_err("truncate failed for filename : %s err %d\n",
+ fp->filename, err);
return err;
}
/**
* ksmbd_vfs_kern_path() - lookup a file and get path info
- * @name: name of file for lookup
+ * @name: file path that is relative to share
* @flags: lookup flags
* @path: if lookup succeed, return path info
* @caseless: caseless filename lookup
*
* Return: 0 on success, otherwise error
*/
-int ksmbd_vfs_kern_path(char *name, unsigned int flags, struct path *path,
- bool caseless)
+int ksmbd_vfs_kern_path(struct ksmbd_work *work, char *name,
+ unsigned int flags, struct path *path, bool caseless)
{
+ struct ksmbd_share_config *share_conf = work->tcon->share_conf;
int err;
- if (name[0] != '/')
- return -EINVAL;
-
- err = kern_path(name, flags, path);
+ flags |= LOOKUP_BENEATH;
+ err = vfs_path_lookup(share_conf->vfs_path.dentry,
+ share_conf->vfs_path.mnt,
+ name,
+ flags,
+ path);
if (!err)
return 0;
return -ENOMEM;
path_len = strlen(filepath);
- remain_len = path_len - 1;
+ remain_len = path_len;
- err = kern_path("/", flags, &parent);
- if (err)
- goto out;
+ parent = share_conf->vfs_path;
+ path_get(&parent);
while (d_can_lookup(parent.dentry)) {
char *filename = filepath + path_len - remain_len;
err = ksmbd_vfs_lookup_in_dir(&parent, filename,
filename_len);
- if (err) {
- path_put(&parent);
+ path_put(&parent);
+ if (err)
goto out;
- }
- path_put(&parent);
next[0] = '\0';
- err = kern_path(filepath, flags, &parent);
+ err = vfs_path_lookup(share_conf->vfs_path.dentry,
+ share_conf->vfs_path.mnt,
+ filepath,
+ flags,
+ &parent);
if (err)
goto out;
-
- if (is_last) {
- path->mnt = parent.mnt;
- path->dentry = parent.dentry;
+ else if (is_last) {
+ *path = parent;
goto out;
}
return err;
}
+struct dentry *ksmbd_vfs_kern_path_create(struct ksmbd_work *work,
+ const char *name,
+ unsigned int flags,
+ struct path *path)
+{
+ char *abs_name;
+ struct dentry *dent;
+
+ abs_name = convert_to_unix_name(work->tcon->share_conf, name);
+ if (!abs_name)
+ return ERR_PTR(-ENOMEM);
+
+ dent = kern_path_create(AT_FDCWD, abs_name, path, flags);
+ kfree(abs_name);
+ return dent;
+}
+
int ksmbd_vfs_remove_acl_xattrs(struct user_namespace *user_ns,
struct dentry *dentry)
{
int ksmbd_vfs_getattr(struct path *path, struct kstat *stat);
int ksmbd_vfs_fp_rename(struct ksmbd_work *work, struct ksmbd_file *fp,
char *newname);
-int ksmbd_vfs_truncate(struct ksmbd_work *work, const char *name,
+int ksmbd_vfs_truncate(struct ksmbd_work *work,
struct ksmbd_file *fp, loff_t size);
struct srv_copychunk;
int ksmbd_vfs_copy_file_ranges(struct ksmbd_work *work,
size_t *xattr_stream_name_size, int s_type);
int ksmbd_vfs_remove_xattr(struct user_namespace *user_ns,
struct dentry *dentry, char *attr_name);
-int ksmbd_vfs_kern_path(char *name, unsigned int flags, struct path *path,
+int ksmbd_vfs_kern_path(struct ksmbd_work *work,
+ char *name, unsigned int flags, struct path *path,
bool caseless);
+struct dentry *ksmbd_vfs_kern_path_create(struct ksmbd_work *work,
+ const char *name,
+ unsigned int flags,
+ struct path *path);
int ksmbd_vfs_empty_dir(struct ksmbd_file *fp);
void ksmbd_vfs_set_fadvise(struct file *filp, __le32 option);
int ksmbd_vfs_zero_data(struct ksmbd_work *work, struct ksmbd_file *fp,
static inline bool
svcxdr_encode_owner(struct xdr_stream *xdr, const struct xdr_netobj *obj)
{
- unsigned int quadlen = XDR_QUADLEN(obj->len);
- __be32 *p;
-
- if (xdr_stream_encode_u32(xdr, obj->len) < 0)
- return false;
- p = xdr_reserve_space(xdr, obj->len);
- if (!p)
+ if (obj->len > XDR_MAX_NETOBJ)
return false;
- p[quadlen - 1] = 0; /* XDR pad */
- memcpy(p, obj->data, obj->len);
-
- return true;
+ return xdr_stream_encode_opaque(xdr, obj->data, obj->len) > 0;
}
#endif /* _LOCKD_SVCXDR_H_ */
}
static __be32 nfsd4_match_existing_connection(struct svc_rqst *rqst,
- struct nfsd4_session *session, u32 req)
+ struct nfsd4_session *session, u32 req, struct nfsd4_conn **conn)
{
struct nfs4_client *clp = session->se_client;
struct svc_xprt *xpt = rqst->rq_xprt;
else
status = nfserr_inval;
spin_unlock(&clp->cl_lock);
+ if (status == nfs_ok && conn)
+ *conn = c;
return status;
}
status = nfserr_wrong_cred;
if (!nfsd4_mach_creds_match(session->se_client, rqstp))
goto out;
- status = nfsd4_match_existing_connection(rqstp, session, bcts->dir);
- if (status == nfs_ok || status == nfserr_inval)
+ status = nfsd4_match_existing_connection(rqstp, session,
+ bcts->dir, &conn);
+ if (status == nfs_ok) {
+ if (bcts->dir == NFS4_CDFC4_FORE_OR_BOTH ||
+ bcts->dir == NFS4_CDFC4_BACK)
+ conn->cn_flags |= NFS4_CDFC4_BACK;
+ nfsd4_probe_callback(session->se_client);
+ goto out;
+ }
+ if (status == nfserr_inval)
goto out;
status = nfsd4_map_bcts_dir(&bcts->dir);
if (status)
oi = OCFS2_I(inode);
oi->ip_dir_lock_gen++;
mlog(0, "generation: %u\n", oi->ip_dir_lock_gen);
- goto out;
+ goto out_forget;
}
if (!S_ISREG(inode->i_mode))
filemap_fdatawait(mapping);
}
+out_forget:
forget_all_cached_acls(inode);
out:
#include <linux/buffer_head.h>
#include "qnx4.h"
+/*
+ * A qnx4 directory entry is an inode entry or link info
+ * depending on the status field in the last byte. The
+ * first byte is where the name start either way, and a
+ * zero means it's empty.
+ *
+ * Also, due to a bug in gcc, we don't want to use the
+ * real (differently sized) name arrays in the inode and
+ * link entries, but always the 'de_name[]' one in the
+ * fake struct entry.
+ *
+ * See
+ *
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578#c6
+ *
+ * for details, but basically gcc will take the size of the
+ * 'name' array from one of the used union entries randomly.
+ *
+ * This use of 'de_name[]' (48 bytes) avoids the false positive
+ * warnings that would happen if gcc decides to use 'inode.di_name'
+ * (16 bytes) even when the pointer and size were to come from
+ * 'link.dl_name' (48 bytes).
+ *
+ * In all cases the actual name pointer itself is the same, it's
+ * only the gcc internal 'what is the size of this field' logic
+ * that can get confused.
+ */
+union qnx4_directory_entry {
+ struct {
+ const char de_name[48];
+ u8 de_pad[15];
+ u8 de_status;
+ };
+ struct qnx4_inode_entry inode;
+ struct qnx4_link_info link;
+};
+
static int qnx4_readdir(struct file *file, struct dir_context *ctx)
{
struct inode *inode = file_inode(file);
unsigned int offset;
struct buffer_head *bh;
- struct qnx4_inode_entry *de;
- struct qnx4_link_info *le;
unsigned long blknum;
int ix, ino;
int size;
}
ix = (ctx->pos >> QNX4_DIR_ENTRY_SIZE_BITS) % QNX4_INODES_PER_BLOCK;
for (; ix < QNX4_INODES_PER_BLOCK; ix++, ctx->pos += QNX4_DIR_ENTRY_SIZE) {
+ union qnx4_directory_entry *de;
+
offset = ix * QNX4_DIR_ENTRY_SIZE;
- de = (struct qnx4_inode_entry *) (bh->b_data + offset);
- if (!de->di_fname[0])
+ de = (union qnx4_directory_entry *) (bh->b_data + offset);
+
+ if (!de->de_name[0])
continue;
- if (!(de->di_status & (QNX4_FILE_USED|QNX4_FILE_LINK)))
+ if (!(de->de_status & (QNX4_FILE_USED|QNX4_FILE_LINK)))
continue;
- if (!(de->di_status & QNX4_FILE_LINK))
- size = QNX4_SHORT_NAME_MAX;
- else
- size = QNX4_NAME_MAX;
- size = strnlen(de->di_fname, size);
- QNX4DEBUG((KERN_INFO "qnx4_readdir:%.*s\n", size, de->di_fname));
- if (!(de->di_status & QNX4_FILE_LINK))
+ if (!(de->de_status & QNX4_FILE_LINK)) {
+ size = sizeof(de->inode.di_fname);
ino = blknum * QNX4_INODES_PER_BLOCK + ix - 1;
- else {
- le = (struct qnx4_link_info*)de;
- ino = ( le32_to_cpu(le->dl_inode_blk) - 1 ) *
+ } else {
+ size = sizeof(de->link.dl_fname);
+ ino = ( le32_to_cpu(de->link.dl_inode_blk) - 1 ) *
QNX4_INODES_PER_BLOCK +
- le->dl_inode_ndx;
+ de->link.dl_inode_ndx;
}
- if (!dir_emit(ctx, de->di_fname, size, ino, DT_UNKNOWN)) {
+ size = strnlen(de->de_name, size);
+ QNX4DEBUG((KERN_INFO "qnx4_readdir:%.*s\n", size, name));
+ if (!dir_emit(ctx, de->de_name, size, ino, DT_UNKNOWN)) {
brelse(bh);
return 0;
}
/* SPDX-License-Identifier: LGPL-2.1+ */
/*
- * fs/cifs/smbfsctl.h: SMB, CIFS, SMB2 FSCTL definitions
+ * SMB, CIFS, SMB2 FSCTL definitions
*
* Copyright (c) International Business Machines Corp., 2002,2013
* Author(s): Steve French (sfrench@us.ibm.com)
}
#endif
-#ifndef acpi_os_memmap
-static inline void __iomem *acpi_os_memmap(acpi_physical_address phys,
- acpi_size size)
-{
- return ioremap_cache(phys, size);
-}
-#endif
-
extern bool acpi_permanent_mmap;
void __iomem __ref
port &= IO_SPACE_LIMIT;
return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
}
-#define __pci_ioport_unmap __pci_ioport_unmap
-static inline void __pci_ioport_unmap(void __iomem *p)
-{
- uintptr_t start = (uintptr_t) PCI_IOBASE;
- uintptr_t addr = (uintptr_t) p;
-
- if (addr >= start && addr < start + IO_SPACE_LIMIT)
- return;
- iounmap(p);
-}
+#define ARCH_HAS_GENERIC_IOPORT_MAP
#endif
#ifndef ioport_unmap
#endif /* CONFIG_HAS_IOPORT_MAP */
#ifndef CONFIG_GENERIC_IOMAP
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-
-#ifndef __pci_ioport_unmap
-static inline void __pci_ioport_unmap(void __iomem *p) {}
-#endif
-
#ifndef pci_iounmap
-#define pci_iounmap pci_iounmap
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
-{
- __pci_ioport_unmap(p);
-}
+#define ARCH_WANTS_GENERIC_PCI_IOUNMAP
+#endif
#endif
-#endif /* CONFIG_GENERIC_IOMAP */
#ifndef xlate_dev_mem_ptr
#define xlate_dev_mem_ptr xlate_dev_mem_ptr
}
#endif
-#ifdef CONFIG_PCI
-/* Destroy a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-#elif defined(CONFIG_GENERIC_IOMAP)
-struct pci_dev;
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
-{ }
-#endif
-
#include <asm-generic/pci_iomap.h>
#endif
return hv_vp_index[cpu_number];
}
-static inline int cpumask_to_vpset(struct hv_vpset *vpset,
- const struct cpumask *cpus)
+static inline int __cpumask_to_vpset(struct hv_vpset *vpset,
+ const struct cpumask *cpus,
+ bool exclude_self)
{
int cpu, vcpu, vcpu_bank, vcpu_offset, nr_bank = 1;
+ int this_cpu = smp_processor_id();
/* valid_bank_mask can represent up to 64 banks */
if (hv_max_vp_index / 64 >= 64)
* Some banks may end up being empty but this is acceptable.
*/
for_each_cpu(cpu, cpus) {
+ if (exclude_self && cpu == this_cpu)
+ continue;
vcpu = hv_cpu_number_to_vp_number(cpu);
if (vcpu == VP_INVAL)
return -1;
return nr_bank;
}
+static inline int cpumask_to_vpset(struct hv_vpset *vpset,
+ const struct cpumask *cpus)
+{
+ return __cpumask_to_vpset(vpset, cpus, false);
+}
+
+static inline int cpumask_to_vpset_noself(struct hv_vpset *vpset,
+ const struct cpumask *cpus)
+{
+ WARN_ON_ONCE(preemptible());
+ return __cpumask_to_vpset(vpset, cpus, true);
+}
+
void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die);
bool hv_is_hyperv_initialized(void);
bool hv_is_hibernation_supported(void);
extern void __iomem *pci_iomap_wc_range(struct pci_dev *dev, int bar,
unsigned long offset,
unsigned long maxlen);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
/* Create a virtual mapping cookie for a port on a given PCI device.
* Do not call this directly, it exists to make it easier for architectures
* to override */
{
return NULL;
}
+static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{ }
#endif
#endif /* __ASM_GENERIC_PCI_IOMAP_H */
* GCC 4.5 and later have a 32 bytes section alignment for structures.
* Except GCC 4.9, that feels the need to align on 64 bytes.
*/
-#if __GNUC__ == 4 && __GNUC_MINOR__ == 9
-#define STRUCT_ALIGNMENT 64
-#else
#define STRUCT_ALIGNMENT 32
-#endif
#define STRUCT_ALIGN() . = ALIGN(STRUCT_ALIGNMENT)
/*
#define MT8173_INFRA_GCE_FAXI_RST 40
#define MT8173_INFRA_MMIOMMURST 47
+/* MMSYS resets */
+#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25
/* PERICFG resets */
#define MT8173_PERI_UART0_SW_RST 0
#define MT8183_INFRACFG_SW_RST_NUM 128
+/* MMSYS resets */
+#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25
+
#define MT8183_TOPRGU_MM_SW_RST 1
#define MT8183_TOPRGU_MFG_SW_RST 2
#define MT8183_TOPRGU_VENC_SW_RST 3
struct buffer_head *__bread_gfp(struct block_device *,
sector_t block, unsigned size, gfp_t gfp);
void invalidate_bh_lrus(void);
-void invalidate_bh_lrus_cpu(int cpu);
+void invalidate_bh_lrus_cpu(void);
bool has_bh_in_lru(int cpu, void *dummy);
struct buffer_head *alloc_buffer_head(gfp_t gfp_flags);
void free_buffer_head(struct buffer_head * bh);
static inline void invalidate_inode_buffers(struct inode *inode) {}
static inline int remove_inode_buffers(struct inode *inode) { return 1; }
static inline int sync_mapping_buffers(struct address_space *mapping) { return 0; }
-static inline void invalidate_bh_lrus_cpu(int cpu) {}
+static inline void invalidate_bh_lrus_cpu(void) {}
static inline bool has_bh_in_lru(int cpu, void *dummy) { return false; }
#define buffer_heads_over_limit 0
* sock_cgroup_data is embedded at sock->sk_cgrp_data and contains
* per-socket cgroup information except for memcg association.
*
- * On legacy hierarchies, net_prio and net_cls controllers directly set
- * attributes on each sock which can then be tested by the network layer.
- * On the default hierarchy, each sock is associated with the cgroup it was
- * created in and the networking layer can match the cgroup directly.
- *
- * To avoid carrying all three cgroup related fields separately in sock,
- * sock_cgroup_data overloads (prioidx, classid) and the cgroup pointer.
- * On boot, sock_cgroup_data records the cgroup that the sock was created
- * in so that cgroup2 matches can be made; however, once either net_prio or
- * net_cls starts being used, the area is overridden to carry prioidx and/or
- * classid. The two modes are distinguished by whether the lowest bit is
- * set. Clear bit indicates cgroup pointer while set bit prioidx and
- * classid.
- *
- * While userland may start using net_prio or net_cls at any time, once
- * either is used, cgroup2 matching no longer works. There is no reason to
- * mix the two and this is in line with how legacy and v2 compatibility is
- * handled. On mode switch, cgroup references which are already being
- * pointed to by socks may be leaked. While this can be remedied by adding
- * synchronization around sock_cgroup_data, given that the number of leaked
- * cgroups is bound and highly unlikely to be high, this seems to be the
- * better trade-off.
+ * On legacy hierarchies, net_prio and net_cls controllers directly
+ * set attributes on each sock which can then be tested by the network
+ * layer. On the default hierarchy, each sock is associated with the
+ * cgroup it was created in and the networking layer can match the
+ * cgroup directly.
*/
struct sock_cgroup_data {
- union {
-#ifdef __LITTLE_ENDIAN
- struct {
- u8 is_data : 1;
- u8 no_refcnt : 1;
- u8 unused : 6;
- u8 padding;
- u16 prioidx;
- u32 classid;
- } __packed;
-#else
- struct {
- u32 classid;
- u16 prioidx;
- u8 padding;
- u8 unused : 6;
- u8 no_refcnt : 1;
- u8 is_data : 1;
- } __packed;
+ struct cgroup *cgroup; /* v2 */
+#ifdef CONFIG_CGROUP_NET_CLASSID
+ u32 classid; /* v1 */
+#endif
+#ifdef CONFIG_CGROUP_NET_PRIO
+ u16 prioidx; /* v1 */
#endif
- u64 val;
- };
};
-/*
- * There's a theoretical window where the following accessors race with
- * updaters and return part of the previous pointer as the prioidx or
- * classid. Such races are short-lived and the result isn't critical.
- */
static inline u16 sock_cgroup_prioidx(const struct sock_cgroup_data *skcd)
{
- /* fallback to 1 which is always the ID of the root cgroup */
- return (skcd->is_data & 1) ? skcd->prioidx : 1;
+#ifdef CONFIG_CGROUP_NET_PRIO
+ return READ_ONCE(skcd->prioidx);
+#else
+ return 1;
+#endif
}
static inline u32 sock_cgroup_classid(const struct sock_cgroup_data *skcd)
{
- /* fallback to 0 which is the unconfigured default classid */
- return (skcd->is_data & 1) ? skcd->classid : 0;
+#ifdef CONFIG_CGROUP_NET_CLASSID
+ return READ_ONCE(skcd->classid);
+#else
+ return 0;
+#endif
}
-/*
- * If invoked concurrently, the updaters may clobber each other. The
- * caller is responsible for synchronization.
- */
static inline void sock_cgroup_set_prioidx(struct sock_cgroup_data *skcd,
u16 prioidx)
{
- struct sock_cgroup_data skcd_buf = {{ .val = READ_ONCE(skcd->val) }};
-
- if (sock_cgroup_prioidx(&skcd_buf) == prioidx)
- return;
-
- if (!(skcd_buf.is_data & 1)) {
- skcd_buf.val = 0;
- skcd_buf.is_data = 1;
- }
-
- skcd_buf.prioidx = prioidx;
- WRITE_ONCE(skcd->val, skcd_buf.val); /* see sock_cgroup_ptr() */
+#ifdef CONFIG_CGROUP_NET_PRIO
+ WRITE_ONCE(skcd->prioidx, prioidx);
+#endif
}
static inline void sock_cgroup_set_classid(struct sock_cgroup_data *skcd,
u32 classid)
{
- struct sock_cgroup_data skcd_buf = {{ .val = READ_ONCE(skcd->val) }};
-
- if (sock_cgroup_classid(&skcd_buf) == classid)
- return;
-
- if (!(skcd_buf.is_data & 1)) {
- skcd_buf.val = 0;
- skcd_buf.is_data = 1;
- }
-
- skcd_buf.classid = classid;
- WRITE_ONCE(skcd->val, skcd_buf.val); /* see sock_cgroup_ptr() */
+#ifdef CONFIG_CGROUP_NET_CLASSID
+ WRITE_ONCE(skcd->classid, classid);
+#endif
}
#else /* CONFIG_SOCK_CGROUP_DATA */
*/
#ifdef CONFIG_SOCK_CGROUP_DATA
-#if defined(CONFIG_CGROUP_NET_PRIO) || defined(CONFIG_CGROUP_NET_CLASSID)
-extern spinlock_t cgroup_sk_update_lock;
-#endif
-
-void cgroup_sk_alloc_disable(void);
void cgroup_sk_alloc(struct sock_cgroup_data *skcd);
void cgroup_sk_clone(struct sock_cgroup_data *skcd);
void cgroup_sk_free(struct sock_cgroup_data *skcd);
static inline struct cgroup *sock_cgroup_ptr(struct sock_cgroup_data *skcd)
{
-#if defined(CONFIG_CGROUP_NET_PRIO) || defined(CONFIG_CGROUP_NET_CLASSID)
- unsigned long v;
-
- /*
- * @skcd->val is 64bit but the following is safe on 32bit too as we
- * just need the lower ulong to be written and read atomically.
- */
- v = READ_ONCE(skcd->val);
-
- if (v & 3)
- return &cgrp_dfl_root.cgrp;
-
- return (struct cgroup *)(unsigned long)v ?: &cgrp_dfl_root.cgrp;
-#else
- return (struct cgroup *)(unsigned long)skcd->val;
-#endif
+ return skcd->cgroup;
}
#else /* CONFIG_CGROUP_DATA */
#define __no_sanitize_coverage
#endif
-/*
- * Not all versions of clang implement the type-generic versions
- * of the builtin overflow checkers. Fortunately, clang implements
- * __has_builtin allowing us to avoid awkward version
- * checks. Unfortunately, we don't know which version of gcc clang
- * pretends to be, so the macro may or may not be defined.
- */
-#if __has_builtin(__builtin_mul_overflow) && \
- __has_builtin(__builtin_add_overflow) && \
- __has_builtin(__builtin_sub_overflow)
-#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
-#endif
-
#if __has_feature(shadow_call_stack)
# define __noscs __attribute__((__no_sanitize__("shadow-call-stack")))
#endif
#if GCC_VERSION >= 70000
#define KASAN_ABI_VERSION 5
-#elif GCC_VERSION >= 50000
+#else
#define KASAN_ABI_VERSION 4
-#elif GCC_VERSION >= 40902
-#define KASAN_ABI_VERSION 3
#endif
#if __has_attribute(__no_sanitize_address__)
#define __no_sanitize_coverage
#endif
-#if GCC_VERSION >= 50100
-#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
-#endif
-
/*
* Turn individual warnings and errors on and off locally, depending
* on version.
(typeof(ptr)) (__ptr + (off)); })
#endif
+#define absolute_pointer(val) RELOC_HIDE((void *)(val), 0)
+
#ifndef OPTIMIZER_HIDE_VAR
/* Make the optimizer believe the variable can be manipulated arbitrarily. */
#define OPTIMIZER_HIDE_VAR(var) \
*/
/*
- * __has_attribute is supported on gcc >= 5, clang >= 2.9 and icc >= 17.
- * In the meantime, to support gcc < 5, we implement __has_attribute
- * by hand.
- */
-#ifndef __has_attribute
-# define __has_attribute(x) __GCC4_has_attribute_##x
-# define __GCC4_has_attribute___assume_aligned__ 1
-# define __GCC4_has_attribute___copy__ 0
-# define __GCC4_has_attribute___designated_init__ 0
-# define __GCC4_has_attribute___error__ 1
-# define __GCC4_has_attribute___externally_visible__ 1
-# define __GCC4_has_attribute___no_caller_saved_registers__ 0
-# define __GCC4_has_attribute___noclone__ 1
-# define __GCC4_has_attribute___no_profile_instrument_function__ 0
-# define __GCC4_has_attribute___nonstring__ 0
-# define __GCC4_has_attribute___no_sanitize_address__ 1
-# define __GCC4_has_attribute___no_sanitize_undefined__ 1
-# define __GCC4_has_attribute___no_sanitize_coverage__ 0
-# define __GCC4_has_attribute___fallthrough__ 0
-# define __GCC4_has_attribute___warning__ 1
-#endif
-
-/*
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-alias-function-attribute
*/
#define __alias(symbol) __attribute__((__alias__(#symbol)))
* compiler should see some alignment anyway, when the return value is
* massaged by 'flags = ptr & 3; ptr &= ~3;').
*
- * Optional: only supported since gcc >= 4.9
* Optional: not supported by icc
*
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-assume_005faligned-function-attribute
/* SPDX-License-Identifier: GPL-2.0
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
#ifndef _NET_DSA_TAG_OCELOT_H
}
void irq_domain_free_fwnode(struct fwnode_handle *fwnode);
-struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, int size,
+struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, unsigned int size,
irq_hw_number_t hwirq_max, int direct_max,
const struct irq_domain_ops *ops,
void *host_data);
/* Clears up any memory if needed */
void (*remove)(struct mdio_device *mdiodev);
+
+ /* Quiesces the device on system shutdown, turns off interrupts etc */
+ void (*shutdown)(struct mdio_device *mdiodev);
};
static inline struct mdio_driver *
int memblock_clear_nomap(phys_addr_t base, phys_addr_t size);
void memblock_free_all(void);
+void memblock_free_ptr(void *ptr, size_t size);
void reset_node_managed_pages(pg_data_t *pgdat);
void reset_all_zones_managed_pages(void);
*/
#define MIGRATEPAGE_SUCCESS 0
+/*
+ * Keep sync with:
+ * - macro MIGRATE_REASON in include/trace/events/migrate.h
+ * - migrate_reason_names[MR_TYPES] in mm/debug.c
+ */
enum migrate_reason {
MR_COMPACTION,
MR_MEMORY_FAILURE,
MR_TYPES
};
-/* In mm/debug.c; also keep sync with include/trace/events/migrate.h */
extern const char *migrate_reason_names[MR_TYPES];
#ifdef CONFIG_MIGRATION
up_read(&mm->mmap_lock);
}
-static inline bool mmap_read_trylock_non_owner(struct mm_struct *mm)
-{
- if (mmap_read_trylock(mm)) {
- rwsem_release(&mm->mmap_lock.dep_map, _RET_IP_);
- return true;
- }
- return false;
-}
-
static inline void mmap_read_unlock_non_owner(struct mm_struct *mm)
{
__mmap_lock_trace_released(mm, false);
return -EOPNOTSUPP;
}
+static inline int nvmem_cell_read_variable_le_u32(struct device *dev,
+ const char *cell_id,
+ u32 *val)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int nvmem_cell_read_variable_le_u64(struct device *dev,
+ const char *cell_id,
+ u64 *val)
+{
+ return -EOPNOTSUPP;
+}
+
static inline struct nvmem_device *nvmem_device_get(struct device *dev,
const char *name)
{
#include <linux/limits.h>
/*
- * In the fallback code below, we need to compute the minimum and
- * maximum values representable in a given type. These macros may also
- * be useful elsewhere, so we provide them outside the
- * COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW block.
- *
- * It would seem more obvious to do something like
+ * We need to compute the minimum and maximum values representable in a given
+ * type. These macros may also be useful elsewhere. It would seem more obvious
+ * to do something like:
*
* #define type_min(T) (T)(is_signed_type(T) ? (T)1 << (8*sizeof(T)-1) : 0)
* #define type_max(T) (T)(is_signed_type(T) ? ((T)1 << (8*sizeof(T)-1)) - 1 : ~(T)0)
return unlikely(overflow);
}
-#ifdef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
/*
* For simplicity and code hygiene, the fallback code below insists on
* a, b and *d having the same type (similar to the min() and max()
__builtin_mul_overflow(__a, __b, __d); \
}))
-#else
-
-
-/* Checking for unsigned overflow is relatively easy without causing UB. */
-#define __unsigned_add_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = __a + __b; \
- *__d < __a; \
-})
-#define __unsigned_sub_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = __a - __b; \
- __a < __b; \
-})
-/*
- * If one of a or b is a compile-time constant, this avoids a division.
- */
-#define __unsigned_mul_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = __a * __b; \
- __builtin_constant_p(__b) ? \
- __b > 0 && __a > type_max(typeof(__a)) / __b : \
- __a > 0 && __b > type_max(typeof(__b)) / __a; \
-})
-
-/*
- * For signed types, detecting overflow is much harder, especially if
- * we want to avoid UB. But the interface of these macros is such that
- * we must provide a result in *d, and in fact we must produce the
- * result promised by gcc's builtins, which is simply the possibly
- * wrapped-around value. Fortunately, we can just formally do the
- * operations in the widest relevant unsigned type (u64) and then
- * truncate the result - gcc is smart enough to generate the same code
- * with and without the (u64) casts.
- */
-
-/*
- * Adding two signed integers can overflow only if they have the same
- * sign, and overflow has happened iff the result has the opposite
- * sign.
- */
-#define __signed_add_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = (u64)__a + (u64)__b; \
- (((~(__a ^ __b)) & (*__d ^ __a)) \
- & type_min(typeof(__a))) != 0; \
-})
-
-/*
- * Subtraction is similar, except that overflow can now happen only
- * when the signs are opposite. In this case, overflow has happened if
- * the result has the opposite sign of a.
- */
-#define __signed_sub_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = (u64)__a - (u64)__b; \
- ((((__a ^ __b)) & (*__d ^ __a)) \
- & type_min(typeof(__a))) != 0; \
-})
-
-/*
- * Signed multiplication is rather hard. gcc always follows C99, so
- * division is truncated towards 0. This means that we can write the
- * overflow check like this:
- *
- * (a > 0 && (b > MAX/a || b < MIN/a)) ||
- * (a < -1 && (b > MIN/a || b < MAX/a) ||
- * (a == -1 && b == MIN)
- *
- * The redundant casts of -1 are to silence an annoying -Wtype-limits
- * (included in -Wextra) warning: When the type is u8 or u16, the
- * __b_c_e in check_mul_overflow obviously selects
- * __unsigned_mul_overflow, but unfortunately gcc still parses this
- * code and warns about the limited range of __b.
- */
-
-#define __signed_mul_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- typeof(a) __tmax = type_max(typeof(a)); \
- typeof(a) __tmin = type_min(typeof(a)); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = (u64)__a * (u64)__b; \
- (__b > 0 && (__a > __tmax/__b || __a < __tmin/__b)) || \
- (__b < (typeof(__b))-1 && (__a > __tmin/__b || __a < __tmax/__b)) || \
- (__b == (typeof(__b))-1 && __a == __tmin); \
-})
-
-
-#define check_add_overflow(a, b, d) __must_check_overflow( \
- __builtin_choose_expr(is_signed_type(typeof(a)), \
- __signed_add_overflow(a, b, d), \
- __unsigned_add_overflow(a, b, d)))
-
-#define check_sub_overflow(a, b, d) __must_check_overflow( \
- __builtin_choose_expr(is_signed_type(typeof(a)), \
- __signed_sub_overflow(a, b, d), \
- __unsigned_sub_overflow(a, b, d)))
-
-#define check_mul_overflow(a, b, d) __must_check_overflow( \
- __builtin_choose_expr(is_signed_type(typeof(a)), \
- __signed_mul_overflow(a, b, d), \
- __unsigned_mul_overflow(a, b, d)))
-
-#endif /* COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW */
-
/** check_shl_overflow() - Calculate a left-shifted value and check overflow
*
* @a: Value to be shifted
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2016-2018, NXP Semiconductors
+ * Copyright 2016-2018 NXP
* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
*/
#ifndef _LINUX_PACKING_H
#include <linux/mm.h>
+#define ARCH_DEFAULT_PKEY 0
+
#ifdef CONFIG_ARCH_HAS_PKEYS
#include <asm/pkeys.h>
#else /* ! CONFIG_ARCH_HAS_PKEYS */
mce_whole_page : 1,
__mce_reserved : 62;
struct callback_head mce_kill_me;
+ int mce_count;
#endif
#ifdef CONFIG_KRETPROBES
WRITE_ONCE(newsk->prev, prev);
WRITE_ONCE(next->prev, newsk);
WRITE_ONCE(prev->next, newsk);
- list->qlen++;
+ WRITE_ONCE(list->qlen, list->qlen + 1);
}
static inline void __skb_queue_splice(const struct sk_buff_head *list,
mem_cgroup_handle_over_high();
blkcg_maybe_throttle_current();
+
+ rseq_handle_notify_resume(NULL, regs);
}
/*
ITER_DISCARD,
};
+struct iov_iter_state {
+ size_t iov_offset;
+ size_t count;
+ unsigned long nr_segs;
+};
+
struct iov_iter {
u8 iter_type;
bool data_source;
};
loff_t xarray_start;
};
- size_t truncated;
};
static inline enum iter_type iov_iter_type(const struct iov_iter *i)
return i->iter_type;
}
+static inline void iov_iter_save_state(struct iov_iter *iter,
+ struct iov_iter_state *state)
+{
+ state->iov_offset = iter->iov_offset;
+ state->count = iter->count;
+ state->nr_segs = iter->nr_segs;
+}
+
static inline bool iter_is_iovec(const struct iov_iter *i)
{
return iov_iter_type(i) == ITER_IOVEC;
ssize_t iov_iter_get_pages_alloc(struct iov_iter *i, struct page ***pages,
size_t maxsize, size_t *start);
int iov_iter_npages(const struct iov_iter *i, int maxpages);
+void iov_iter_restore(struct iov_iter *i, struct iov_iter_state *state);
const void *dup_iter(struct iov_iter *new, struct iov_iter *old, gfp_t flags);
* conversion in assignement is by definition greater than all
* values of size_t, including old i->count.
*/
- if (i->count > count) {
- i->truncated += i->count - count;
+ if (i->count > count)
i->count = count;
- }
}
/*
*/
static inline void iov_iter_reexpand(struct iov_iter *i, size_t count)
{
- i->truncated -= count - i->count;
i->count = count;
}
#define HCD_FLAG_RH_RUNNING 5 /* root hub is running? */
#define HCD_FLAG_DEAD 6 /* controller has died? */
#define HCD_FLAG_INTF_AUTHORIZED 7 /* authorize interfaces? */
+#define HCD_FLAG_DEFER_RH_REGISTER 8 /* Defer roothub registration */
/* The flags can be tested using these macros; they are likely to
* be slightly faster than test_bit().
#define HCD_WAKEUP_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_WAKEUP_PENDING))
#define HCD_RH_RUNNING(hcd) ((hcd)->flags & (1U << HCD_FLAG_RH_RUNNING))
#define HCD_DEAD(hcd) ((hcd)->flags & (1U << HCD_FLAG_DEAD))
+#define HCD_DEFER_RH_REGISTER(hcd) ((hcd)->flags & (1U << HCD_FLAG_DEFER_RH_REGISTER))
/*
* Specifies if interfaces are authorized by default
return dp->type == DSA_PORT_TYPE_USER;
}
+static inline bool dsa_port_is_unused(struct dsa_port *dp)
+{
+ return dp->type == DSA_PORT_TYPE_UNUSED;
+}
+
static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p)
{
return dsa_to_port(ds, p)->type == DSA_PORT_TYPE_UNUSED;
int (*change_tag_protocol)(struct dsa_switch *ds, int port,
enum dsa_tag_protocol proto);
+ /* Optional switch-wide initialization and destruction methods */
int (*setup)(struct dsa_switch *ds);
void (*teardown)(struct dsa_switch *ds);
+
+ /* Per-port initialization and destruction methods. Mandatory if the
+ * driver registers devlink port regions, optional otherwise.
+ */
+ int (*port_setup)(struct dsa_switch *ds, int port);
+ void (*port_teardown)(struct dsa_switch *ds, int port);
+
u32 (*get_phy_flags)(struct dsa_switch *ds, int port);
/*
void dsa_unregister_switch(struct dsa_switch *ds);
int dsa_register_switch(struct dsa_switch *ds);
+void dsa_switch_shutdown(struct dsa_switch *ds);
struct dsa_switch *dsa_switch_find(int tree_index, int sw_index);
#ifdef CONFIG_PM_SLEEP
int dsa_switch_suspend(struct dsa_switch *ds);
release_sock(sk);
__release(&sk->sk_lock.slock);
} else {
+ mutex_release(&sk->sk_lock.dep_map, _RET_IP_);
spin_unlock_bh(&sk->sk_lock.slock);
}
}
struct scsi_vpd __rcu *vpd_pg83;
struct scsi_vpd __rcu *vpd_pg80;
struct scsi_vpd __rcu *vpd_pg89;
- unsigned char current_tag; /* current tag */
struct scsi_target *sdev_target;
blist_flags_t sdev_bflags; /* black/white flags as also found in
enum afs_cb_break_reason {
afs_cb_break_no_break,
+ afs_cb_break_no_promise,
afs_cb_break_for_callback,
afs_cb_break_for_deleted,
afs_cb_break_for_lapsed,
+ afs_cb_break_for_s_reinit,
afs_cb_break_for_unlink,
- afs_cb_break_for_vsbreak,
+ afs_cb_break_for_v_break,
afs_cb_break_for_volume_callback,
afs_cb_break_for_zap,
};
#define afs_cb_break_reasons \
EM(afs_cb_break_no_break, "no-break") \
+ EM(afs_cb_break_no_promise, "no-promise") \
EM(afs_cb_break_for_callback, "break-cb") \
EM(afs_cb_break_for_deleted, "break-del") \
EM(afs_cb_break_for_lapsed, "break-lapsed") \
+ EM(afs_cb_break_for_s_reinit, "s-reinit") \
EM(afs_cb_break_for_unlink, "break-unlink") \
- EM(afs_cb_break_for_vsbreak, "break-vs") \
+ EM(afs_cb_break_for_v_break, "break-v") \
EM(afs_cb_break_for_volume_callback, "break-v-cb") \
E_(afs_cb_break_for_zap, "break-zap")
TP_STRUCT__entry(
__field(dev_t, dev )
__field(erofs_nid_t, nid )
- __field(const char *, name )
+ __string(name, dentry->d_name.name )
__field(unsigned int, flags )
),
TP_fast_assign(
__entry->dev = dir->i_sb->s_dev;
__entry->nid = EROFS_I(dir)->nid;
- __entry->name = dentry->d_name.name;
+ __assign_str(name, dentry->d_name.name);
__entry->flags = flags;
),
TP_printk("dev = (%d,%d), pnid = %llu, name:%s, flags:%x",
show_dev_nid(__entry),
- __entry->name,
+ __get_str(name),
__entry->flags)
);
struct binder_frozen_status_info {
__u32 pid;
+
+ /* process received sync transactions since last frozen
+ * bit 0: received sync transaction after being frozen
+ * bit 1: new pending sync transaction during freezing
+ */
__u32 sync_recv;
+
+ /* process received async transactions since last frozen */
__u32 async_recv;
};
/* SPDX-License-Identifier: LGPL-2.1+ WITH Linux-syscall-note */
/*
- * include/uapi/linux/cifs/cifs_mount.h
*
* Author(s): Scott Lovenberg (scott.lovenberg@gmail.com)
*
IORING_REGISTER_IOWQ_AFF = 17,
IORING_UNREGISTER_IOWQ_AFF = 18,
- /* set/get max number of workers */
+ /* set/get max number of io-wq workers */
IORING_REGISTER_IOWQ_MAX_WORKERS = 19,
/* this goes last */
IORING_REGISTER_LAST
};
+/* io-wq worker categories */
+enum {
+ IO_WQ_BOUND,
+ IO_WQ_UNBOUND,
+};
+
/* deprecated, see struct io_uring_rsrc_update */
struct io_uring_files_update {
__u32 offset;
int xen_create_contiguous_region(phys_addr_t pstart, unsigned int order,
unsigned int address_bits,
dma_addr_t *dma_handle);
-
void xen_destroy_contiguous_region(phys_addr_t pstart, unsigned int order);
-#else
-static inline int xen_create_contiguous_region(phys_addr_t pstart,
- unsigned int order,
- unsigned int address_bits,
- dma_addr_t *dma_handle)
-{
- return 0;
-}
-
-static inline void xen_destroy_contiguous_region(phys_addr_t pstart,
- unsigned int order) { }
#endif
#if defined(CONFIG_XEN_PV)
__setup("rootfstype=", fs_names_setup);
__setup("rootdelay=", root_delay_setup);
-static int __init split_fs_names(char *page, char *names)
+/* This can return zero length strings. Caller should check */
+static int __init split_fs_names(char *page, size_t size, char *names)
{
- int count = 0;
+ int count = 1;
char *p = page;
- strcpy(p, root_fs_names);
+ strlcpy(p, root_fs_names, size);
while (*p++) {
- if (p[-1] == ',')
+ if (p[-1] == ',') {
p[-1] = '\0';
+ count++;
+ }
}
- *p = '\0';
-
- for (p = page; *p; p += strlen(p)+1)
- count++;
return count;
}
scnprintf(b, BDEVNAME_SIZE, "unknown-block(%u,%u)",
MAJOR(ROOT_DEV), MINOR(ROOT_DEV));
if (root_fs_names)
- num_fs = split_fs_names(fs_names, root_fs_names);
+ num_fs = split_fs_names(fs_names, PAGE_SIZE, root_fs_names);
else
num_fs = list_bdev_fs_names(fs_names, PAGE_SIZE);
retry:
for (i = 0, p = fs_names; i < num_fs; i++, p += strlen(p)+1) {
- int err = do_mount_root(name, p, flags, root_mount_data);
+ int err;
+
+ if (!*p)
+ continue;
+ err = do_mount_root(name, p, flags, root_mount_data);
switch (err) {
case 0:
goto out;
fs_names = (void *)__get_free_page(GFP_KERNEL);
if (!fs_names)
return -EINVAL;
- num_fs = split_fs_names(fs_names, root_fs_names);
+ num_fs = split_fs_names(fs_names, PAGE_SIZE, root_fs_names);
for (i = 0, fstype = fs_names; i < num_fs;
i++, fstype += strlen(fstype) + 1) {
+ if (!*fstype)
+ continue;
if (!fs_is_nodev(fstype))
continue;
err = do_mount_root(root_device_name, fstype, root_mountflags,
root_mount_data);
if (!err)
break;
- if (err != -EACCES && err != -EINVAL)
- panic("VFS: Unable to mount root \"%s\" (%s), err=%d\n",
- root_device_name, fstype, err);
}
free_page((unsigned long)fs_names);
end += sprintf(end, " %s", *p);
pr_notice("Unknown command line parameters:%s\n", unknown_options);
- memblock_free(__pa(unknown_options), len);
+ memblock_free_ptr(unknown_options, len);
}
asmlinkage __visible void __init __no_sanitize_address start_kernel(void)
{
ktime_t *calltime = (ktime_t *)data;
- printk(KERN_DEBUG "calling %pS @ %i irqs_disabled() %d\n", fn, task_pid_nr(current), irqs_disabled());
+ printk(KERN_DEBUG "calling %pS @ %i\n", fn, task_pid_nr(current));
*calltime = ktime_get();
}
rettime = ktime_get();
delta = ktime_sub(rettime, *calltime);
duration = (unsigned long long) ktime_to_ns(delta) >> 10;
- printk(KERN_DEBUG "initcall %pS returned %d after %lld usecs, irqs_disabled() %d\n",
- fn, ret, duration, irqs_disabled());
+ printk(KERN_DEBUG "initcall %pS returned %d after %lld usecs\n",
+ fn, ret, duration);
}
static ktime_t initcall_calltime;
return -EINVAL;
if (nsops > SEMOPM_FAST) {
- sops = kvmalloc_array(nsops, sizeof(*sops), GFP_KERNEL_ACCOUNT);
+ sops = kvmalloc_array(nsops, sizeof(*sops), GFP_KERNEL);
if (sops == NULL)
return -ENOMEM;
}
-// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/* Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
* Copyright (c) 2016 Facebook
*/
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/* Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
* Copyright (c) 2016 Facebook
*/
* with build_id.
*/
if (!user || !current || !current->mm || irq_work_busy ||
- !mmap_read_trylock_non_owner(current->mm)) {
+ !mmap_read_trylock(current->mm)) {
/* cannot access current->mm, fall back to ips */
for (i = 0; i < trace_nr; i++) {
id_offs[i].status = BPF_STACK_BUILD_ID_IP;
}
if (!work) {
- mmap_read_unlock_non_owner(current->mm);
+ mmap_read_unlock(current->mm);
} else {
work->mm = current->mm;
+
+ /* The lock will be released once we're out of interrupt
+ * context. Tell lockdep that we've released it now so
+ * it doesn't complain that we forgot to release it.
+ */
+ rwsem_release(¤t->mm->mmap_lock.dep_map, _RET_IP_);
irq_work_queue(&work->irq_work);
}
}
nr_linfo = attr->line_info_cnt;
if (!nr_linfo)
return 0;
+ if (nr_linfo > INT_MAX / sizeof(struct bpf_line_info))
+ return -EINVAL;
rec_size = attr->line_info_rec_size;
if (rec_size < MIN_BPF_LINEINFO_SIZE ||
*/
#ifdef CONFIG_SOCK_CGROUP_DATA
-#if defined(CONFIG_CGROUP_NET_PRIO) || defined(CONFIG_CGROUP_NET_CLASSID)
-
-DEFINE_SPINLOCK(cgroup_sk_update_lock);
-static bool cgroup_sk_alloc_disabled __read_mostly;
-
-void cgroup_sk_alloc_disable(void)
-{
- if (cgroup_sk_alloc_disabled)
- return;
- pr_info("cgroup: disabling cgroup2 socket matching due to net_prio or net_cls activation\n");
- cgroup_sk_alloc_disabled = true;
-}
-
-#else
-
-#define cgroup_sk_alloc_disabled false
-
-#endif
-
void cgroup_sk_alloc(struct sock_cgroup_data *skcd)
{
- if (cgroup_sk_alloc_disabled) {
- skcd->no_refcnt = 1;
- return;
- }
-
/* Don't associate the sock with unrelated interrupted task's cgroup. */
if (in_interrupt())
return;
rcu_read_lock();
-
while (true) {
struct css_set *cset;
cset = task_css_set(current);
if (likely(cgroup_tryget(cset->dfl_cgrp))) {
- skcd->val = (unsigned long)cset->dfl_cgrp;
+ skcd->cgroup = cset->dfl_cgrp;
cgroup_bpf_get(cset->dfl_cgrp);
break;
}
cpu_relax();
}
-
rcu_read_unlock();
}
void cgroup_sk_clone(struct sock_cgroup_data *skcd)
{
- if (skcd->val) {
- if (skcd->no_refcnt)
- return;
- /*
- * We might be cloning a socket which is left in an empty
- * cgroup and the cgroup might have already been rmdir'd.
- * Don't use cgroup_get_live().
- */
- cgroup_get(sock_cgroup_ptr(skcd));
- cgroup_bpf_get(sock_cgroup_ptr(skcd));
- }
+ struct cgroup *cgrp = sock_cgroup_ptr(skcd);
+
+ /*
+ * We might be cloning a socket which is left in an empty
+ * cgroup and the cgroup might have already been rmdir'd.
+ * Don't use cgroup_get_live().
+ */
+ cgroup_get(cgrp);
+ cgroup_bpf_get(cgrp);
}
void cgroup_sk_free(struct sock_cgroup_data *skcd)
{
struct cgroup *cgrp = sock_cgroup_ptr(skcd);
- if (skcd->no_refcnt)
- return;
cgroup_bpf_put(cgrp);
cgroup_put(cgrp);
}
pr_err("cacheline tracking ENOMEM, dma-debug disabled\n");
global_disable = true;
} else if (rc == -EEXIST) {
- pr_err("cacheline tracking EEXIST, overlapping mappings aren't supported\n");
+ err_printk(entry->dev, entry,
+ "cacheline tracking EEXIST, overlapping mappings aren't supported\n");
}
}
/**
* dma_map_sg_attrs - Map the given buffer for DMA
* @dev: The device for which to perform the DMA operation
- * @sg: The sg_table object describing the buffer
+ * @sg: The sg_table object describing the buffer
+ * @nents: Number of entries to map
* @dir: DMA direction
* @attrs: Optional DMA attributes for the map operation
*
if (ti_work & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
handle_signal_work(regs, ti_work);
- if (ti_work & _TIF_NOTIFY_RESUME) {
+ if (ti_work & _TIF_NOTIFY_RESUME)
tracehook_notify_resume(regs);
- rseq_handle_notify_resume(NULL, regs);
- }
/* Architecture specific TIF work */
arch_exit_to_user_mode_work(regs, ti_work);
return;
if (ifh->nr_file_filters) {
- mm = get_task_mm(event->ctx->task);
+ mm = get_task_mm(task);
if (!mm)
goto restart;
* Allocates and initializes an irq_domain structure.
* Returns pointer to IRQ domain, or NULL on failure.
*/
-struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, int size,
+struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, unsigned int size,
irq_hw_number_t hwirq_max, int direct_max,
const struct irq_domain_ops *ops,
void *host_data)
* The risk of writer starvation is there, but the pathological use cases
* which trigger it are not necessarily the typical RT workloads.
*
+ * Fast-path orderings:
+ * The lock/unlock of readers can run in fast paths: lock and unlock are only
+ * atomic ops, and there is no inner lock to provide ACQUIRE and RELEASE
+ * semantics of rwbase_rt. Atomic ops should thus provide _acquire()
+ * and _release() (or stronger).
+ *
* Common code shared between RT rw_semaphore and rwlock
*/
* set.
*/
for (r = atomic_read(&rwb->readers); r < 0;) {
+ /* Fully-ordered if cmpxchg() succeeds, provides ACQUIRE */
if (likely(atomic_try_cmpxchg(&rwb->readers, &r, r + 1)))
return 1;
}
/*
* rwb->readers can only hit 0 when a writer is waiting for the
* active readers to leave the critical section.
+ *
+ * dec_and_test() is fully ordered, provides RELEASE.
*/
if (unlikely(atomic_dec_and_test(&rwb->readers)))
__rwbase_read_unlock(rwb, state);
{
struct rt_mutex_base *rtm = &rwb->rtmutex;
- atomic_add(READER_BIAS - bias, &rwb->readers);
+ /*
+ * _release() is needed in case that reader is in fast path, pairing
+ * with atomic_try_cmpxchg() in rwbase_read_trylock(), provides RELEASE
+ */
+ (void)atomic_add_return_release(READER_BIAS - bias, &rwb->readers);
raw_spin_unlock_irqrestore(&rtm->wait_lock, flags);
rwbase_rtmutex_unlock(rtm);
}
__rwbase_write_unlock(rwb, WRITER_BIAS - 1, flags);
}
+static inline bool __rwbase_write_trylock(struct rwbase_rt *rwb)
+{
+ /* Can do without CAS because we're serialized by wait_lock. */
+ lockdep_assert_held(&rwb->rtmutex.wait_lock);
+
+ /*
+ * _acquire is needed in case the reader is in the fast path, pairing
+ * with rwbase_read_unlock(), provides ACQUIRE.
+ */
+ if (!atomic_read_acquire(&rwb->readers)) {
+ atomic_set(&rwb->readers, WRITER_BIAS);
+ return 1;
+ }
+
+ return 0;
+}
+
static int __sched rwbase_write_lock(struct rwbase_rt *rwb,
unsigned int state)
{
atomic_sub(READER_BIAS, &rwb->readers);
raw_spin_lock_irqsave(&rtm->wait_lock, flags);
- /*
- * set_current_state() for rw_semaphore
- * current_save_and_set_rtlock_wait_state() for rwlock
- */
- rwbase_set_and_save_current_state(state);
+ if (__rwbase_write_trylock(rwb))
+ goto out_unlock;
- /* Block until all readers have left the critical section. */
- for (; atomic_read(&rwb->readers);) {
+ rwbase_set_and_save_current_state(state);
+ for (;;) {
/* Optimized out for rwlocks */
if (rwbase_signal_pending_state(state, current)) {
- __set_current_state(TASK_RUNNING);
+ rwbase_restore_current_state();
__rwbase_write_unlock(rwb, 0, flags);
return -EINTR;
}
+
+ if (__rwbase_write_trylock(rwb))
+ break;
+
raw_spin_unlock_irqrestore(&rtm->wait_lock, flags);
+ rwbase_schedule();
+ raw_spin_lock_irqsave(&rtm->wait_lock, flags);
- /*
- * Schedule and wait for the readers to leave the critical
- * section. The last reader leaving it wakes the waiter.
- */
- if (atomic_read(&rwb->readers) != 0)
- rwbase_schedule();
set_current_state(state);
- raw_spin_lock_irqsave(&rtm->wait_lock, flags);
}
-
- atomic_set(&rwb->readers, WRITER_BIAS);
rwbase_restore_current_state();
+
+out_unlock:
raw_spin_unlock_irqrestore(&rtm->wait_lock, flags);
return 0;
}
atomic_sub(READER_BIAS, &rwb->readers);
raw_spin_lock_irqsave(&rtm->wait_lock, flags);
- if (!atomic_read(&rwb->readers)) {
- atomic_set(&rwb->readers, WRITER_BIAS);
+ if (__rwbase_write_trylock(rwb)) {
raw_spin_unlock_irqrestore(&rtm->wait_lock, flags);
return 1;
}
return;
err_free_descs:
- memblock_free(__pa(new_descs), new_descs_size);
+ memblock_free_ptr(new_descs, new_descs_size);
err_free_log_buf:
- memblock_free(__pa(new_log_buf), new_log_buf_len);
+ memblock_free_ptr(new_log_buf, new_log_buf_len);
}
static bool __read_mostly ignore_loglevel;
if (unlikely(t->flags & PF_EXITING))
return;
- ret = rseq_ip_fixup(regs);
- if (unlikely(ret < 0))
- goto error;
+
+ /*
+ * regs is NULL if and only if the caller is in a syscall path. Skip
+ * fixup and leave rseq_cs as is so that rseq_sycall() will detect and
+ * kill a misbehaving userspace on debug kernels.
+ */
+ if (regs) {
+ ret = rseq_ip_fixup(regs);
+ if (unlikely(ret < 0))
+ goto error;
+ }
if (unlikely(rseq_update_cpu_id(t)))
goto error;
return;
}
}
- *newval += now;
+ if (*newval)
+ *newval += now;
}
/*
if (bt == NULL)
return -EINVAL;
+ if (bt->trace_state == Blktrace_running) {
+ bt->trace_state = Blktrace_stopped;
+ spin_lock_irq(&running_trace_lock);
+ list_del_init(&bt->running_list);
+ spin_unlock_irq(&running_trace_lock);
+ relay_flush(bt->rchan);
+ }
+
put_probe_ref();
synchronize_rcu();
blk_trace_free(bt);
config DEBUG_INFO_DWARF5
bool "Generate DWARF Version 5 debuginfo"
- depends on GCC_VERSION >= 50000 || (CC_IS_CLANG && (AS_IS_LLVM || (AS_IS_GNU && AS_VERSION >= 23502)))
+ depends on !CC_IS_CLANG || (CC_IS_CLANG && (AS_IS_LLVM || (AS_IS_GNU && AS_VERSION >= 23502)))
depends on !DEBUG_INFO_BTF
help
Generate DWARF v5 debug info. Requires binutils 2.35.2, gcc 5.0+ (gcc
int "Warn for stack frames larger than"
range 0 8192
default 2048 if GCC_PLUGIN_LATENT_ENTROPY
- default 1536 if (!64BIT && PARISC)
+ default 1536 if (!64BIT && (PARISC || XTENSA))
default 1024 if (!64BIT && !PARISC)
default 2048 if 64BIT
help
config KASAN_GENERIC
bool "Generic mode"
depends on HAVE_ARCH_KASAN && CC_HAS_KASAN_GENERIC
+ depends on CC_HAS_WORKING_NOSANITIZE_ADDRESS
select SLUB_DEBUG if SLUB
select CONSTRUCTORS
help
config KASAN_SW_TAGS
bool "Software tag-based mode"
depends on HAVE_ARCH_KASAN_SW_TAGS && CC_HAS_KASAN_SW_TAGS
+ depends on CC_HAS_WORKING_NOSANITIZE_ADDRESS
select SLUB_DEBUG if SLUB
select CONSTRUCTORS
help
xbc_data = NULL;
xbc_data_size = 0;
xbc_node_num = 0;
- memblock_free(__pa(xbc_nodes), sizeof(struct xbc_node) * XBC_NODE_MAX);
+ memblock_free_ptr(xbc_nodes, sizeof(struct xbc_node) * XBC_NODE_MAX);
xbc_nodes = NULL;
brace_index = 0;
}
return 0;
}
EXPORT_SYMBOL(import_single_range);
+
+/**
+ * iov_iter_restore() - Restore a &struct iov_iter to the same state as when
+ * iov_iter_save_state() was called.
+ *
+ * @i: &struct iov_iter to restore
+ * @state: state to restore from
+ *
+ * Used after iov_iter_save_state() to bring restore @i, if operations may
+ * have advanced it.
+ *
+ * Note: only works on ITER_IOVEC, ITER_BVEC, and ITER_KVEC
+ */
+void iov_iter_restore(struct iov_iter *i, struct iov_iter_state *state)
+{
+ if (WARN_ON_ONCE(!iov_iter_is_bvec(i) && !iter_is_iovec(i)) &&
+ !iov_iter_is_kvec(i))
+ return;
+ i->iov_offset = state->iov_offset;
+ i->count = state->count;
+ /*
+ * For the *vec iters, nr_segs + iov is constant - if we increment
+ * the vec, then we also decrement the nr_segs count. Hence we don't
+ * need to track both of these, just one is enough and we can deduct
+ * the other from that. ITER_KVEC and ITER_IOVEC are the same struct
+ * size, so we can just increment the iov pointer as they are unionzed.
+ * ITER_BVEC _may_ be the same size on some archs, but on others it is
+ * not. Be safe and handle it separately.
+ */
+ BUILD_BUG_ON(sizeof(struct iovec) != sizeof(struct kvec));
+ if (iov_iter_is_bvec(i))
+ i->bvec -= state->nr_segs - i->nr_segs;
+ else
+ i->iov -= state->nr_segs - i->nr_segs;
+ i->nr_segs = state->nr_segs;
+}
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
-/* Copyright (c) 2016-2018, NXP Semiconductors
+/* Copyright 2016-2018 NXP
* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
*/
#include <linux/packing.h>
return pci_iomap_wc_range(dev, bar, 0, maxlen);
}
EXPORT_SYMBOL_GPL(pci_iomap_wc);
+
+/*
+ * pci_iounmap() somewhat illogically comes from lib/iomap.c for the
+ * CONFIG_GENERIC_IOMAP case, because that's the code that knows about
+ * the different IOMAP ranges.
+ *
+ * But if the architecture does not use the generic iomap code, and if
+ * it has _not_ defined it's own private pci_iounmap function, we define
+ * it here.
+ *
+ * NOTE! This default implementation assumes that if the architecture
+ * support ioport mapping (HAS_IOPORT_MAP), the ioport mapping will
+ * be fixed to the range [ PCI_IOBASE, PCI_IOBASE+IO_SPACE_LIMIT [,
+ * and does not need unmapping with 'ioport_unmap()'.
+ *
+ * If you have different rules for your architecture, you need to
+ * implement your own pci_iounmap() that knows the rules for where
+ * and how IO vs MEM get mapped.
+ *
+ * This code is odd, and the ARCH_HAS/ARCH_WANTS #define logic comes
+ * from legacy <asm-generic/io.h> header file behavior. In particular,
+ * it would seem to make sense to do the iounmap(p) for the non-IO-space
+ * case here regardless, but that's not what the old header file code
+ * did. Probably incorrectly, but this is meant to be bug-for-bug
+ * compatible.
+ */
+#if defined(ARCH_WANTS_GENERIC_PCI_IOUNMAP)
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *p)
+{
+#ifdef ARCH_HAS_GENERIC_IOPORT_MAP
+ uintptr_t start = (uintptr_t) PCI_IOBASE;
+ uintptr_t addr = (uintptr_t) p;
+
+ if (addr >= start && addr < start + IO_SPACE_LIMIT)
+ return;
+ iounmap(p);
+#endif
+}
+EXPORT_SYMBOL(pci_iounmap);
+
+#endif /* ARCH_WANTS_GENERIC_PCI_IOUNMAP */
+
#endif /* CONFIG_PCI */
sfrom = (unsigned short *)(from);
loops = len >> 1;
- do
-#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
- *sout++ = *sfrom++;
-#else
- *sout++ = get_unaligned16(sfrom++);
-#endif
- while (--loops);
+ do {
+ if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS))
+ *sout++ = *sfrom++;
+ else
+ *sout++ = get_unaligned16(sfrom++);
+ } while (--loops);
out = (unsigned char *)sout;
from = (unsigned char *)sfrom;
} else { /* dist == 1 or dist == 2 */
ssize_t nr_integers = 0, i;
question = "123";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)1, nr_integers);
KUNIT_EXPECT_EQ(test, 123ul, answers[0]);
kfree(answers);
question = "123abc";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)1, nr_integers);
KUNIT_EXPECT_EQ(test, 123ul, answers[0]);
kfree(answers);
question = "a123";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)0, nr_integers);
kfree(answers);
question = "12 35";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)2, nr_integers);
for (i = 0; i < nr_integers; i++)
kfree(answers);
question = "12 35 46";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)3, nr_integers);
for (i = 0; i < nr_integers; i++)
kfree(answers);
question = "12 35 abc 46";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)2, nr_integers);
for (i = 0; i < 2; i++)
kfree(answers);
question = "";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)0, nr_integers);
kfree(answers);
question = "\n";
- answers = str_to_target_ids(question, strnlen(question, 128),
+ answers = str_to_target_ids(question, strlen(question),
&nr_integers);
KUNIT_EXPECT_EQ(test, (ssize_t)0, nr_integers);
kfree(answers);
"syscall_or_cpuset",
"mempolicy_mbind",
"numa_misplaced",
- "cma",
+ "contig_range",
+ "longterm_pin",
+ "demotion",
};
const struct trace_print_flags pageflag_names[] = {
* from &migrate_nodes. This will verify that future list.h changes
* don't break STABLE_NODE_DUP_HEAD. Only recent gcc can handle it.
*/
-#if defined(GCC_VERSION) && GCC_VERSION >= 40903
BUILD_BUG_ON(STABLE_NODE_DUP_HEAD <= &migrate_nodes);
BUILD_BUG_ON(STABLE_NODE_DUP_HEAD >= &migrate_nodes + 1);
-#endif
if (stable_node->head == &migrate_nodes)
list_del(&stable_node->list);
kfree(old_array);
else if (old_array != memblock_memory_init_regions &&
old_array != memblock_reserved_init_regions)
- memblock_free(__pa(old_array), old_alloc_size);
+ memblock_free_ptr(old_array, old_alloc_size);
/*
* Reserve the new array if that comes from the memblock. Otherwise, we
}
/**
+ * memblock_free_ptr - free boot memory allocation
+ * @ptr: starting address of the boot memory allocation
+ * @size: size of the boot memory block in bytes
+ *
+ * Free boot memory block previously allocated by memblock_alloc_xx() API.
+ * The freeing memory will not be released to the buddy allocator.
+ */
+void __init_memblock memblock_free_ptr(void *ptr, size_t size)
+{
+ if (ptr)
+ memblock_free(__pa(ptr), size);
+}
+
+/**
* memblock_free - free boot memory block
* @base: phys starting address of the boot memory block
* @size: size of the boot memory block in bytes
/* memcg and lruvec stats flushing */
static void flush_memcg_stats_dwork(struct work_struct *w);
static DECLARE_DEFERRABLE_WORK(stats_flush_dwork, flush_memcg_stats_dwork);
-static void flush_memcg_stats_work(struct work_struct *w);
-static DECLARE_WORK(stats_flush_work, flush_memcg_stats_work);
-static DEFINE_PER_CPU(unsigned int, stats_flush_threshold);
static DEFINE_SPINLOCK(stats_flush_lock);
#define THRESHOLDS_EVENTS_TARGET 128
/* Update lruvec */
__this_cpu_add(pn->lruvec_stats_percpu->state[idx], val);
- if (!(__this_cpu_inc_return(stats_flush_threshold) % MEMCG_CHARGE_BATCH))
- queue_work(system_unbound_wq, &stats_flush_work);
}
/**
queue_delayed_work(system_unbound_wq, &stats_flush_dwork, 2UL*HZ);
}
-static void flush_memcg_stats_work(struct work_struct *w)
-{
- mem_cgroup_flush_stats();
-}
-
static void mem_cgroup_css_rstat_flush(struct cgroup_subsys_state *css, int cpu)
{
struct mem_cgroup *memcg = mem_cgroup_from_css(css);
struct vm_area_struct *vma)
{
unsigned long address = vma_address(page, vma);
+ unsigned long ret = 0;
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
if (pmd_devmap(*pmd))
return PMD_SHIFT;
pte = pte_offset_map(pmd, address);
- if (!pte_present(*pte))
- return 0;
- if (pte_devmap(*pte))
- return PAGE_SHIFT;
- return 0;
+ if (pte_present(*pte) && pte_devmap(*pte))
+ ret = PAGE_SHIFT;
+ pte_unmap(pte);
+ return ret;
}
/*
*/
static inline bool HWPoisonHandlable(struct page *page)
{
- return PageLRU(page) || __PageMovable(page);
+ return PageLRU(page) || __PageMovable(page) || is_free_buddy_page(page);
}
static int __get_hwpoison_page(struct page *page)
unmap_mapping_range_tree(&mapping->i_mmap, &details);
i_mmap_unlock_write(mapping);
}
+EXPORT_SYMBOL_GPL(unmap_mapping_pages);
/**
* unmap_mapping_range - unmap the portion of all mmaps in the specified
case SHMEM_HUGE_ALWAYS:
return true;
case SHMEM_HUGE_WITHIN_SIZE:
- index = round_up(index, HPAGE_PMD_NR);
+ index = round_up(index + 1, HPAGE_PMD_NR);
i_size = round_up(i_size_read(inode), PAGE_SIZE);
- if (i_size >= HPAGE_PMD_SIZE && (i_size >> PAGE_SHIFT) >= index)
+ if (i_size >> PAGE_SHIFT >= index)
return true;
fallthrough;
case SHMEM_HUGE_ADVISE:
pagevec_lru_move_fn(pvec, lru_lazyfree_fn);
activate_page_drain(cpu);
- invalidate_bh_lrus_cpu(cpu);
}
/**
local_unlock(&lru_pvecs.lock);
}
+/*
+ * It's called from per-cpu workqueue context in SMP case so
+ * lru_add_drain_cpu and invalidate_bh_lrus_cpu should run on
+ * the same cpu. It shouldn't be a problem in !SMP case since
+ * the core is only one and the locks will disable preemption.
+ */
+static void lru_add_and_bh_lrus_drain(void)
+{
+ local_lock(&lru_pvecs.lock);
+ lru_add_drain_cpu(smp_processor_id());
+ local_unlock(&lru_pvecs.lock);
+ invalidate_bh_lrus_cpu();
+}
+
void lru_add_drain_cpu_zone(struct zone *zone)
{
local_lock(&lru_pvecs.lock);
static void lru_add_drain_per_cpu(struct work_struct *dummy)
{
- lru_add_drain();
+ lru_add_and_bh_lrus_drain();
}
/*
*/
__lru_add_drain_all(true);
#else
- lru_add_drain();
+ lru_add_and_bh_lrus_drain();
#endif
}
size_t *lenp, loff_t *ppos)
{
struct ctl_table t;
- int new_policy;
+ int new_policy = -1;
int ret;
/*
t = *table;
t.data = &new_policy;
ret = proc_dointvec_minmax(&t, write, buffer, lenp, ppos);
- if (ret)
+ if (ret || new_policy == -1)
return ret;
mm_compute_batch(new_policy);
inc_lruvec_state(lruvec, WORKINGSET_REFAULT_BASE + file);
+ mem_cgroup_flush_stats();
/*
* Compare the distance to the existing workingset size. We
* don't activate pages that couldn't stay resident even if
enum caif_states state;
};
-static void robust_list_del(struct list_head *delete_node)
-{
- struct list_head *list_node;
- struct list_head *n;
- ASSERT_RTNL();
- list_for_each_safe(list_node, n, &chnl_net_list) {
- if (list_node == delete_node) {
- list_del(list_node);
- return;
- }
- }
- WARN_ON(1);
-}
-
static int chnl_recv_cb(struct cflayer *layr, struct cfpkt *pkt)
{
struct sk_buff *skb;
ASSERT_RTNL();
priv = netdev_priv(dev);
strncpy(priv->name, dev->name, sizeof(priv->name));
+ INIT_LIST_HEAD(&priv->list_field);
return 0;
}
struct chnl_net *priv;
ASSERT_RTNL();
priv = netdev_priv(dev);
- robust_list_del(&priv->list_field);
+ list_del_init(&priv->list_field);
}
static const struct net_device_ops netdev_ops = {
rtnl_lock();
list_for_each_safe(list_node, _tmp, &chnl_net_list) {
dev = list_entry(list_node, struct chnl_net, list_field);
- list_del(list_node);
+ list_del_init(list_node);
delete_device(dev);
}
rtnl_unlock();
*/
void napi_enable(struct napi_struct *n)
{
- BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state));
- smp_mb__before_atomic();
- clear_bit(NAPI_STATE_SCHED, &n->state);
- clear_bit(NAPI_STATE_NPSVC, &n->state);
- if (n->dev->threaded && n->thread)
- set_bit(NAPI_STATE_THREADED, &n->state);
+ unsigned long val, new;
+
+ do {
+ val = READ_ONCE(n->state);
+ BUG_ON(!test_bit(NAPI_STATE_SCHED, &val));
+
+ new = val & ~(NAPIF_STATE_SCHED | NAPIF_STATE_NPSVC);
+ if (n->dev->threaded && n->thread)
+ new |= NAPIF_STATE_THREADED;
+ } while (cmpxchg(&n->state, val, new) != val);
}
EXPORT_SYMBOL(napi_enable);
struct update_classid_context *ctx = (void *)v;
struct socket *sock = sock_from_file(file);
- if (sock) {
- spin_lock(&cgroup_sk_update_lock);
+ if (sock)
sock_cgroup_set_classid(&sock->sk->sk_cgrp_data, ctx->classid);
- spin_unlock(&cgroup_sk_update_lock);
- }
if (--ctx->batch == 0) {
ctx->batch = UPDATE_CLASSID_BATCH;
return n + 1;
struct css_task_iter it;
struct task_struct *p;
- cgroup_sk_alloc_disable();
-
cs->classid = (u32)value;
css_task_iter_start(css, 0, &it);
if (!dev)
return -ENODEV;
- cgroup_sk_alloc_disable();
-
rtnl_lock();
ret = netprio_set_prio(of_css(of), dev, prio);
static int update_netprio(const void *v, struct file *file, unsigned n)
{
struct socket *sock = sock_from_file(file);
- if (sock) {
- spin_lock(&cgroup_sk_update_lock);
+
+ if (sock)
sock_cgroup_set_prioidx(&sock->sk->sk_cgrp_data,
(unsigned long)v);
- spin_unlock(&cgroup_sk_update_lock);
- }
return 0;
}
struct task_struct *p;
struct cgroup_subsys_state *css;
- cgroup_sk_alloc_disable();
-
cgroup_taskset_for_each(p, css, tset) {
void *v = (void *)(unsigned long)css->id;
void lock_sock_nested(struct sock *sk, int subclass)
{
+ /* The sk_lock has mutex_lock() semantics here. */
+ mutex_acquire(&sk->sk_lock.dep_map, subclass, 0, _RET_IP_);
+
might_sleep();
spin_lock_bh(&sk->sk_lock.slock);
if (sk->sk_lock.owned)
__lock_sock(sk);
sk->sk_lock.owned = 1;
- spin_unlock(&sk->sk_lock.slock);
- /*
- * The sk_lock has mutex_lock() semantics here:
- */
- mutex_acquire(&sk->sk_lock.dep_map, subclass, 0, _RET_IP_);
- local_bh_enable();
+ spin_unlock_bh(&sk->sk_lock.slock);
}
EXPORT_SYMBOL(lock_sock_nested);
*/
bool lock_sock_fast(struct sock *sk) __acquires(&sk->sk_lock.slock)
{
+ /* The sk_lock has mutex_lock() semantics here. */
+ mutex_acquire(&sk->sk_lock.dep_map, 0, 0, _RET_IP_);
+
might_sleep();
spin_lock_bh(&sk->sk_lock.slock);
- if (!sk->sk_lock.owned)
+ if (!sk->sk_lock.owned) {
/*
- * Note : We must disable BH
+ * Fast path return with bottom halves disabled and
+ * sock::sk_lock.slock held.
+ *
+ * The 'mutex' is not contended and holding
+ * sock::sk_lock.slock prevents all other lockers to
+ * proceed so the corresponding unlock_sock_fast() can
+ * avoid the slow path of release_sock() completely and
+ * just release slock.
+ *
+ * From a semantical POV this is equivalent to 'acquiring'
+ * the 'mutex', hence the corresponding lockdep
+ * mutex_release() has to happen in the fast path of
+ * unlock_sock_fast().
*/
return false;
+ }
__lock_sock(sk);
sk->sk_lock.owned = 1;
- spin_unlock(&sk->sk_lock.slock);
- /*
- * The sk_lock has mutex_lock() semantics here:
- */
- mutex_acquire(&sk->sk_lock.dep_map, 0, 0, _RET_IP_);
__acquire(&sk->sk_lock.slock);
- local_bh_enable();
+ spin_unlock_bh(&sk->sk_lock.slock);
return true;
}
EXPORT_SYMBOL(lock_sock_fast);
newdp->dccps_role = DCCP_ROLE_SERVER;
newdp->dccps_hc_rx_ackvec = NULL;
newdp->dccps_service_list = NULL;
+ newdp->dccps_hc_rx_ccid = NULL;
+ newdp->dccps_hc_tx_ccid = NULL;
newdp->dccps_service = dreq->dreq_service;
newdp->dccps_timestamp_echo = dreq->dreq_timestamp_echo;
newdp->dccps_timestamp_time = dreq->dreq_timestamp_time;
return queue_work(dsa_owq, work);
}
+void dsa_flush_workqueue(void)
+{
+ flush_workqueue(dsa_owq);
+}
+
int dsa_devlink_param_get(struct devlink *dl, u32 id,
struct devlink_param_gset_ctx *ctx)
{
{
struct devlink_port *dlp = &dp->devlink_port;
bool dsa_port_link_registered = false;
+ struct dsa_switch *ds = dp->ds;
bool dsa_port_enabled = false;
int err = 0;
INIT_LIST_HEAD(&dp->fdbs);
INIT_LIST_HEAD(&dp->mdbs);
+ if (ds->ops->port_setup) {
+ err = ds->ops->port_setup(ds, dp->index);
+ if (err)
+ return err;
+ }
+
switch (dp->type) {
case DSA_PORT_TYPE_UNUSED:
dsa_port_disable(dp);
dsa_port_disable(dp);
if (err && dsa_port_link_registered)
dsa_port_link_unregister_of(dp);
- if (err)
+ if (err) {
+ if (ds->ops->port_teardown)
+ ds->ops->port_teardown(ds, dp->index);
return err;
+ }
dp->setup = true;
static void dsa_port_teardown(struct dsa_port *dp)
{
struct devlink_port *dlp = &dp->devlink_port;
+ struct dsa_switch *ds = dp->ds;
struct dsa_mac_addr *a, *tmp;
if (!dp->setup)
return;
+ if (ds->ops->port_teardown)
+ ds->ops->port_teardown(ds, dp->index);
+
devlink_port_type_clear(dlp);
switch (dp->type) {
dp->devlink_port_setup = false;
}
+/* Destroy the current devlink port, and create a new one which has the UNUSED
+ * flavour. At this point, any call to ds->ops->port_setup has been already
+ * balanced out by a call to ds->ops->port_teardown, so we know that any
+ * devlink port regions the driver had are now unregistered. We then call its
+ * ds->ops->port_setup again, in order for the driver to re-create them on the
+ * new devlink port.
+ */
+static int dsa_port_reinit_as_unused(struct dsa_port *dp)
+{
+ struct dsa_switch *ds = dp->ds;
+ int err;
+
+ dsa_port_devlink_teardown(dp);
+ dp->type = DSA_PORT_TYPE_UNUSED;
+ err = dsa_port_devlink_setup(dp);
+ if (err)
+ return err;
+
+ if (ds->ops->port_setup) {
+ /* On error, leave the devlink port registered,
+ * dsa_switch_teardown will clean it up later.
+ */
+ err = ds->ops->port_setup(ds, dp->index);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int dsa_devlink_info_get(struct devlink *dl,
struct devlink_info_req *req,
struct netlink_ext_ack *extack)
devlink_params_publish(ds->devlink);
if (!ds->slave_mii_bus && ds->ops->phy_read) {
- ds->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
+ ds->slave_mii_bus = mdiobus_alloc();
if (!ds->slave_mii_bus) {
err = -ENOMEM;
goto teardown;
err = mdiobus_register(ds->slave_mii_bus);
if (err < 0)
- goto teardown;
+ goto free_slave_mii_bus;
}
ds->setup = true;
return 0;
+free_slave_mii_bus:
+ if (ds->slave_mii_bus && ds->ops->phy_read)
+ mdiobus_free(ds->slave_mii_bus);
teardown:
if (ds->ops->teardown)
ds->ops->teardown(ds);
if (!ds->setup)
return;
- if (ds->slave_mii_bus && ds->ops->phy_read)
+ if (ds->slave_mii_bus && ds->ops->phy_read) {
mdiobus_unregister(ds->slave_mii_bus);
+ mdiobus_free(ds->slave_mii_bus);
+ ds->slave_mii_bus = NULL;
+ }
dsa_switch_unregister_notifier(ds);
ds->setup = false;
}
+/* First tear down the non-shared, then the shared ports. This ensures that
+ * all work items scheduled by our switchdev handlers for user ports have
+ * completed before we destroy the refcounting kept on the shared ports.
+ */
+static void dsa_tree_teardown_ports(struct dsa_switch_tree *dst)
+{
+ struct dsa_port *dp;
+
+ list_for_each_entry(dp, &dst->ports, list)
+ if (dsa_port_is_user(dp) || dsa_port_is_unused(dp))
+ dsa_port_teardown(dp);
+
+ dsa_flush_workqueue();
+
+ list_for_each_entry(dp, &dst->ports, list)
+ if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
+ dsa_port_teardown(dp);
+}
+
+static void dsa_tree_teardown_switches(struct dsa_switch_tree *dst)
+{
+ struct dsa_port *dp;
+
+ list_for_each_entry(dp, &dst->ports, list)
+ dsa_switch_teardown(dp->ds);
+}
+
static int dsa_tree_setup_switches(struct dsa_switch_tree *dst)
{
struct dsa_port *dp;
list_for_each_entry(dp, &dst->ports, list) {
err = dsa_port_setup(dp);
if (err) {
- dsa_port_devlink_teardown(dp);
- dp->type = DSA_PORT_TYPE_UNUSED;
- err = dsa_port_devlink_setup(dp);
+ err = dsa_port_reinit_as_unused(dp);
if (err)
goto teardown;
- continue;
}
}
return 0;
teardown:
- list_for_each_entry(dp, &dst->ports, list)
- dsa_port_teardown(dp);
+ dsa_tree_teardown_ports(dst);
- list_for_each_entry(dp, &dst->ports, list)
- dsa_switch_teardown(dp->ds);
+ dsa_tree_teardown_switches(dst);
return err;
}
-static void dsa_tree_teardown_switches(struct dsa_switch_tree *dst)
-{
- struct dsa_port *dp;
-
- list_for_each_entry(dp, &dst->ports, list)
- dsa_port_teardown(dp);
-
- list_for_each_entry(dp, &dst->ports, list)
- dsa_switch_teardown(dp->ds);
-}
-
static int dsa_tree_setup_master(struct dsa_switch_tree *dst)
{
struct dsa_port *dp;
teardown_master:
dsa_tree_teardown_master(dst);
teardown_switches:
+ dsa_tree_teardown_ports(dst);
dsa_tree_teardown_switches(dst);
teardown_cpu_ports:
dsa_tree_teardown_cpu_ports(dst);
dsa_tree_teardown_master(dst);
+ dsa_tree_teardown_ports(dst);
+
dsa_tree_teardown_switches(dst);
dsa_tree_teardown_cpu_ports(dst);
mutex_unlock(&dsa2_mutex);
}
EXPORT_SYMBOL_GPL(dsa_unregister_switch);
+
+/* If the DSA master chooses to unregister its net_device on .shutdown, DSA is
+ * blocking that operation from completion, due to the dev_hold taken inside
+ * netdev_upper_dev_link. Unlink the DSA slave interfaces from being uppers of
+ * the DSA master, so that the system can reboot successfully.
+ */
+void dsa_switch_shutdown(struct dsa_switch *ds)
+{
+ struct net_device *master, *slave_dev;
+ LIST_HEAD(unregister_list);
+ struct dsa_port *dp;
+
+ mutex_lock(&dsa2_mutex);
+ rtnl_lock();
+
+ list_for_each_entry(dp, &ds->dst->ports, list) {
+ if (dp->ds != ds)
+ continue;
+
+ if (!dsa_port_is_user(dp))
+ continue;
+
+ master = dp->cpu_dp->master;
+ slave_dev = dp->slave;
+
+ netdev_upper_dev_unlink(master, slave_dev);
+ /* Just unlinking ourselves as uppers of the master is not
+ * sufficient. When the master net device unregisters, that will
+ * also call dev_close, which we will catch as NETDEV_GOING_DOWN
+ * and trigger a dev_close on our own devices (dsa_slave_close).
+ * In turn, that will call dev_mc_unsync on the master's net
+ * device. If the master is also a DSA switch port, this will
+ * trigger dsa_slave_set_rx_mode which will call dev_mc_sync on
+ * its own master. Lockdep will complain about the fact that
+ * all cascaded masters have the same dsa_master_addr_list_lock_key,
+ * which it normally would not do if the cascaded masters would
+ * be in a proper upper/lower relationship, which we've just
+ * destroyed.
+ * To suppress the lockdep warnings, let's actually unregister
+ * the DSA slave interfaces too, to avoid the nonsensical
+ * multicast address list synchronization on shutdown.
+ */
+ unregister_netdevice_queue(slave_dev, &unregister_list);
+ }
+ unregister_netdevice_many(&unregister_list);
+
+ rtnl_unlock();
+ mutex_unlock(&dsa2_mutex);
+}
+EXPORT_SYMBOL_GPL(dsa_switch_shutdown);
const struct dsa_device_ops *dsa_find_tagger_by_name(const char *buf);
bool dsa_schedule_work(struct work_struct *work);
+void dsa_flush_workqueue(void);
const char *dsa_tag_protocol_to_str(const struct dsa_device_ops *ops);
static inline int dsa_tag_protocol_overhead(const struct dsa_device_ops *ops)
* use the switch internal MDIO bus instead
*/
ret = dsa_slave_phy_connect(slave_dev, dp->index, phy_flags);
- if (ret) {
- netdev_err(slave_dev,
- "failed to connect to port %d: %d\n",
- dp->index, ret);
- phylink_destroy(dp->pl);
- return ret;
- }
+ }
+ if (ret) {
+ netdev_err(slave_dev, "failed to connect to PHY: %pe\n",
+ ERR_PTR(ret));
+ phylink_destroy(dp->pl);
}
return ret;
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2019 NXP Semiconductors
+/* Copyright 2019 NXP
*/
#include <linux/dsa/ocelot.h>
#include <soc/mscc/ocelot.h>
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2020-2021 NXP Semiconductors
+/* Copyright 2020-2021 NXP
*
* An implementation of the software-defined tag_8021q.c tagger format, which
* also preserves full functionality under a vlan_filtering bridge. It does
rcu_assign_pointer(old->nh_grp, newg);
if (newg->resilient) {
+ /* Make sure concurrent readers are not using 'oldg' anymore. */
+ synchronize_net();
rcu_assign_pointer(oldg->res_table, tmp_table);
rcu_assign_pointer(oldg->spare->res_table, tmp_table);
}
};
static int nexthops_dump(struct net *net, struct notifier_block *nb,
+ enum nexthop_event_type event_type,
struct netlink_ext_ack *extack)
{
struct rb_root *root = &net->nexthop.rb_root;
struct nexthop *nh;
nh = rb_entry(node, struct nexthop, rb_node);
- err = call_nexthop_notifier(nb, net, NEXTHOP_EVENT_REPLACE, nh,
- extack);
+ err = call_nexthop_notifier(nb, net, event_type, nh, extack);
if (err)
break;
}
int err;
rtnl_lock();
- err = nexthops_dump(net, nb, extack);
+ err = nexthops_dump(net, nb, NEXTHOP_EVENT_REPLACE, extack);
if (err)
goto unlock;
err = blocking_notifier_chain_register(&net->nexthop.notifier_chain,
int unregister_nexthop_notifier(struct net *net, struct notifier_block *nb)
{
- return blocking_notifier_chain_unregister(&net->nexthop.notifier_chain,
- nb);
+ int err;
+
+ rtnl_lock();
+ err = blocking_notifier_chain_unregister(&net->nexthop.notifier_chain,
+ nb);
+ if (err)
+ goto unlock;
+ nexthops_dump(net, nb, NEXTHOP_EVENT_DEL, NULL);
+unlock:
+ rtnl_unlock();
+ return err;
}
EXPORT_SYMBOL(unregister_nexthop_notifier);
if (dup_sack && (sacked & TCPCB_RETRANS)) {
if (tp->undo_marker && tp->undo_retrans > 0 &&
after(end_seq, tp->undo_marker))
- tp->undo_retrans--;
+ tp->undo_retrans = max_t(int, 0, tp->undo_retrans - pcount);
if ((sacked & TCPCB_SACKED_ACKED) &&
before(start_seq, state->reord))
state->reord = start_seq;
{
int err;
- udp_tunnel_nic_workqueue = alloc_workqueue("udp_tunnel_nic", 0, 0);
+ udp_tunnel_nic_workqueue = alloc_ordered_workqueue("udp_tunnel_nic", 0);
if (!udp_tunnel_nic_workqueue)
return -ENOMEM;
int err = -ENOMEM;
int allow_create = 1;
int replace_required = 0;
- int sernum = fib6_new_sernum(info->nl_net);
if (info->nlh) {
if (!(info->nlh->nlmsg_flags & NLM_F_CREATE))
if (!err) {
if (rt->nh)
list_add(&rt->nh_list, &rt->nh->f6i_list);
- __fib6_update_sernum_upto_root(rt, sernum);
+ __fib6_update_sernum_upto_root(rt, fib6_new_sernum(info->nl_net));
fib6_start_gc(info->nl_net, rt);
}
}
if (tunnel->version == L2TP_HDR_VER_3 &&
- l2tp_v3_ensure_opt_in_linear(session, skb, &ptr, &optr))
+ l2tp_v3_ensure_opt_in_linear(session, skb, &ptr, &optr)) {
+ l2tp_session_dec_refcount(session);
goto invalid;
+ }
l2tp_recv_common(session, skb, ptr, optr, hdrflags, length);
l2tp_session_dec_refcount(session);
{
struct mctp_route *rt;
+ rcu_read_lock();
list_for_each_entry_rcu(rt, &net->mctp.routes, list)
mctp_route_release(rt);
+ rcu_read_unlock();
}
static struct pernet_operations mctp_net_ops = {
goto alloc_skb;
}
- must_collapse = (info->size_goal - skb->len > 0) &&
+ must_collapse = (info->size_goal > skb->len) &&
(skb_shinfo(skb)->nr_frags < sysctl_max_skb_frags);
if (must_collapse) {
size_bias = skb->len;
}
alloc_skb:
- if (!must_collapse && !ssk->sk_tx_skb_cache &&
+ if (!must_collapse &&
!mptcp_alloc_tx_skb(sk, ssk, info->data_lock_held))
return 0;
* Copyright (C) 2011, <lokec@ccs.neu.edu>
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/ethtool.h>
#include <linux/types.h>
#include <linux/mm.h>
goto out_rel;
}
/* get address to which the internal TCP socket is bound */
- kernel_getsockname(clcsock, (struct sockaddr *)&addrs);
+ if (kernel_getsockname(clcsock, (struct sockaddr *)&addrs) < 0)
+ goto out_rel;
/* analyze IP specific data of net_device belonging to TCP socket */
addr6 = (struct sockaddr_in6 *)&addrs;
rcu_read_lock();
abort_work);
struct smc_sock *smc = container_of(conn, struct smc_sock, conn);
+ lock_sock(&smc->sk);
smc_conn_kill(conn, true);
+ release_sock(&smc->sk);
sock_put(&smc->sk); /* sock_hold done by schedulers of abort_work */
}
static void tipc_sk_enqueue(struct sk_buff_head *inputq, struct sock *sk,
u32 dport, struct sk_buff_head *xmitq)
{
- unsigned long time_limit = jiffies + 2;
+ unsigned long time_limit = jiffies + usecs_to_jiffies(20000);
struct sk_buff *skb;
unsigned int lim;
atomic_t *dcnt;
other = unix_peer(sk);
if (other && unix_peer(other) != sk &&
- unix_recvq_full(other) &&
+ unix_recvq_full_lockless(other) &&
unix_dgram_peer_wake_me(sk, other))
writable = 0;
else
CLANG_FLAGS += -fintegrated-as
endif
+# By default, clang only warns when it encounters an unknown warning flag or
+# certain optimization flags it knows it has not implemented.
+# Make it behave more like gcc by erroring when these flags are encountered
+# so they can be implemented or wrapped in cc-option.
CLANG_FLAGS += -Werror=unknown-warning-option
+CLANG_FLAGS += -Werror=ignored-optimization-argument
KBUILD_CFLAGS += $(CLANG_FLAGS)
KBUILD_AFLAGS += $(CLANG_FLAGS)
export CLANG_FLAGS
CFLAGS_KASAN := $(CFLAGS_KASAN_SHADOW) \
$(call cc-param,asan-globals=1) \
$(call cc-param,asan-instrumentation-with-call-threshold=$(call_threshold)) \
- $(call cc-param,asan-stack=$(stack_enable)) \
$(call cc-param,asan-instrument-allocas=1)
endif
+CFLAGS_KASAN += $(call cc-param,asan-stack=$(stack_enable))
+
endif # CONFIG_KASAN_GENERIC
ifdef CONFIG_KASAN_SW_TAGS
# Stage 2 is handled by this file and does the following
# 1) Find all modules listed in modules.order
# 2) modpost is then used to
-# 3) create one <module>.mod.c file pr. module
+# 3) create one <module>.mod.c file per module
# 4) create one Module.symvers file with CRC for all exported symbols
# Step 3 is used to place certain information in the module's ELF
REGEX_KCONFIG_DEF = re.compile(DEF)
REGEX_KCONFIG_EXPR = re.compile(EXPR)
REGEX_KCONFIG_STMT = re.compile(STMT)
-REGEX_KCONFIG_HELP = re.compile(r"^\s+help\s*$")
REGEX_FILTER_SYMBOLS = re.compile(r"[A-Za-z0-9]$")
REGEX_NUMERIC = re.compile(r"0[xX][0-9a-fA-F]+|[0-9]+")
REGEX_QUOTES = re.compile("(\"(.*?)\")")
"continue.")
if args.commit:
+ if args.commit.startswith('HEAD'):
+ sys.exit("The --commit option can't use the HEAD ref")
+
args.find = False
if args.ignore:
lines = []
defined = []
references = []
- skip = False
if not os.path.exists(kfile):
return defined, references
if REGEX_KCONFIG_DEF.match(line):
symbol_def = REGEX_KCONFIG_DEF.findall(line)
defined.append(symbol_def[0])
- skip = False
- elif REGEX_KCONFIG_HELP.match(line):
- skip = True
- elif skip:
- # ignore content of help messages
- pass
elif REGEX_KCONFIG_STMT.match(line):
line = REGEX_QUOTES.sub("", line)
symbols = get_symbols_in_line(line)
import os
import re
import subprocess
+import sys
_DEFAULT_OUTPUT = 'compile_commands.json'
_DEFAULT_LOG_LEVEL = 'WARNING'
echo 2.23.0
;;
gcc)
- # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63293
- # https://lore.kernel.org/r/20210107111841.GN1551@shell.armlinux.org.uk
- if [ "$SRCARCH" = arm64 ]; then
- echo 5.1.0
- else
- echo 4.9.0
- fi
+ echo 5.1.0
;;
icc)
# temporary
#define EM_ARCV2 195
#endif
+#ifndef EM_RISCV
+#define EM_RISCV 243
+#endif
+
static uint32_t (*r)(const uint32_t *);
static uint16_t (*r2)(const uint16_t *);
static uint64_t (*r8)(const uint64_t *);
static int selinux_ptrace_traceme(struct task_struct *parent)
{
return avc_has_perm(&selinux_state,
- task_sid_subj(parent), task_sid_obj(current),
+ task_sid_obj(parent), task_sid_obj(current),
SECCLASS_PROCESS, PROCESS__PTRACE, NULL);
}
struct ipc_security_struct *isec;
struct msg_security_struct *msec;
struct common_audit_data ad;
- u32 sid = task_sid_subj(target);
+ u32 sid = task_sid_obj(target);
int rc;
isec = selinux_ipc(msq);
const char *caller)
{
struct smk_audit_info ad;
- struct smack_known *skp = smk_of_task_struct_subj(p);
+ struct smack_known *skp = smk_of_task_struct_obj(p);
int rc;
smk_ad_init(&ad, caller, LSM_AUDIT_DATA_TASK);
*/
static int smack_getprocattr(struct task_struct *p, char *name, char **value)
{
- struct smack_known *skp = smk_of_task_struct_subj(p);
+ struct smack_known *skp = smk_of_task_struct_obj(p);
char *cp;
int slen;
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __NR_userfaultfd
-#define __NR_userfaultfd 282
-#endif
#ifndef __NR_perf_event_open
# define __NR_perf_event_open 298
#endif
((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
#define __get_next(t, insn) \
- ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); leXX_to_cpu(t, r); })
+ ({ t r; memcpy(&r, insn->next_byte, sizeof(t)); insn->next_byte += sizeof(t); leXX_to_cpu(t, r); })
#define __peek_nbyte_next(t, insn, n) \
- ({ t r = *(t*)((insn)->next_byte + n); leXX_to_cpu(t, r); })
+ ({ t r; memcpy(&r, (insn)->next_byte + n, sizeof(t)); leXX_to_cpu(t, r); })
#define get_next(t, insn) \
({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
#include <stdlib.h>
-#define __pa(addr) (addr)
#define SMP_CACHE_BYTES 0
#define memblock_alloc(size, align) malloc(size)
-#define memblock_free(paddr, size) free(paddr)
+#define memblock_free_ptr(paddr, size) free(paddr)
#endif
# define __fallthrough __attribute__ ((fallthrough))
#endif
-#if GCC_VERSION >= 40300
+#if __has_attribute(__error__)
# define __compiletime_error(message) __attribute__((error(message)))
-#endif /* GCC_VERSION >= 40300 */
+#endif
/* &a[0] degrades to a pointer: a different type from an array */
#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
#endif
#define __printf(a, b) __attribute__((format(printf, a, b)))
#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-
-#if GCC_VERSION >= 50100
-#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
-#endif
#include <linux/compiler.h>
/*
- * In the fallback code below, we need to compute the minimum and
- * maximum values representable in a given type. These macros may also
- * be useful elsewhere, so we provide them outside the
- * COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW block.
- *
- * It would seem more obvious to do something like
+ * We need to compute the minimum and maximum values representable in a given
+ * type. These macros may also be useful elsewhere. It would seem more obvious
+ * to do something like:
*
* #define type_min(T) (T)(is_signed_type(T) ? (T)1 << (8*sizeof(T)-1) : 0)
* #define type_max(T) (T)(is_signed_type(T) ? ((T)1 << (8*sizeof(T)-1)) - 1 : ~(T)0)
#define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
#define type_min(T) ((T)((T)-type_max(T)-(T)1))
-
-#ifdef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
/*
* For simplicity and code hygiene, the fallback code below insists on
* a, b and *d having the same type (similar to the min() and max()
__builtin_mul_overflow(__a, __b, __d); \
})
-#else
-
-
-/* Checking for unsigned overflow is relatively easy without causing UB. */
-#define __unsigned_add_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = __a + __b; \
- *__d < __a; \
-})
-#define __unsigned_sub_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = __a - __b; \
- __a < __b; \
-})
-/*
- * If one of a or b is a compile-time constant, this avoids a division.
- */
-#define __unsigned_mul_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = __a * __b; \
- __builtin_constant_p(__b) ? \
- __b > 0 && __a > type_max(typeof(__a)) / __b : \
- __a > 0 && __b > type_max(typeof(__b)) / __a; \
-})
-
-/*
- * For signed types, detecting overflow is much harder, especially if
- * we want to avoid UB. But the interface of these macros is such that
- * we must provide a result in *d, and in fact we must produce the
- * result promised by gcc's builtins, which is simply the possibly
- * wrapped-around value. Fortunately, we can just formally do the
- * operations in the widest relevant unsigned type (u64) and then
- * truncate the result - gcc is smart enough to generate the same code
- * with and without the (u64) casts.
- */
-
-/*
- * Adding two signed integers can overflow only if they have the same
- * sign, and overflow has happened iff the result has the opposite
- * sign.
- */
-#define __signed_add_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = (u64)__a + (u64)__b; \
- (((~(__a ^ __b)) & (*__d ^ __a)) \
- & type_min(typeof(__a))) != 0; \
-})
-
-/*
- * Subtraction is similar, except that overflow can now happen only
- * when the signs are opposite. In this case, overflow has happened if
- * the result has the opposite sign of a.
- */
-#define __signed_sub_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = (u64)__a - (u64)__b; \
- ((((__a ^ __b)) & (*__d ^ __a)) \
- & type_min(typeof(__a))) != 0; \
-})
-
-/*
- * Signed multiplication is rather hard. gcc always follows C99, so
- * division is truncated towards 0. This means that we can write the
- * overflow check like this:
- *
- * (a > 0 && (b > MAX/a || b < MIN/a)) ||
- * (a < -1 && (b > MIN/a || b < MAX/a) ||
- * (a == -1 && b == MIN)
- *
- * The redundant casts of -1 are to silence an annoying -Wtype-limits
- * (included in -Wextra) warning: When the type is u8 or u16, the
- * __b_c_e in check_mul_overflow obviously selects
- * __unsigned_mul_overflow, but unfortunately gcc still parses this
- * code and warns about the limited range of __b.
- */
-
-#define __signed_mul_overflow(a, b, d) ({ \
- typeof(a) __a = (a); \
- typeof(b) __b = (b); \
- typeof(d) __d = (d); \
- typeof(a) __tmax = type_max(typeof(a)); \
- typeof(a) __tmin = type_min(typeof(a)); \
- (void) (&__a == &__b); \
- (void) (&__a == __d); \
- *__d = (u64)__a * (u64)__b; \
- (__b > 0 && (__a > __tmax/__b || __a < __tmin/__b)) || \
- (__b < (typeof(__b))-1 && (__a > __tmin/__b || __a < __tmax/__b)) || \
- (__b == (typeof(__b))-1 && __a == __tmin); \
-})
-
-
-#define check_add_overflow(a, b, d) \
- __builtin_choose_expr(is_signed_type(typeof(a)), \
- __signed_add_overflow(a, b, d), \
- __unsigned_add_overflow(a, b, d))
-
-#define check_sub_overflow(a, b, d) \
- __builtin_choose_expr(is_signed_type(typeof(a)), \
- __signed_sub_overflow(a, b, d), \
- __unsigned_sub_overflow(a, b, d))
-
-#define check_mul_overflow(a, b, d) \
- __builtin_choose_expr(is_signed_type(typeof(a)), \
- __signed_mul_overflow(a, b, d), \
- __unsigned_mul_overflow(a, b, d))
-
-
-#endif /* COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW */
-
/**
* array_size() - Calculate size of 2-dimensional array.
*
free(evsel);
}
-#define FD(e, x, y) (*(int *) xyarray__entry(e->fd, x, y))
+#define FD(e, x, y) ((int *) xyarray__entry(e->fd, x, y))
#define MMAP(e, x, y) (e->mmap ? ((struct perf_mmap *) xyarray__entry(e->mmap, x, y)) : NULL)
int perf_evsel__alloc_fd(struct perf_evsel *evsel, int ncpus, int nthreads)
int cpu, thread;
for (cpu = 0; cpu < ncpus; cpu++) {
for (thread = 0; thread < nthreads; thread++) {
- FD(evsel, cpu, thread) = -1;
+ int *fd = FD(evsel, cpu, thread);
+
+ if (fd)
+ *fd = -1;
}
}
}
static int get_group_fd(struct perf_evsel *evsel, int cpu, int thread, int *group_fd)
{
struct perf_evsel *leader = evsel->leader;
- int fd;
+ int *fd;
if (evsel == leader) {
*group_fd = -1;
return -ENOTCONN;
fd = FD(leader, cpu, thread);
- if (fd == -1)
+ if (fd == NULL || *fd == -1)
return -EBADF;
- *group_fd = fd;
+ *group_fd = *fd;
return 0;
}
for (cpu = 0; cpu < cpus->nr; cpu++) {
for (thread = 0; thread < threads->nr; thread++) {
- int fd, group_fd;
+ int fd, group_fd, *evsel_fd;
+
+ evsel_fd = FD(evsel, cpu, thread);
+ if (evsel_fd == NULL)
+ return -EINVAL;
err = get_group_fd(evsel, cpu, thread, &group_fd);
if (err < 0)
if (fd < 0)
return -errno;
- FD(evsel, cpu, thread) = fd;
+ *evsel_fd = fd;
}
}
int thread;
for (thread = 0; thread < xyarray__max_y(evsel->fd); ++thread) {
- if (FD(evsel, cpu, thread) >= 0)
- close(FD(evsel, cpu, thread));
- FD(evsel, cpu, thread) = -1;
+ int *fd = FD(evsel, cpu, thread);
+
+ if (fd && *fd >= 0) {
+ close(*fd);
+ *fd = -1;
+ }
}
}
for (cpu = 0; cpu < xyarray__max_x(evsel->fd); cpu++) {
for (thread = 0; thread < xyarray__max_y(evsel->fd); thread++) {
- int fd = FD(evsel, cpu, thread);
- struct perf_mmap *map = MMAP(evsel, cpu, thread);
+ int *fd = FD(evsel, cpu, thread);
- if (fd < 0)
+ if (fd == NULL || *fd < 0)
continue;
- perf_mmap__munmap(map);
+ perf_mmap__munmap(MMAP(evsel, cpu, thread));
}
}
for (cpu = 0; cpu < xyarray__max_x(evsel->fd); cpu++) {
for (thread = 0; thread < xyarray__max_y(evsel->fd); thread++) {
- int fd = FD(evsel, cpu, thread);
- struct perf_mmap *map = MMAP(evsel, cpu, thread);
+ int *fd = FD(evsel, cpu, thread);
+ struct perf_mmap *map;
- if (fd < 0)
+ if (fd == NULL || *fd < 0)
continue;
+ map = MMAP(evsel, cpu, thread);
perf_mmap__init(map, NULL, false, NULL);
- ret = perf_mmap__mmap(map, &mp, fd, cpu);
+ ret = perf_mmap__mmap(map, &mp, *fd, cpu);
if (ret) {
perf_evsel__munmap(evsel);
return ret;
void *perf_evsel__mmap_base(struct perf_evsel *evsel, int cpu, int thread)
{
- if (FD(evsel, cpu, thread) < 0 || MMAP(evsel, cpu, thread) == NULL)
+ int *fd = FD(evsel, cpu, thread);
+
+ if (fd == NULL || *fd < 0 || MMAP(evsel, cpu, thread) == NULL)
return NULL;
return MMAP(evsel, cpu, thread)->base;
struct perf_counts_values *count)
{
size_t size = perf_evsel__read_size(evsel);
+ int *fd = FD(evsel, cpu, thread);
memset(count, 0, sizeof(*count));
- if (FD(evsel, cpu, thread) < 0)
+ if (fd == NULL || *fd < 0)
return -EINVAL;
if (MMAP(evsel, cpu, thread) &&
!perf_mmap__read_self(MMAP(evsel, cpu, thread), count))
return 0;
- if (readn(FD(evsel, cpu, thread), count->values, size) <= 0)
+ if (readn(*fd, count->values, size) <= 0)
return -errno;
return 0;
int thread;
for (thread = 0; thread < xyarray__max_y(evsel->fd); thread++) {
- int fd = FD(evsel, cpu, thread),
- err = ioctl(fd, ioc, arg);
+ int err;
+ int *fd = FD(evsel, cpu, thread);
+
+ if (fd == NULL || *fd < 0)
+ return -1;
+
+ err = ioctl(*fd, ioc, arg);
if (err)
return err;
return OUTPUT_TYPE_OTHER;
}
-static inline unsigned int attr_type(unsigned int type)
-{
- switch (type) {
- case OUTPUT_TYPE_SYNTH:
- return PERF_TYPE_SYNTH;
- default:
- return type;
- }
-}
-
static bool output_set_by_user(void)
{
int j;
output[type].print_ip_opts |= EVSEL__PRINT_SRCLINE;
}
+static struct evsel *find_first_output_type(struct evlist *evlist,
+ unsigned int type)
+{
+ struct evsel *evsel;
+
+ evlist__for_each_entry(evlist, evsel) {
+ if (output_type(evsel->core.attr.type) == (int)type)
+ return evsel;
+ }
+ return NULL;
+}
+
/*
* verify all user requested events exist and the samples
* have the expected data
struct evsel *evsel;
for (j = 0; j < OUTPUT_TYPE_MAX; ++j) {
- evsel = perf_session__find_first_evtype(session, attr_type(j));
+ evsel = find_first_output_type(session->evlist, j);
/*
* even if fields is set to 0 (ie., show nothing) event must
}
void ui_browser__mark_fused(struct ui_browser *browser, unsigned int column,
- unsigned int row, bool arrow_down)
+ unsigned int row, int diff, bool arrow_down)
{
- unsigned int end_row;
+ int end_row;
- if (row >= browser->top_idx)
- end_row = row - browser->top_idx;
- else
+ if (diff <= 0)
return;
SLsmg_set_char_set(1);
if (arrow_down) {
+ if (row + diff <= browser->top_idx)
+ return;
+
+ end_row = row + diff - browser->top_idx;
ui_browser__gotorc(browser, end_row, column - 1);
- SLsmg_write_char(SLSMG_ULCORN_CHAR);
- ui_browser__gotorc(browser, end_row, column);
- SLsmg_draw_hline(2);
- ui_browser__gotorc(browser, end_row + 1, column - 1);
SLsmg_write_char(SLSMG_LTEE_CHAR);
+
+ while (--end_row >= 0 && end_row > (int)(row - browser->top_idx)) {
+ ui_browser__gotorc(browser, end_row, column - 1);
+ SLsmg_draw_vline(1);
+ }
+
+ end_row = (int)(row - browser->top_idx);
+ if (end_row >= 0) {
+ ui_browser__gotorc(browser, end_row, column - 1);
+ SLsmg_write_char(SLSMG_ULCORN_CHAR);
+ ui_browser__gotorc(browser, end_row, column);
+ SLsmg_draw_hline(2);
+ }
} else {
+ if (row < browser->top_idx)
+ return;
+
+ end_row = row - browser->top_idx;
ui_browser__gotorc(browser, end_row, column - 1);
SLsmg_write_char(SLSMG_LTEE_CHAR);
ui_browser__gotorc(browser, end_row, column);
void __ui_browser__line_arrow(struct ui_browser *browser, unsigned int column,
u64 start, u64 end);
void ui_browser__mark_fused(struct ui_browser *browser, unsigned int column,
- unsigned int row, bool arrow_down);
+ unsigned int row, int diff, bool arrow_down);
void __ui_browser__show_title(struct ui_browser *browser, const char *title);
void ui_browser__show_title(struct ui_browser *browser, const char *title);
int ui_browser__show(struct ui_browser *browser, const char *title,
ab->selection = al;
}
-static bool is_fused(struct annotate_browser *ab, struct disasm_line *cursor)
+static int is_fused(struct annotate_browser *ab, struct disasm_line *cursor)
{
struct disasm_line *pos = list_prev_entry(cursor, al.node);
const char *name;
+ int diff = 1;
+
+ while (pos && pos->al.offset == -1) {
+ pos = list_prev_entry(pos, al.node);
+ if (!ab->opts->hide_src_code)
+ diff++;
+ }
if (!pos)
- return false;
+ return 0;
if (ins__is_lock(&pos->ins))
name = pos->ops.locked.ins.name;
name = pos->ins.name;
if (!name || !cursor->ins.name)
- return false;
+ return 0;
- return ins__is_fused(ab->arch, name, cursor->ins.name);
+ if (ins__is_fused(ab->arch, name, cursor->ins.name))
+ return diff;
+ return 0;
}
static void annotate_browser__draw_current_jump(struct ui_browser *browser)
struct annotation *notes = symbol__annotation(sym);
u8 pcnt_width = annotation__pcnt_width(notes);
int width;
+ int diff = 0;
/* PLT symbols contain external offsets */
if (strstr(sym->name, "@plt"))
pcnt_width + 2 + notes->widths.addr + width,
from, to);
- if (is_fused(ab, cursor)) {
+ diff = is_fused(ab, cursor);
+ if (diff > 0) {
ui_browser__mark_fused(browser,
pcnt_width + 3 + notes->widths.addr + width,
- from - 1,
- to > from);
+ from - diff, diff, to > from);
}
}
struct btf * __weak btf__load_from_kernel_by_id(__u32 id)
{
struct btf *btf;
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
int err = btf__get_from_id(id, &btf);
+#pragma GCC diagnostic pop
return err ? ERR_PTR(err) : btf;
}
al.filtered = 0;
al.sym = NULL;
+ al.srcline = NULL;
if (!cpumode) {
thread__find_cpumode_addr_location(thread, ip, &al);
} else {
td->feats_supported |= FEAT_SSBS;
if (getauxval(AT_HWCAP) & HWCAP_SVE)
td->feats_supported |= FEAT_SVE;
- if (feats_ok(td))
+ if (feats_ok(td)) {
fprintf(stderr,
"Required Features: [%s] supported\n",
feats_to_string(td->feats_required &
td->feats_supported));
- else
+ } else {
fprintf(stderr,
"Required Features: [%s] NOT supported\n",
feats_to_string(td->feats_required &
~td->feats_supported));
+ td->result = KSFT_SKIP;
+ return 0;
+ }
}
/* Perform test specific additional initialization */
#include <unistd.h>
#include <ftw.h>
-
#include "cgroup_helpers.h"
/*
* To avoid relying on the system setup, when setup_cgroup_env is called
- * we create a new mount namespace, and cgroup namespace. The cgroup2
- * root is mounted at CGROUP_MOUNT_PATH
- *
- * Unfortunately, most people don't have cgroupv2 enabled at this point in time.
- * It's easier to create our own mount namespace and manage it ourselves.
+ * we create a new mount namespace, and cgroup namespace. The cgroupv2
+ * root is mounted at CGROUP_MOUNT_PATH. Unfortunately, most people don't
+ * have cgroupv2 enabled at this point in time. It's easier to create our
+ * own mount namespace and manage it ourselves. We assume /mnt exists.
*
- * We assume /mnt exists.
+ * Related cgroupv1 helpers are named *classid*(), since we only use the
+ * net_cls controller for tagging net_cls.classid. We assume the default
+ * mount under /sys/fs/cgroup/net_cls, which should be the case for the
+ * vast majority of users.
*/
#define WALK_FD_LIMIT 16
+
#define CGROUP_MOUNT_PATH "/mnt"
+#define CGROUP_MOUNT_DFLT "/sys/fs/cgroup"
+#define NETCLS_MOUNT_PATH CGROUP_MOUNT_DFLT "/net_cls"
#define CGROUP_WORK_DIR "/cgroup-test-work-dir"
+
#define format_cgroup_path(buf, path) \
snprintf(buf, sizeof(buf), "%s%s%s", CGROUP_MOUNT_PATH, \
CGROUP_WORK_DIR, path)
+#define format_classid_path(buf) \
+ snprintf(buf, sizeof(buf), "%s%s", NETCLS_MOUNT_PATH, \
+ CGROUP_WORK_DIR)
+
/**
* enable_all_controllers() - Enable all available cgroup v2 controllers
*
return 0;
}
-
-static int join_cgroup_from_top(char *cgroup_path)
+static int join_cgroup_from_top(const char *cgroup_path)
{
char cgroup_procs_path[PATH_MAX + 1];
pid_t pid = getpid();
}
return cg_fd;
}
+
+/**
+ * setup_classid_environment() - Setup the cgroupv1 net_cls environment
+ *
+ * After calling this function, cleanup_classid_environment should be called
+ * once testing is complete.
+ *
+ * This function will print an error to stderr and return 1 if it is unable
+ * to setup the cgroup environment. If setup is successful, 0 is returned.
+ */
+int setup_classid_environment(void)
+{
+ char cgroup_workdir[PATH_MAX + 1];
+
+ format_classid_path(cgroup_workdir);
+
+ if (mount("tmpfs", CGROUP_MOUNT_DFLT, "tmpfs", 0, NULL) &&
+ errno != EBUSY) {
+ log_err("mount cgroup base");
+ return 1;
+ }
+
+ if (mkdir(NETCLS_MOUNT_PATH, 0777) && errno != EEXIST) {
+ log_err("mkdir cgroup net_cls");
+ return 1;
+ }
+
+ if (mount("net_cls", NETCLS_MOUNT_PATH, "cgroup", 0, "net_cls") &&
+ errno != EBUSY) {
+ log_err("mount cgroup net_cls");
+ return 1;
+ }
+
+ cleanup_classid_environment();
+
+ if (mkdir(cgroup_workdir, 0777) && errno != EEXIST) {
+ log_err("mkdir cgroup work dir");
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * set_classid() - Set a cgroupv1 net_cls classid
+ * @id: the numeric classid
+ *
+ * Writes the passed classid into the cgroup work dir's net_cls.classid
+ * file in order to later on trigger socket tagging.
+ *
+ * On success, it returns 0, otherwise on failure it returns 1. If there
+ * is a failure, it prints the error to stderr.
+ */
+int set_classid(unsigned int id)
+{
+ char cgroup_workdir[PATH_MAX - 42];
+ char cgroup_classid_path[PATH_MAX + 1];
+ int fd, rc = 0;
+
+ format_classid_path(cgroup_workdir);
+ snprintf(cgroup_classid_path, sizeof(cgroup_classid_path),
+ "%s/net_cls.classid", cgroup_workdir);
+
+ fd = open(cgroup_classid_path, O_WRONLY);
+ if (fd < 0) {
+ log_err("Opening cgroup classid: %s", cgroup_classid_path);
+ return 1;
+ }
+
+ if (dprintf(fd, "%u\n", id) < 0) {
+ log_err("Setting cgroup classid");
+ rc = 1;
+ }
+
+ close(fd);
+ return rc;
+}
+
+/**
+ * join_classid() - Join a cgroupv1 net_cls classid
+ *
+ * This function expects the cgroup work dir to be already created, as we
+ * join it here. This causes the process sockets to be tagged with the given
+ * net_cls classid.
+ *
+ * On success, it returns 0, otherwise on failure it returns 1.
+ */
+int join_classid(void)
+{
+ char cgroup_workdir[PATH_MAX + 1];
+
+ format_classid_path(cgroup_workdir);
+ return join_cgroup_from_top(cgroup_workdir);
+}
+
+/**
+ * cleanup_classid_environment() - Cleanup the cgroupv1 net_cls environment
+ *
+ * At call time, it moves the calling process to the root cgroup, and then
+ * runs the deletion process.
+ *
+ * On failure, it will print an error to stderr, and try to continue.
+ */
+void cleanup_classid_environment(void)
+{
+ char cgroup_workdir[PATH_MAX + 1];
+
+ format_classid_path(cgroup_workdir);
+ join_cgroup_from_top(NETCLS_MOUNT_PATH);
+ nftw(cgroup_workdir, nftwfunc, WALK_FD_LIMIT, FTW_DEPTH | FTW_MOUNT);
+}
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __CGROUP_HELPERS_H
#define __CGROUP_HELPERS_H
+
#include <errno.h>
#include <string.h>
#define log_err(MSG, ...) fprintf(stderr, "(%s:%d: errno: %s) " MSG "\n", \
__FILE__, __LINE__, clean_errno(), ##__VA_ARGS__)
-
+/* cgroupv2 related */
int cgroup_setup_and_join(const char *path);
int create_and_get_cgroup(const char *path);
+unsigned long long get_cgroup_id(const char *path);
+
int join_cgroup(const char *path);
+
int setup_cgroup_environment(void);
void cleanup_cgroup_environment(void);
-unsigned long long get_cgroup_id(const char *path);
-#endif
+/* cgroupv1 related */
+int set_classid(unsigned int id);
+int join_classid(void);
+
+int setup_classid_environment(void);
+void cleanup_classid_environment(void);
+
+#endif /* __CGROUP_HELPERS_H */
static int connect_fd_to_addr(int fd,
const struct sockaddr_storage *addr,
- socklen_t addrlen)
+ socklen_t addrlen, const bool must_fail)
{
- if (connect(fd, (const struct sockaddr *)addr, addrlen)) {
- log_err("Failed to connect to server");
- return -1;
+ int ret;
+
+ errno = 0;
+ ret = connect(fd, (const struct sockaddr *)addr, addrlen);
+ if (must_fail) {
+ if (!ret) {
+ log_err("Unexpected success to connect to server");
+ return -1;
+ }
+ if (errno != EPERM) {
+ log_err("Unexpected error from connect to server");
+ return -1;
+ }
+ } else {
+ if (ret) {
+ log_err("Failed to connect to server");
+ return -1;
+ }
}
return 0;
strlen(opts->cc) + 1))
goto error_close;
- if (connect_fd_to_addr(fd, &addr, addrlen))
+ if (connect_fd_to_addr(fd, &addr, addrlen, opts->must_fail))
goto error_close;
return fd;
return -1;
}
- if (connect_fd_to_addr(client_fd, &addr, len))
+ if (connect_fd_to_addr(client_fd, &addr, len, false))
return -1;
return 0;
struct network_helper_opts {
const char *cc;
int timeout_ms;
+ bool must_fail;
};
/* ipv4 test vector */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <test_progs.h>
+
+#include "connect4_dropper.skel.h"
+
+#include "cgroup_helpers.h"
+#include "network_helpers.h"
+
+static int run_test(int cgroup_fd, int server_fd, bool classid)
+{
+ struct network_helper_opts opts = {
+ .must_fail = true,
+ };
+ struct connect4_dropper *skel;
+ int fd, err = 0;
+
+ skel = connect4_dropper__open_and_load();
+ if (!ASSERT_OK_PTR(skel, "skel_open"))
+ return -1;
+
+ skel->links.connect_v4_dropper =
+ bpf_program__attach_cgroup(skel->progs.connect_v4_dropper,
+ cgroup_fd);
+ if (!ASSERT_OK_PTR(skel->links.connect_v4_dropper, "prog_attach")) {
+ err = -1;
+ goto out;
+ }
+
+ if (classid && !ASSERT_OK(join_classid(), "join_classid")) {
+ err = -1;
+ goto out;
+ }
+
+ fd = connect_to_fd_opts(server_fd, &opts);
+ if (fd < 0)
+ err = -1;
+ else
+ close(fd);
+out:
+ connect4_dropper__destroy(skel);
+ return err;
+}
+
+void test_cgroup_v1v2(void)
+{
+ struct network_helper_opts opts = {};
+ int server_fd, client_fd, cgroup_fd;
+ static const int port = 60123;
+
+ /* Step 1: Check base connectivity works without any BPF. */
+ server_fd = start_server(AF_INET, SOCK_STREAM, NULL, port, 0);
+ if (!ASSERT_GE(server_fd, 0, "server_fd"))
+ return;
+ client_fd = connect_to_fd_opts(server_fd, &opts);
+ if (!ASSERT_GE(client_fd, 0, "client_fd")) {
+ close(server_fd);
+ return;
+ }
+ close(client_fd);
+ close(server_fd);
+
+ /* Step 2: Check BPF policy prog attached to cgroups drops connectivity. */
+ cgroup_fd = test__join_cgroup("/connect_dropper");
+ if (!ASSERT_GE(cgroup_fd, 0, "cgroup_fd"))
+ return;
+ server_fd = start_server(AF_INET, SOCK_STREAM, NULL, port, 0);
+ if (!ASSERT_GE(server_fd, 0, "server_fd")) {
+ close(cgroup_fd);
+ return;
+ }
+ ASSERT_OK(run_test(cgroup_fd, server_fd, false), "cgroup-v2-only");
+ setup_classid_environment();
+ set_classid(42);
+ ASSERT_OK(run_test(cgroup_fd, server_fd, true), "cgroup-v1v2");
+ cleanup_classid_environment();
+ close(server_fd);
+ close(cgroup_fd);
+}
// SPDX-License-Identifier: GPL-2.0
#define _GNU_SOURCE
#include <test_progs.h>
-#include <linux/ptrace.h>
#include "test_task_pt_regs.skel.h"
void test_task_pt_regs(void)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <string.h>
+
+#include <linux/stddef.h>
+#include <linux/bpf.h>
+
+#include <sys/socket.h>
+
+#include <bpf/bpf_helpers.h>
+#include <bpf/bpf_endian.h>
+
+#define VERDICT_REJECT 0
+#define VERDICT_PROCEED 1
+
+SEC("cgroup/connect4")
+int connect_v4_dropper(struct bpf_sock_addr *ctx)
+{
+ if (ctx->type != SOCK_STREAM)
+ return VERDICT_PROCEED;
+ if (ctx->user_port == bpf_htons(60123))
+ return VERDICT_REJECT;
+ return VERDICT_PROCEED;
+}
+
+char _license[] SEC("license") = "GPL";
// SPDX-License-Identifier: GPL-2.0
-#include <linux/ptrace.h>
-#include <linux/bpf.h>
+#include "vmlinux.h"
#include <bpf/bpf_helpers.h>
#include <bpf/bpf_tracing.h>
-struct pt_regs current_regs = {};
-struct pt_regs ctx_regs = {};
+#define PT_REGS_SIZE sizeof(struct pt_regs)
+
+/*
+ * The kernel struct pt_regs isn't exported in its entirety to userspace.
+ * Pass it as an array to task_pt_regs.c
+ */
+char current_regs[PT_REGS_SIZE] = {};
+char ctx_regs[PT_REGS_SIZE] = {};
int uprobe_res = 0;
SEC("uprobe/trigger_func")
current = bpf_get_current_task_btf();
regs = (struct pt_regs *) bpf_task_pt_regs(current);
- __builtin_memcpy(¤t_regs, regs, sizeof(*regs));
- __builtin_memcpy(&ctx_regs, ctx, sizeof(*ctx));
+ if (bpf_probe_read_kernel(current_regs, PT_REGS_SIZE, regs))
+ return 0;
+ if (bpf_probe_read_kernel(ctx_regs, PT_REGS_SIZE, ctx))
+ return 0;
/* Prove that uprobe was run */
uprobe_res = 1;
#!/bin/bash
# SPDX-License-Identifier: GPL-2.0
-# Copyright 2020 NXP Semiconductors
+# Copyright 2020 NXP
WAIT_TIME=1
NUM_NETIFS=4
/kvm_page_table_test
/memslot_modification_stress_test
/memslot_perf_test
+/rseq_test
/set_memory_region_test
/steal_time
/kvm_binary_stats_test
TEST_GEN_PROGS_x86_64 += kvm_page_table_test
TEST_GEN_PROGS_x86_64 += memslot_modification_stress_test
TEST_GEN_PROGS_x86_64 += memslot_perf_test
+TEST_GEN_PROGS_x86_64 += rseq_test
TEST_GEN_PROGS_x86_64 += set_memory_region_test
TEST_GEN_PROGS_x86_64 += steal_time
TEST_GEN_PROGS_x86_64 += kvm_binary_stats_test
TEST_GEN_PROGS_aarch64 += dirty_log_perf_test
TEST_GEN_PROGS_aarch64 += kvm_create_max_vcpus
TEST_GEN_PROGS_aarch64 += kvm_page_table_test
+TEST_GEN_PROGS_aarch64 += rseq_test
TEST_GEN_PROGS_aarch64 += set_memory_region_test
TEST_GEN_PROGS_aarch64 += steal_time
TEST_GEN_PROGS_aarch64 += kvm_binary_stats_test
TEST_GEN_PROGS_s390x += dirty_log_test
TEST_GEN_PROGS_s390x += kvm_create_max_vcpus
TEST_GEN_PROGS_s390x += kvm_page_table_test
+TEST_GEN_PROGS_s390x += rseq_test
TEST_GEN_PROGS_s390x += set_memory_region_test
TEST_GEN_PROGS_s390x += kvm_binary_stats_test
uint32_t flag;
};
+#define MIN_RUN_DELAY_NS 200000UL
+
bool thp_configured(void);
size_t get_trans_hugepagesz(void);
size_t get_def_hugetlb_pagesz(void);
size_t get_backing_src_pagesz(uint32_t i);
void backing_src_help(void);
enum vm_mem_backing_src_type parse_backing_src_type(const char *type_name);
+long get_run_delay(void);
/*
* Whether or not the given source type is shared memory (as opposed to
#include <stdlib.h>
#include <time.h>
#include <sys/stat.h>
+#include <sys/syscall.h>
#include <linux/mman.h>
#include "linux/kernel.h"
{
size_t size;
FILE *f;
+ int ret;
TEST_ASSERT(thp_configured(), "THP is not configured in host kernel");
f = fopen("/sys/kernel/mm/transparent_hugepage/hpage_pmd_size", "r");
TEST_ASSERT(f != NULL, "Error in opening transparent_hugepage/hpage_pmd_size");
- fscanf(f, "%ld", &size);
+ ret = fscanf(f, "%ld", &size);
+ ret = fscanf(f, "%ld", &size);
+ TEST_ASSERT(ret < 1, "Error reading transparent_hugepage/hpage_pmd_size");
fclose(f);
return size;
TEST_FAIL("Unknown backing src type: %s", type_name);
return -1;
}
+
+long get_run_delay(void)
+{
+ char path[64];
+ long val[2];
+ FILE *fp;
+
+ sprintf(path, "/proc/%ld/schedstat", syscall(SYS_gettid));
+ fp = fopen(path, "r");
+ /* Return MIN_RUN_DELAY_NS upon failure just to be safe */
+ if (fscanf(fp, "%ld %ld ", &val[0], &val[1]) < 2)
+ val[1] = MIN_RUN_DELAY_NS;
+ fclose(fp);
+
+ return val[1];
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+#define _GNU_SOURCE /* for program_invocation_short_name */
+#include <errno.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <sched.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <signal.h>
+#include <syscall.h>
+#include <sys/ioctl.h>
+#include <asm/barrier.h>
+#include <linux/atomic.h>
+#include <linux/rseq.h>
+#include <linux/unistd.h>
+
+#include "kvm_util.h"
+#include "processor.h"
+#include "test_util.h"
+
+#define VCPU_ID 0
+
+static __thread volatile struct rseq __rseq = {
+ .cpu_id = RSEQ_CPU_ID_UNINITIALIZED,
+};
+
+/*
+ * Use an arbitrary, bogus signature for configuring rseq, this test does not
+ * actually enter an rseq critical section.
+ */
+#define RSEQ_SIG 0xdeadbeef
+
+/*
+ * Any bug related to task migration is likely to be timing-dependent; perform
+ * a large number of migrations to reduce the odds of a false negative.
+ */
+#define NR_TASK_MIGRATIONS 100000
+
+static pthread_t migration_thread;
+static cpu_set_t possible_mask;
+static bool done;
+
+static atomic_t seq_cnt;
+
+static void guest_code(void)
+{
+ for (;;)
+ GUEST_SYNC(0);
+}
+
+static void sys_rseq(int flags)
+{
+ int r;
+
+ r = syscall(__NR_rseq, &__rseq, sizeof(__rseq), flags, RSEQ_SIG);
+ TEST_ASSERT(!r, "rseq failed, errno = %d (%s)", errno, strerror(errno));
+}
+
+static void *migration_worker(void *ign)
+{
+ cpu_set_t allowed_mask;
+ int r, i, nr_cpus, cpu;
+
+ CPU_ZERO(&allowed_mask);
+
+ nr_cpus = CPU_COUNT(&possible_mask);
+
+ for (i = 0; i < NR_TASK_MIGRATIONS; i++) {
+ cpu = i % nr_cpus;
+ if (!CPU_ISSET(cpu, &possible_mask))
+ continue;
+
+ CPU_SET(cpu, &allowed_mask);
+
+ /*
+ * Bump the sequence count twice to allow the reader to detect
+ * that a migration may have occurred in between rseq and sched
+ * CPU ID reads. An odd sequence count indicates a migration
+ * is in-progress, while a completely different count indicates
+ * a migration occurred since the count was last read.
+ */
+ atomic_inc(&seq_cnt);
+
+ /*
+ * Ensure the odd count is visible while sched_getcpu() isn't
+ * stable, i.e. while changing affinity is in-progress.
+ */
+ smp_wmb();
+ r = sched_setaffinity(0, sizeof(allowed_mask), &allowed_mask);
+ TEST_ASSERT(!r, "sched_setaffinity failed, errno = %d (%s)",
+ errno, strerror(errno));
+ smp_wmb();
+ atomic_inc(&seq_cnt);
+
+ CPU_CLR(cpu, &allowed_mask);
+
+ /*
+ * Wait 1-10us before proceeding to the next iteration and more
+ * specifically, before bumping seq_cnt again. A delay is
+ * needed on three fronts:
+ *
+ * 1. To allow sched_setaffinity() to prompt migration before
+ * ioctl(KVM_RUN) enters the guest so that TIF_NOTIFY_RESUME
+ * (or TIF_NEED_RESCHED, which indirectly leads to handling
+ * NOTIFY_RESUME) is handled in KVM context.
+ *
+ * If NOTIFY_RESUME/NEED_RESCHED is set after KVM enters
+ * the guest, the guest will trigger a IO/MMIO exit all the
+ * way to userspace and the TIF flags will be handled by
+ * the generic "exit to userspace" logic, not by KVM. The
+ * exit to userspace is necessary to give the test a chance
+ * to check the rseq CPU ID (see #2).
+ *
+ * Alternatively, guest_code() could include an instruction
+ * to trigger an exit that is handled by KVM, but any such
+ * exit requires architecture specific code.
+ *
+ * 2. To let ioctl(KVM_RUN) make its way back to the test
+ * before the next round of migration. The test's check on
+ * the rseq CPU ID must wait for migration to complete in
+ * order to avoid false positive, thus any kernel rseq bug
+ * will be missed if the next migration starts before the
+ * check completes.
+ *
+ * 3. To ensure the read-side makes efficient forward progress,
+ * e.g. if sched_getcpu() involves a syscall. Stalling the
+ * read-side means the test will spend more time waiting for
+ * sched_getcpu() to stabilize and less time trying to hit
+ * the timing-dependent bug.
+ *
+ * Because any bug in this area is likely to be timing-dependent,
+ * run with a range of delays at 1us intervals from 1us to 10us
+ * as a best effort to avoid tuning the test to the point where
+ * it can hit _only_ the original bug and not detect future
+ * regressions.
+ *
+ * The original bug can reproduce with a delay up to ~500us on
+ * x86-64, but starts to require more iterations to reproduce
+ * as the delay creeps above ~10us, and the average runtime of
+ * each iteration obviously increases as well. Cap the delay
+ * at 10us to keep test runtime reasonable while minimizing
+ * potential coverage loss.
+ *
+ * The lower bound for reproducing the bug is likely below 1us,
+ * e.g. failures occur on x86-64 with nanosleep(0), but at that
+ * point the overhead of the syscall likely dominates the delay.
+ * Use usleep() for simplicity and to avoid unnecessary kernel
+ * dependencies.
+ */
+ usleep((i % 10) + 1);
+ }
+ done = true;
+ return NULL;
+}
+
+int main(int argc, char *argv[])
+{
+ int r, i, snapshot;
+ struct kvm_vm *vm;
+ u32 cpu, rseq_cpu;
+
+ /* Tell stdout not to buffer its content */
+ setbuf(stdout, NULL);
+
+ r = sched_getaffinity(0, sizeof(possible_mask), &possible_mask);
+ TEST_ASSERT(!r, "sched_getaffinity failed, errno = %d (%s)", errno,
+ strerror(errno));
+
+ if (CPU_COUNT(&possible_mask) < 2) {
+ print_skip("Only one CPU, task migration not possible\n");
+ exit(KSFT_SKIP);
+ }
+
+ sys_rseq(0);
+
+ /*
+ * Create and run a dummy VM that immediately exits to userspace via
+ * GUEST_SYNC, while concurrently migrating the process by setting its
+ * CPU affinity.
+ */
+ vm = vm_create_default(VCPU_ID, 0, guest_code);
+
+ pthread_create(&migration_thread, NULL, migration_worker, 0);
+
+ for (i = 0; !done; i++) {
+ vcpu_run(vm, VCPU_ID);
+ TEST_ASSERT(get_ucall(vm, VCPU_ID, NULL) == UCALL_SYNC,
+ "Guest failed?");
+
+ /*
+ * Verify rseq's CPU matches sched's CPU. Ensure migration
+ * doesn't occur between sched_getcpu() and reading the rseq
+ * cpu_id by rereading both if the sequence count changes, or
+ * if the count is odd (migration in-progress).
+ */
+ do {
+ /*
+ * Drop bit 0 to force a mismatch if the count is odd,
+ * i.e. if a migration is in-progress.
+ */
+ snapshot = atomic_read(&seq_cnt) & ~1;
+
+ /*
+ * Ensure reading sched_getcpu() and rseq.cpu_id
+ * complete in a single "no migration" window, i.e. are
+ * not reordered across the seq_cnt reads.
+ */
+ smp_rmb();
+ cpu = sched_getcpu();
+ rseq_cpu = READ_ONCE(__rseq.cpu_id);
+ smp_rmb();
+ } while (snapshot != atomic_read(&seq_cnt));
+
+ TEST_ASSERT(rseq_cpu == cpu,
+ "rseq CPU = %d, sched CPU = %d\n", rseq_cpu, cpu);
+ }
+
+ /*
+ * Sanity check that the test was able to enter the guest a reasonable
+ * number of times, e.g. didn't get stalled too often/long waiting for
+ * sched_getcpu() to stabilize. A 2:1 migration:KVM_RUN ratio is a
+ * fairly conservative ratio on x86-64, which can do _more_ KVM_RUNs
+ * than migrations given the 1us+ delay in the migration task.
+ */
+ TEST_ASSERT(i > (NR_TASK_MIGRATIONS / 2),
+ "Only performed %d KVM_RUNs, task stalled too much?\n", i);
+
+ pthread_join(migration_thread, NULL);
+
+ kvm_vm_free(vm);
+
+ sys_rseq(RSEQ_FLAG_UNREGISTER);
+
+ return 0;
+}
#include <sched.h>
#include <pthread.h>
#include <linux/kernel.h>
-#include <sys/syscall.h>
#include <asm/kvm.h>
#include <asm/kvm_para.h>
#define NR_VCPUS 4
#define ST_GPA_BASE (1 << 30)
-#define MIN_RUN_DELAY_NS 200000UL
static void *st_gva[NR_VCPUS];
static uint64_t guest_stolen_time[NR_VCPUS];
#endif
-static long get_run_delay(void)
-{
- char path[64];
- long val[2];
- FILE *fp;
-
- sprintf(path, "/proc/%ld/schedstat", syscall(SYS_gettid));
- fp = fopen(path, "r");
- fscanf(fp, "%ld %ld ", &val[0], &val[1]);
- fclose(fp);
-
- return val[1];
-}
-
static void *do_steal_time(void *arg)
{
struct timespec ts, stop;
FILE *f;
f = popen("dmesg | grep \"WARNING:\" | wc -l", "r");
- fscanf(f, "%d", &warnings);
+ if (fscanf(f, "%d", &warnings) < 1)
+ warnings = 0;
fclose(f);
return warnings;
#include <stdint.h>
#include <time.h>
#include <sched.h>
-#include <sys/syscall.h>
#define VCPU_ID 5
GUEST_DONE();
}
-static long get_run_delay(void)
-{
- char path[64];
- long val[2];
- FILE *fp;
-
- sprintf(path, "/proc/%ld/schedstat", syscall(SYS_gettid));
- fp = fopen(path, "r");
- fscanf(fp, "%ld %ld ", &val[0], &val[1]);
- fclose(fp);
-
- return val[1];
-}
-
static int cmp_timespec(struct timespec *a, struct timespec *b)
{
if (a->tv_sec > b->tv_sec)
# When local build is done, headers are installed in the default
# INSTALL_HDR_PATH usr/include.
.PHONY: khdr
+.NOTPARALLEL:
khdr:
ifndef KSFT_KHDR_INSTALL_DONE
ifeq (1,$(DEFAULT_INSTALL_HDR_PATH))
const __u8 *rsp, __u32 rsp_len)
{
char buf[256];
- unsigned int len;
+ int len;
send(nfc_sock, &cmd[3], cmd_len - 3, 0);
len = read(virtual_fd, buf, cmd_len);
-##TEST_GEN_FILES := test_unix_oob
-TEST_PROGS := test_unix_oob
+TEST_GEN_PROGS := test_unix_oob
include ../../lib.mk
-
-all: $(TEST_PROGS)
read_oob(pfd, &oob);
if (!signal_recvd || len != 127 || oob != '%' || atmark != 1) {
- fprintf(stderr, "Test 3 failed, sigurg %d len %d OOB %c ",
- "atmark %d\n", signal_recvd, len, oob, atmark);
+ fprintf(stderr,
+ "Test 3 failed, sigurg %d len %d OOB %c atmark %d\n",
+ signal_recvd, len, oob, atmark);
die(1);
}
check_err $? "Got unexpected long alternative name from link show JSON"
ip link property del $DUMMY_DEV altname $SHORT_NAME
- check_err $? "Failed to add short alternative name"
+ check_err $? "Failed to delete short alternative name"
ip -j -p link show $SHORT_NAME &>/dev/null
check_fail $? "Unexpected success while trying to do link show with deleted short alternative name"
/* SPDX-License-Identifier: GPL-2.0 */
-#include <ppc-asm.h>
+#include <basic_asm.h>
#include <asm/unistd.h>
.text
1:
li r3, -1
blr
+
+
+.macro scv level
+ .long (0x44000001 | (\level) << 5)
+.endm
+
+FUNC_START(getppid_scv_tm_active)
+ PUSH_BASIC_STACK(0)
+ tbegin.
+ beq 1f
+ li r0, __NR_getppid
+ scv 0
+ tend.
+ POP_BASIC_STACK(0)
+ blr
+1:
+ li r3, -1
+ POP_BASIC_STACK(0)
+ blr
+
+FUNC_START(getppid_scv_tm_suspended)
+ PUSH_BASIC_STACK(0)
+ tbegin.
+ beq 1f
+ li r0, __NR_getppid
+ tsuspend.
+ scv 0
+ tresume.
+ tend.
+ POP_BASIC_STACK(0)
+ blr
+1:
+ li r3, -1
+ POP_BASIC_STACK(0)
+ blr
#include "utils.h"
#include "tm.h"
+#ifndef PPC_FEATURE2_SCV
+#define PPC_FEATURE2_SCV 0x00100000 /* scv syscall */
+#endif
+
extern int getppid_tm_active(void);
extern int getppid_tm_suspended(void);
+extern int getppid_scv_tm_active(void);
+extern int getppid_scv_tm_suspended(void);
unsigned retries = 0;
#define TEST_DURATION 10 /* seconds */
-pid_t getppid_tm(bool suspend)
+pid_t getppid_tm(bool scv, bool suspend)
{
int i;
pid_t pid;
for (i = 0; i < TM_RETRIES; i++) {
- if (suspend)
- pid = getppid_tm_suspended();
- else
- pid = getppid_tm_active();
+ if (suspend) {
+ if (scv)
+ pid = getppid_scv_tm_suspended();
+ else
+ pid = getppid_tm_suspended();
+ } else {
+ if (scv)
+ pid = getppid_scv_tm_active();
+ else
+ pid = getppid_tm_active();
+ }
if (pid >= 0)
return pid;
* Test a syscall within a suspended transaction and verify
* that it succeeds.
*/
- FAIL_IF(getppid_tm(true) == -1); /* Should succeed. */
+ FAIL_IF(getppid_tm(false, true) == -1); /* Should succeed. */
/*
* Test a syscall within an active transaction and verify that
* it fails with the correct failure code.
*/
- FAIL_IF(getppid_tm(false) != -1); /* Should fail... */
+ FAIL_IF(getppid_tm(false, false) != -1); /* Should fail... */
FAIL_IF(!failure_is_persistent()); /* ...persistently... */
FAIL_IF(!failure_is_syscall()); /* ...with code syscall. */
+
+ /* Now do it all again with scv if it is available. */
+ if (have_hwcap2(PPC_FEATURE2_SCV)) {
+ FAIL_IF(getppid_tm(true, true) == -1); /* Should succeed. */
+ FAIL_IF(getppid_tm(true, false) != -1); /* Should fail... */
+ FAIL_IF(!failure_is_persistent()); /* ...persistently... */
+ FAIL_IF(!failure_is_syscall()); /* ...with code syscall. */
+ }
+
gettimeofday(&now, 0);
}
}
entry->ifnum = ifnum;
-
- /* FIXME update USBDEVFS_CONNECTINFO so it tells about high speed etc */
-
- fprintf(stderr, "%s speed\t%s\t%u\n",
- speed(entry->speed), entry->name, entry->ifnum);
-
entry->next = testdevs;
testdevs = entry;
return 0;
return 0;
}
+ status = ioctl(fd, USBDEVFS_GET_SPEED, NULL);
+ if (status < 0)
+ fprintf(stderr, "USBDEVFS_GET_SPEED failed %d\n", status);
+ else
+ dev->speed = status;
+ fprintf(stderr, "%s speed\t%s\t%u\n",
+ speed(dev->speed), dev->name, dev->ifnum);
+
restart:
for (i = 0; i < TEST_CASES; i++) {
if (dev->test != -1 && dev->test != i)
if (opt_list && opt_list_mapcnt)
kpagecount_fd = checked_open(PROC_KPAGECOUNT, O_RDONLY);
- if (opt_mark_idle && opt_file)
+ if (opt_mark_idle)
page_idle_fd = checked_open(SYS_KERNEL_MM_PAGE_IDLE, O_RDWR);
if (opt_list && opt_pid)
projects / platform / kernel / linux-starfive.git / commitdiff