[VE] fp32/64 fadd/fsub/fdiv/fmul isel patterns

Summary: fp32/64 fadd/fsub/fdiv/fmul isel patterns and tests.

Reviewers: arsenm, craig.topper, rengolin, k-ishizaka

Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D73540

diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 3bd50d3..81f9054 100644 (file)
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -368,6 +368,18 @@ multiclass RRNCm<string opcStr, bits<8>opc,
   RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
   RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
 
+// Used by fadd, fsub, and similar floating point instructions
+//   The order of operands are "$sx, $sy, $sz"
+
+multiclass RRFm<string opcStr, bits<8>opc,
+               RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2,
+               SDPatternOperator OpNode=null_frag> :
+  RRmrr<opcStr, opc, RC, Ty, RC, Ty, OpNode>,
+  RRmir<opcStr, opc, RC, Ty, RC, Ty, immOp, null_frag>,
+  RRmiz<opcStr, opc, RC, Ty, RC, Ty, immOp, null_frag>,
+  RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
+  RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
+
 // Multiclass for RR type instructions
 //   Used by sra, sla, sll, and similar instructions
 //   The order of operands are "$sx, $sz, $sy"
@@ -667,6 +679,26 @@ def : Pat<(i32 (srl i32:$src, i32:$val)),
             $src, sub_i32), 32), $val), sub_i32)>;
 
 // 5.3.2.5. Floating-point Arithmetic Operation Instructions
+let cx = 0 in
+defm FAD : RRFm<"fadd.d", 0x4C, I64, f64, simm7Op64, uimm6Op64, fadd>;
+let cx = 1 in
+defm FADS : RRFm<"fadd.s", 0x4C, F32, f32, simm7Op32, uimm6Op32, fadd>;
+
+let cx = 0 in
+defm FSB : RRFm<"fsub.d", 0x5C, I64, f64, simm7Op64, uimm6Op64, fsub>;
+let cx = 1 in
+defm FSBS : RRFm<"fsub.s", 0x5C, F32, f32, simm7Op32, uimm6Op32, fsub>;
+
+let cx = 0 in
+defm FMP : RRFm<"fmul.d", 0x4D, I64, f64, simm7Op64, uimm6Op64, fmul>;
+let cx = 1 in
+defm FMPS : RRFm<"fmul.s", 0x4D, F32, f32, simm7Op32, uimm6Op32, fmul>;
+
+let cx = 0 in
+defm FDV : RRFm<"fdiv.d", 0x5D, I64, f64, simm7Op64, uimm6Op64, fdiv>;
+let cx = 1 in
+defm FDVS : RRFm<"fdiv.s", 0x5D, F32, f32, simm7Op32, uimm6Op32, fdiv>;
+
 // FCP instruction
 let cx = 0 in
 defm FCP : RRm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>;

diff --git a/llvm/test/CodeGen/VE/fp_add.ll b/llvm/test/CodeGen/VE/fp_add.ll
new file mode 100644 (file)
index 0000000..03e32e8
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_add.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
+
+define float @func1(float %a, float %b) {
+; CHECK-LABEL: func1:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fadd.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd float %a, %b
+  ret float %r
+}
+
+define double @func2(double %a, double %b) {
+; CHECK-LABEL: func2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fadd.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd double %a, %b
+  ret double %r
+}
+
+define float @func4(float %a) {
+; CHECK-LABEL: func4:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 1084227584
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fadd.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd float %a, 5.000000e+00
+  ret float %r
+}
+
+define double @func5(double %a) {
+; CHECK-LABEL: func5:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 1075052544
+; CHECK-NEXT:    fadd.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd double %a, 5.000000e+00
+  ret double %r
+}
+
+define float @func7(float %a) {
+; CHECK-LABEL: func7:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 2139095039
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fadd.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd float %a, 0x47EFFFFFE0000000
+  ret float %r
+}
+
+define double @func8(double %a) {
+; CHECK-LABEL: func8:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s1, -1
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, 2146435071(%s1)
+; CHECK-NEXT:    fadd.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd double %a, 0x7FEFFFFFFFFFFFFF
+  ret double %r
+}

diff --git a/llvm/test/CodeGen/VE/fp_div.ll b/llvm/test/CodeGen/VE/fp_div.ll
new file mode 100644 (file)
index 0000000..2a8c7df
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_div.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
+
+define float @func1(float %a, float %b) {
+; CHECK-LABEL: func1:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fdiv.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fdiv float %a, %b
+  ret float %r
+}
+
+define double @func2(double %a, double %b) {
+; CHECK-LABEL: func2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fdiv.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fdiv double %a, %b
+  ret double %r
+}
+
+define float @func4(float %a) {
+; CHECK-LABEL: func4:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 1084227584
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fdiv.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fdiv float %a, 5.000000e+00
+  ret float %r
+}
+
+define double @func5(double %a) {
+; CHECK-LABEL: func5:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 1075052544
+; CHECK-NEXT:    fdiv.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fdiv double %a, 5.000000e+00
+  ret double %r
+}
+
+define float @func7(float %a) {
+; CHECK-LABEL: func7:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 2139095039
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fdiv.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fdiv float %a, 0x47EFFFFFE0000000
+  ret float %r
+}
+
+define double @func8(double %a) {
+; CHECK-LABEL: func8:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s1, -1
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, 2146435071(%s1)
+; CHECK-NEXT:    fdiv.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fdiv double %a, 0x7FEFFFFFFFFFFFFF
+  ret double %r
+}

diff --git a/llvm/test/CodeGen/VE/fp_mul.ll b/llvm/test/CodeGen/VE/fp_mul.ll
new file mode 100644 (file)
index 0000000..047c66d
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_mul.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
+
+define float @func1(float %a, float %b) {
+; CHECK-LABEL: func1:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fmul.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fmul float %a, %b
+  ret float %r
+}
+
+define double @func2(double %a, double %b) {
+; CHECK-LABEL: func2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fmul.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fmul double %a, %b
+  ret double %r
+}
+
+define float @func4(float %a) {
+; CHECK-LABEL: func4:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 1084227584
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fmul.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fmul float %a, 5.000000e+00
+  ret float %r
+}
+
+define double @func5(double %a) {
+; CHECK-LABEL: func5:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 1075052544
+; CHECK-NEXT:    fmul.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fmul double %a, 5.000000e+00
+  ret double %r
+}
+
+define float @func7(float %a) {
+; CHECK-LABEL: func7:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, 2139095039
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fmul.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fmul float %a, 0x47EFFFFFE0000000
+  ret float %r
+}
+
+define double @func8(double %a) {
+; CHECK-LABEL: func8:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s1, -1
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, 2146435071(%s1)
+; CHECK-NEXT:    fmul.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fmul double %a, 0x7FEFFFFFFFFFFFFF
+  ret double %r
+}

diff --git a/llvm/test/CodeGen/VE/fp_sub.ll b/llvm/test/CodeGen/VE/fp_sub.ll
new file mode 100644 (file)
index 0000000..6a4b803
--- /dev/null
+++ b/llvm/test/CodeGen/VE/fp_sub.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
+
+define float @func1(float %a, float %b) {
+; CHECK-LABEL: func1:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fsub.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fsub float %a, %b
+  ret float %r
+}
+
+define double @func2(double %a, double %b) {
+; CHECK-LABEL: func2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    fsub.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fsub double %a, %b
+  ret double %r
+}
+
+define float @func4(float %a) {
+; CHECK-LABEL: func4:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, -1063256064
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fadd.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd float %a, -5.000000e+00
+  ret float %r
+}
+
+define double @func5(double %a) {
+; CHECK-LABEL: func5:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, -1072431104
+; CHECK-NEXT:    fadd.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd double %a, -5.000000e+00
+  ret double %r
+}
+
+define float @func7(float %a) {
+; CHECK-LABEL: func7:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea.sl %s1, -8388609
+; CHECK-NEXT:    or %s1, 0, %s1
+; CHECK-NEXT:    fadd.s %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd float %a, 0xC7EFFFFFE0000000
+  ret float %r
+}
+
+define double @func8(double %a) {
+; CHECK-LABEL: func8:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s1, -1
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, -1048577(%s1)
+; CHECK-NEXT:    fadd.d %s0, %s0, %s1
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = fadd double %a, 0xFFEFFFFFFFFFFFFF
+  ret double %r
+}