irqchip/gic-v3-its: Add VPE interrupt masking

When masking/unmasking a doorbell interrupt, it is necessary
to issue an invalidation to the corresponding redistributor.
We use the DirectLPI feature by writting directly to the corresponding
redistributor.

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 8d45e88..eee2693 100644 (file)
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -276,6 +276,12 @@ static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
 #define gicr_write_pendbaser(v, c)     __gic_writeq_nonatomic(v, c)
 
 /*
+ * GICR_xLPIR - only the lower bits are significant
+ */
+#define gic_read_lpir(c)               readl_relaxed(c)
+#define gic_write_lpir(v, c)           writel_relaxed(lower_32_bits(v), c)
+
+/*
  * GITS_TYPER is an ID register and doesn't need atomicity.
  */
 #define gits_read_typer(c)             __gic_readq_nonatomic(c)

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 0d2a534..b7e3f74 100644 (file)
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -116,6 +116,8 @@ static inline void gic_write_bpr1(u32 val)
 
 #define gic_read_typer(c)              readq_relaxed(c)
 #define gic_write_irouter(v, c)                writeq_relaxed(v, c)
+#define gic_read_lpir(c)               readq_relaxed(c)
+#define gic_write_lpir(v, c)           writeq_relaxed(v, c)
 
 #define gic_flush_dcache_to_poc(a,l)   __flush_dcache_area((a), (l))
 

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index ab25b57..9040fb4 100644 (file)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2336,8 +2336,41 @@ static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
        }
 }
 
+static void its_vpe_send_inv(struct irq_data *d)
+{
+       struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
+       void __iomem *rdbase;
+
+       rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
+       gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
+       while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
+               cpu_relax();
+}
+
+static void its_vpe_mask_irq(struct irq_data *d)
+{
+       /*
+        * We need to unmask the LPI, which is described by the parent
+        * irq_data. Instead of calling into the parent (which won't
+        * exactly do the right thing, let's simply use the
+        * parent_data pointer. Yes, I'm naughty.
+        */
+       lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
+       its_vpe_send_inv(d);
+}
+
+static void its_vpe_unmask_irq(struct irq_data *d)
+{
+       /* Same hack as above... */
+       lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
+       its_vpe_send_inv(d);
+}
+
 static struct irq_chip its_vpe_irq_chip = {
        .name                   = "GICv4-vpe",
+       .irq_mask               = its_vpe_mask_irq,
+       .irq_unmask             = its_vpe_unmask_irq,
+       .irq_eoi                = irq_chip_eoi_parent,
        .irq_set_affinity       = its_vpe_set_affinity,
        .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
 };