asm volatile("" : : : "memory");
}
-void pxa_dram_init(void)
+void pxa2xx_dram_init(void)
{
uint32_t tmp;
int i;
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
- pxa_dram_init();
+ pxa2xx_dram_init();
icache_disable();
dcache_disable();
asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
-void pxa_dram_init(void);
+void pxa2xx_dram_init(void);
#endif /* __PXA_H__ */
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
/* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */
arch_cpu_init();
- pxa_dram_init();
+ pxa2xx_dram_init();
onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR,
CONFIG_SPL_ONENAND_LOAD_SIZE,
(void *)CONFIG_SYS_TEXT_BASE);
int dram_init(void)
{
#ifndef CONFIG_ONENAND
- pxa_dram_init();
+ pxa2xx_dram_init();
#endif
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init(void)
{
- pxa_dram_init();
+ pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}