mvebe: Migrate CONFIG_DDR_LOG_LEVEL to Kconfig

Move this specific option to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 1daa647..944bbee 100644 (file)
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -197,6 +197,20 @@ config DDR_32BIT
 
 endchoice
 
+config DDR_LOG_LEVEL
+       int "DDR training code log level"
+       depends on ARMADA_XP
+       default 0
+       range 0 3
+       help
+         Amount of information provided on error while running the DDR
+         training code.  At level 0, provides an error code in a case of
+         failure, RL, WL errors and other algorithm failure.  At level 1,
+         provides the D-Unit setup (SPD/Static configuration).  At level 2,
+         provides the windows margin as a results of DQS centeralization.
+         At level 3, rovides the windows margin of each DQ as a results of
+         DQS centeralization.
+
 config SYS_BOARD
        default "clearfog" if TARGET_CLEARFOG
        default "helios4" if TARGET_HELIOS4

diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index 10d064d..437a02e 100644 (file)
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -16,11 +16,7 @@
  * Level 3: Provides the windows margin of each DQ as a results of DQS
  *          centeralization
  */
-#ifdef CONFIG_DDR_LOG_LEVEL
 #define        DDR3_LOG_LEVEL  CONFIG_DDR_LOG_LEVEL
-#else
-#define        DDR3_LOG_LEVEL  0
-#endif
 
 #define DDR3_PBS        1