intel/fs/ra: Sanity-check our IP counts

Starting with e99081e76d4a, we don't re-construct liveness information
every time we spill a register.  Instead, we're very careful to track
which instructions are spill instructions and not contribute those to
the IP count so that we can continue to use the old liveness information
even though instructions have been added.  This commit adds an assert
that sanity-checks that we count the same number of instructions as our
liveness information is based on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7084>

diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp
index c7b37a9..62b4299 100644 (file)
--- a/src/intel/compiler/brw_fs_reg_allocate.cpp
+++ b/src/intel/compiler/brw_fs_reg_allocate.cpp
@@ -416,6 +416,11 @@ public:
    {
       mem_ctx = ralloc_context(NULL);
 
+      /* Stash the number of instructions so we can sanity check that our
+       * counts still match liveness.
+       */
+      live_instr_count = fs->cfg->last_block()->end_ip + 1;
+
       /* Most of this allocation was written for a reg_width of 1
        * (dispatch_width == 8).  In extending to SIMD16, the code was
        * left in place and it was converted to have the hardware
@@ -467,6 +472,7 @@ private:
    const gen_device_info *devinfo;
    const brw_compiler *compiler;
    const fs_live_variables &live;
+   int live_instr_count;
 
    /* Which compiler->fs_reg_sets[] to use */
    int rsi;
@@ -1172,6 +1178,8 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
           inst->opcode != SHADER_OPCODE_GEN7_SCRATCH_READ)
          ip++;
    }
+
+   assert(ip == live_instr_count);
 }
 
 bool