}
if (ret)
- dev_err(nor->dev, "error %d reading SR\n", ret);
+ dev_dbg(nor->dev, "error %d reading SR\n", ret);
return ret;
}
}
if (ret)
- dev_err(nor->dev, "error %d reading FSR\n", ret);
+ dev_dbg(nor->dev, "error %d reading FSR\n", ret);
return ret;
}
}
if (ret)
- dev_err(nor->dev, "error %d reading CR\n", ret);
+ dev_dbg(nor->dev, "error %d reading CR\n", ret);
return ret;
}
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
if (ret) {
- dev_err(nor->dev, "error %d reading XRDSR\n", ret);
+ dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
return ret;
}
cond_resched();
}
- dev_err(nor->dev, "flash operation timed out\n");
+ dev_dbg(nor->dev, "flash operation timed out\n");
return -ETIMEDOUT;
}
}
if (ret) {
- dev_err(nor->dev,
+ dev_dbg(nor->dev,
"error while writing configuration register\n");
return -EINVAL;
}
return ret;
if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
- dev_err(nor->dev, "Macronix Quad bit not set\n");
+ dev_dbg(nor->dev, "Macronix Quad bit not set\n");
return -EINVAL;
}
return ret;
if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
- dev_err(nor->dev, "Spansion Quad bit not set\n");
+ dev_dbg(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
return ret;
if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
- dev_err(nor->dev, "Spansion Quad bit not set\n");
+ dev_dbg(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
ret = spi_nor_write_sr2(nor, sr2);
if (ret) {
- dev_err(nor->dev, "error while writing status register 2\n");
+ dev_dbg(nor->dev, "error while writing status register 2\n");
return ret;
}
return ret;
if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
- dev_err(nor->dev, "SR2 Quad bit not set\n");
+ dev_dbg(nor->dev, "SR2 Quad bit not set\n");
return -EINVAL;
}
ret = spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret) {
- dev_err(nor->dev, "write to status register failed\n");
+ dev_dbg(nor->dev, "write to status register failed\n");
return ret;
}
SPI_NOR_MAX_ID_LEN);
}
if (tmp) {
- dev_err(nor->dev, "error %d reading JEDEC ID\n", tmp);
+ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp);
}
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
if (ret) {
- dev_err(nor->dev, "error %d reading XRDSR\n", ret);
+ dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
return ret;
}
err = spi_nor_read_sfdp(nor, sizeof(header),
psize, param_headers);
if (err < 0) {
- dev_err(dev, "failed to read SFDP parameter headers\n");
+ dev_dbg(dev, "failed to read SFDP parameter headers\n");
goto exit;
}
}
/* Select the (Fast) Read command. */
err = spi_nor_select_read(nor, shared_mask);
if (err) {
- dev_err(nor->dev,
+ dev_dbg(nor->dev,
"can't select read settings supported by both the SPI controller and memory.\n");
return err;
}
/* Select the Page Program command. */
err = spi_nor_select_pp(nor, shared_mask);
if (err) {
- dev_err(nor->dev,
+ dev_dbg(nor->dev,
"can't select write settings supported by both the SPI controller and memory.\n");
return err;
}
/* Select the Sector Erase command. */
err = spi_nor_select_erase(nor);
if (err) {
- dev_err(nor->dev,
+ dev_dbg(nor->dev,
"can't select erase settings supported by both the SPI controller and memory.\n");
return err;
}
err = nor->clear_sr_bp(nor);
if (err) {
- dev_err(nor->dev,
+ dev_dbg(nor->dev,
"fail to clear block protection bits\n");
return err;
}
err = spi_nor_quad_enable(nor);
if (err) {
- dev_err(nor->dev, "quad mode not supported\n");
+ dev_dbg(nor->dev, "quad mode not supported\n");
return err;
}
}
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
- dev_err(nor->dev, "address width is too large: %u\n",
+ dev_dbg(nor->dev, "address width is too large: %u\n",
nor->addr_width);
return -EINVAL;
}