i40e: Add functions which apply correct PHY access method for read and write operation
authorMichal Kosiarz <michal.kosiarz@intel.com>
Mon, 21 Nov 2016 21:03:50 +0000 (13:03 -0800)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Wed, 7 Dec 2016 05:09:39 +0000 (21:09 -0800)
Depending on external PHY type, register access method should be
different. Clause22 or Clause45 can be chosen for different PHYs.
Implemented functions apply correct access method for used device.

Change-ID: If39d5f0da9c0b905a8cbdc1ab89885535e7d0426
Signed-off-by: Michal Kosiarz <michal.kosiarz@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/i40e/i40e_common.c
drivers/net/ethernet/intel/i40e/i40e_prototype.h
drivers/net/ethernet/intel/i40evf/i40e_prototype.h

index f8c4c14..1287359 100644 (file)
@@ -4676,6 +4676,78 @@ phy_write_end:
 }
 
 /**
+ * i40e_write_phy_register
+ * @hw: pointer to the HW structure
+ * @page: registers page number
+ * @reg: register address in the page
+ * @phy_adr: PHY address on MDIO interface
+ * @value: PHY register value
+ *
+ * Writes value to specified PHY register
+ **/
+i40e_status i40e_write_phy_register(struct i40e_hw *hw,
+                                   u8 page, u16 reg, u8 phy_addr, u16 value)
+{
+       i40e_status status;
+
+       switch (hw->device_id) {
+       case I40E_DEV_ID_1G_BASE_T_X722:
+               status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
+                                                         value);
+               break;
+       case I40E_DEV_ID_10G_BASE_T:
+       case I40E_DEV_ID_10G_BASE_T4:
+       case I40E_DEV_ID_10G_BASE_T_X722:
+       case I40E_DEV_ID_25G_B:
+       case I40E_DEV_ID_25G_SFP28:
+               status = i40e_write_phy_register_clause45(hw, page, reg,
+                                                         phy_addr, value);
+               break;
+       default:
+               status = I40E_ERR_UNKNOWN_PHY;
+               break;
+       }
+
+       return status;
+}
+
+/**
+ * i40e_read_phy_register
+ * @hw: pointer to the HW structure
+ * @page: registers page number
+ * @reg: register address in the page
+ * @phy_adr: PHY address on MDIO interface
+ * @value: PHY register value
+ *
+ * Reads specified PHY register value
+ **/
+i40e_status i40e_read_phy_register(struct i40e_hw *hw,
+                                  u8 page, u16 reg, u8 phy_addr, u16 *value)
+{
+       i40e_status status;
+
+       switch (hw->device_id) {
+       case I40E_DEV_ID_1G_BASE_T_X722:
+               status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
+                                                        value);
+               break;
+       case I40E_DEV_ID_10G_BASE_T:
+       case I40E_DEV_ID_10G_BASE_T4:
+       case I40E_DEV_ID_10G_BASE_T_X722:
+       case I40E_DEV_ID_25G_B:
+       case I40E_DEV_ID_25G_SFP28:
+               status = i40e_read_phy_register_clause45(hw, page, reg,
+                                                        phy_addr, value);
+               break;
+       default:
+               status = I40E_ERR_UNKNOWN_PHY;
+               break;
+       }
+
+       return status;
+}
+
+/**
  * i40e_get_phy_address
  * @hw: pointer to the HW structure
  * @dev_num: PHY port num that address we want
index 37d67e7..2551fc8 100644 (file)
@@ -373,6 +373,10 @@ i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
                                u8 page, u16 reg, u8 phy_addr, u16 *value);
 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
                                u8 page, u16 reg, u8 phy_addr, u16 value);
+i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
+                                  u8 phy_addr, u16 *value);
+i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
+                                   u8 phy_addr, u16 value);
 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
                                    u32 time, u32 interval);
index d89d521..ba6c6bd 100644 (file)
@@ -115,6 +115,10 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,
                                   u16 reg, u8 phy_addr, u16 *value);
 i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,
                                    u16 reg, u8 phy_addr, u16 value);
+i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
+                                  u8 phy_addr, u16 *value);
+i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
+                                   u8 phy_addr, u16 value);
 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
                                    u32 time, u32 interval);