hw_random: starfive-trng: Standardize the code and annotation

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

diff --git a/drivers/char/hw_random/starfive-trng.c b/drivers/char/hw_random/starfive-trng.c
index 4c1051b..c84aead 100644 (file)
--- a/drivers/char/hw_random/starfive-trng.c
+++ b/drivers/char/hw_random/starfive-trng.c
@@ -1,13 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2021 StarFive, Inc
+ * TRNG driver for the StarFive JH7110 SoC
  *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
  */
 
 #include <linux/err.h>
@@ -84,7 +79,7 @@ static inline int is_reseed_done(struct trng *hrng)
 
 static inline void trng_irq_mask_clear(struct trng *hrng)
 {
-       // clear register: ISTAT
+       /* clear register: ISTAT */
        u32 data = readl(hrng->base + CCORE_ISTAT);
 
        writel(data, hrng->base + CCORE_ISTAT);
@@ -99,7 +94,7 @@ static int trng_random_reseed(struct trng *hrng)
        } while (!is_reseed_done(hrng));
        hrng->trng_reseed_done = 0;
 
-       // start random
+       /* start random */
        writel(CCORE_CTRL_GENE_RANDOM, hrng->base + CCORE_CTRL);
        return 0;
 }
@@ -114,7 +109,7 @@ static int trng_nonce_reseed(struct trng *hrng, const void *nonce_in, int len)
        } while (!is_reseed_done(hrng));
        hrng->trng_reseed_done = 0;
 
-       // start random
+       /* start random */
        writel(CCORE_CTRL_GENE_RANDOM, hrng->base + CCORE_CTRL);
        return 0;
 }
@@ -127,10 +122,10 @@ static int trng_cmd(struct trng *hrng, u32 cmd)
                0xd2daadab, 0x00000000, 0x00000000, 0x00000000,
        };
 
-       // wait till idle
+       /* wait till idle */
        trng_wait_till_idle(hrng);
 
-       //start trng
+       /* start trng */
        switch (cmd) {
        case CCORE_CTRL_EXEC_NOP:
        case CCORE_CTRL_GENE_RANDOM:
@@ -157,14 +152,14 @@ static int trng_init(struct hwrng *rng)
        struct trng *hrng = to_trng(rng);
        u32 mode, smode = 0;
 
-       //disable Auto Request/Age register
+       /* disable Auto Request/Age register */
        writel(AUTOAGE_DISABLED, hrng->base + CCORE_AUTO_AGE);
        writel(AUTOREQ_DISABLED, hrng->base + CCORE_AUTO_RQSTS);
 
-       // clear register: ISTAT
+       /* clear register: ISTAT */
        trng_irq_mask_clear(hrng);
 
-       //set smode/mode
+       /* set smode/mode */
        mode  = readl(hrng->base + CCORE_MODE);
        smode = readl(hrng->base + CCORE_SMODE);
 
@@ -190,7 +185,7 @@ static int trng_init(struct hwrng *rng)
        writel(mode, hrng->base + CCORE_MODE);
        writel(smode, hrng->base + CCORE_SMODE);
 
-       //clear int_mode
+       /* clear int_mode */
        if (hrng->opmode == int_mode)
                writel(0, hrng->base + CCORE_IE);
 
@@ -205,25 +200,19 @@ static irqreturn_t trng_irq(int irq, void *priv)
        status = readl(hrng->base + CCORE_ISTAT);
        if (status & CCORE_ISTAT_RAND_RDY) {
                writel(CCORE_ISTAT_RAND_RDY, hrng->base + CCORE_ISTAT);
-               //dev_info(hrng->dev, "rand ready\r\n");
                hrng->trng_random_done = 1;
        }
 
        if (status & CCORE_ISTAT_SEED_DONE) {
                writel(CCORE_ISTAT_SEED_DONE, hrng->base + CCORE_ISTAT);
-               //dev_info(hrng->dev, "seed ready\r\n");
                hrng->trng_reseed_done = 1;
        }
 
-       if (status & CCORE_ISTAT_AGE_ALARM) {
+       if (status & CCORE_ISTAT_AGE_ALARM)
                writel(CCORE_ISTAT_AGE_ALARM, hrng->base + CCORE_ISTAT);
-               //dev_info(hrng->dev, "age alarm\r\n");
-       }
 
-       if (status & CCORE_ISTAT_LFSR_LOOKUP) {
+       if (status & CCORE_ISTAT_LFSR_LOOKUP)
                writel(CCORE_ISTAT_LFSR_LOOKUP, hrng->base + CCORE_ISTAT);
-               //dev_info(hrng->dev, "lfsr lookup\r\n");
-       }
 
        trng_irq_mask_clear(hrng);
 
@@ -243,7 +232,6 @@ static int trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
        u32 intr = 0;
 
        trng_cmd(hrng, CCORE_CTRL_EXEC_NOP);
-       //trng_wait_till_idle(hrng);
 
        if (hrng->mode == PRNG_256BIT)
                max = min_t(size_t, max, (CCORE_RAND_LEN * 4));
@@ -257,7 +245,6 @@ static int trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
        writel(intr, hrng->base + CCORE_IE);
 
        trng_cmd(hrng, hrng->ctl_cmd);
-       //trng_wait_till_idle(hrng);
 
        if (wait) {
                do {
@@ -341,7 +328,7 @@ static int trng_probe(struct platform_device *pdev)
        if (ret) {
                dev_err(&pdev->dev,
                        "Failed to enable the trng miscahb_clk clock, %d\n", ret);
-               return ret;
+               goto err_disable_hclk;
        }
 
        reset_control_deassert(rng->rst);
@@ -367,10 +354,18 @@ static int trng_probe(struct platform_device *pdev)
        ret = devm_hwrng_register(&pdev->dev, &rng->rng);
        if (ret) {
                dev_err(&pdev->dev, "failed to register hwrng\n");
-               return ret;
+               goto err_disable_miscahb_clk;
        }
 
        return 0;
+
+err_disable_miscahb_clk:
+       clk_disable_unprepare(rng->miscahb_clk);
+
+err_disable_hclk:
+       clk_disable_unprepare(rng->hclk);
+
+       return ret;
 }
 
 static const struct of_device_id trng_dt_ids[] = {

diff --git a/drivers/char/hw_random/starfive-trng.h b/drivers/char/hw_random/starfive-trng.h
index ce37527..302453e 100644 (file)
--- a/drivers/char/hw_random/starfive-trng.h
+++ b/drivers/char/hw_random/starfive-trng.h
@@ -1,23 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
- ******************************************************************************
- * @file  starfive-trng.h
- * @author  StarFive Technology
- * @version  V1.0
- * @date  09/08/2021
- * @brief
- ******************************************************************************
- * @copy
+ * TRNG driver for the StarFive JH7110 SoC
  *
- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
  */
 
+/* trng register offset */
 #define CCORE_CTRL             0x00
 #define CCORE_STAT             0x04
 #define CCORE_MODE             0x08
@@ -45,13 +33,12 @@
 #define CCORE_AUTO_AGE         0x64
 #define CCORE_BUILD_CONFIG     0x68
 
-/* CTRL CMD*/
+/* CTRL CMD */
 #define CCORE_CTRL_EXEC_NOP            (0x0)
 #define CCORE_CTRL_GENE_RANDOM         (0x1)
 #define CCORE_CTRL_EXEC_RANDRESEED     (0x2)
 #define CCORE_CTRL_EXEC_NONCRESEED     (0x3)
 
-
 /* STAT */
 #define _CCORE_STAT_NONCE_MODE         2
 #define _CCORE_STAT_R256               3
@@ -62,31 +49,28 @@
 #define _CCORE_STAT_RAND_GENERATING    30
 #define _CCORE_STAT_RAND_SEEDING       31
 
-#define CCORE_STAT_NONCE_MODE          (1UL << _CCORE_STAT_NONCE_MODE)
-#define CCORE_STAT_R256                        (1UL << _CCORE_STAT_R256)
-#define CCORE_STAT_MISSION_MODE                (1UL << _CCORE_STAT_MISSION_MODE)
-#define CCORE_STAT_SEEDED              (1UL << _CCORE_STAT_SEEDED)
+#define CCORE_STAT_NONCE_MODE          BIT(_CCORE_STAT_NONCE_MODE)
+#define CCORE_STAT_R256                        BIT(_CCORE_STAT_R256)
+#define CCORE_STAT_MISSION_MODE                BIT(_CCORE_STAT_MISSION_MODE)
+#define CCORE_STAT_SEEDED              BIT(_CCORE_STAT_SEEDED)
 #define CCORE_STAT_LAST_RESEED(x)      ((x) << _CCORE_STAT_LAST_RESEED)
-#define CCORE_STAT_SRVC_RQST           (1UL << _CCORE_STAT_SRVC_RQST)
-#define CCORE_STAT_RAND_GENERATING     (1UL << _CCORE_STAT_RAND_GENERATING)
-#define CCORE_STAT_RAND_SEEDING                (1UL << _CCORE_STAT_RAND_SEEDING)
-
-
+#define CCORE_STAT_SRVC_RQST           BIT(_CCORE_STAT_SRVC_RQST)
+#define CCORE_STAT_RAND_GENERATING     BIT(_CCORE_STAT_RAND_GENERATING)
+#define CCORE_STAT_RAND_SEEDING                BIT(_CCORE_STAT_RAND_SEEDING)
 
 /* MODE */
 #define _CCORE_MODE_R256               3
-#define CCORE_MODE_R256                        (1UL << _CCORE_MODE_R256)
+#define CCORE_MODE_R256                        BIT(_CCORE_MODE_R256)
 
 /* SMODE */
 #define _CCORE_SMODE_NONCE_MODE        2
 #define _CCORE_SMODE_MISSION_MODE      8
 #define _CCORE_SMODE_MAX_REJECTS       16
 
-#define CCORE_SMODE_NONCE_MODE         (1UL << _CCORE_SMODE_NONCE_MODE)
-#define CCORE_SMODE_MISSION_MODE       (1UL << _CCORE_SMODE_MISSION_MODE)
+#define CCORE_SMODE_NONCE_MODE         BIT(_CCORE_SMODE_NONCE_MODE)
+#define CCORE_SMODE_MISSION_MODE       BIT(_CCORE_SMODE_MISSION_MODE)
 #define CCORE_SMODE_MAX_REJECTS(x)     ((x) << _CCORE_SMODE_MAX_REJECTS)
 
-
 /* IE */
 #define _CCORE_IE_RAND_REY_EN          0
 #define _CCORE_IE_SEED_DONE_EN         1
@@ -95,16 +79,16 @@
 #define _CCORE_IE_LOCKUP_EN            4
 #define _CCORE_IE_GLBL_EN              31
 
+#define CCORE_IE_RAND_REY_EN           BIT(_CCORE_IE_RAND_REY_EN)
+#define CCORE_IE_SEED_DONE_EN          BIT(_CCORE_IE_SEED_DONE_EN)
+#define CCORE_IE_AGE_ALARM_EN          BIT(_CCORE_IE_AGE_ALARM_EN)
+#define CCORE_IE_RQST_ALARM_EN         BIT(_CCORE_IE_RQST_ALARM_EN)
+#define CCORE_IE_LOCKUP_EN             BIT(_CCORE_IE_LOCKUP_EN)
+#define CCORE_IE_GLBL_EN               BIT(_CCORE_IE_GLBL_EN)
 
-#define CCORE_IE_RAND_REY_EN           (1UL << _CCORE_IE_RAND_REY_EN)
-#define CCORE_IE_SEED_DONE_EN          (1UL << _CCORE_IE_SEED_DONE_EN)
-#define CCORE_IE_AGE_ALARM_EN          (1UL << _CCORE_IE_AGE_ALARM_EN)
-#define CCORE_IE_RQST_ALARM_EN         (1UL << _CCORE_IE_RQST_ALARM_EN)
-#define CCORE_IE_LOCKUP_EN             (1UL << _CCORE_IE_LOCKUP_EN)
-#define CCORE_IE_GLBL_EN               (1UL << _CCORE_IE_GLBL_EN)
-
-#define CCORE_IE_ALL                   (CCORE_IE_GLBL_EN | CCORE_IE_RAND_REY_EN | CCORE_IE_SEED_DONE_EN | \
-                                        CCORE_IE_AGE_ALARM_EN | CCORE_IE_RQST_ALARM_EN | CCORE_IE_LOCKUP_EN)
+#define CCORE_IE_ALL                   (CCORE_IE_GLBL_EN | CCORE_IE_RAND_REY_EN | \
+                                        CCORE_IE_SEED_DONE_EN | CCORE_IE_AGE_ALARM_EN | \
+                                        CCORE_IE_RQST_ALARM_EN | CCORE_IE_LOCKUP_EN)
 
 /* ISTAT */
 #define _CCORE_ISTAT_RAND_RDY          0
@@ -113,38 +97,33 @@
 #define _CCORE_ISTAT_RQST_ALARM                3
 #define _CCORE_ISTAT_LFSR_LOOKUP       4
 
-
-#define CCORE_ISTAT_RAND_RDY           (1UL << _CCORE_ISTAT_RAND_RDY)
-#define CCORE_ISTAT_SEED_DONE          (1UL << _CCORE_ISTAT_SEED_DONE)
-#define CCORE_ISTAT_AGE_ALARM          (1UL << _CCORE_ISTAT_AGE_ALARM)
-#define CCORE_ISTAT_LFSR_LOOKUP                (1UL << _CCORE_ISTAT_LFSR_LOOKUP)
-
+#define CCORE_ISTAT_RAND_RDY           BIT(_CCORE_ISTAT_RAND_RDY)
+#define CCORE_ISTAT_SEED_DONE          BIT(_CCORE_ISTAT_SEED_DONE)
+#define CCORE_ISTAT_AGE_ALARM          BIT(_CCORE_ISTAT_AGE_ALARM)
+#define CCORE_ISTAT_LFSR_LOOKUP                BIT(_CCORE_ISTAT_LFSR_LOOKUP)
 
 /* FEATURES */
 #define _CCORE_FEATURES_MAX_RAND_LENGTH                        0
 #define _CCORE_FEATURES_RAND_SEED_AVAIL                        2
 #define _CCORE_FEATURES_MISSION_MODE_RESET_STATE       3
 
-#define CCORE_FEATURES_MAX_RAND_LENGTH(x)              (x << _CCORE_FEATURES_MAX_RAND_LENGTH)
-#define CCORE_FEATURES_RAND_SEED_AVAIL                 (1UL << _CCORE_FEATURES_RAND_SEED_AVAIL)
-#define CCORE_FEATURES_MISSION_MODE_RESET_STATE                (1UL << _CCORE_FEATURES_MISSION_MODE_RESET_STATE)
-
+#define CCORE_FEATURES_MAX_RAND_LENGTH(x)        ((x) << _CCORE_FEATURES_MAX_RAND_LENGTH)
+#define CCORE_FEATURES_RAND_SEED_AVAIL           BIT(_CCORE_FEATURES_RAND_SEED_AVAIL)
+#define CCORE_FEATURES_MISSION_MODE_RESET_STATE          BIT(_CCORE_FEATURES_MISSION_MODE_RESET_STATE)
 
 #define AUTOREQ_DISABLED                       (0x0)
 #define AUTOAGE_DISABLED                       (0x0)
 
-
 /* BUILD_CONFIG */
 #define _CCORE_BUILD_CONFIG_MAX_PRNG_LEN               2
 #define _CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST                3
 #define _CCORE_BUILD_CONFIG_MODE_AFTER_REST            4
 #define _CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK       5
 
-#define CCORE_BUILD_CONFIG_MAX_PRNG_LEN                        (1UL << _CCORE_BUILD_CONFIG_MAX_PRNG_LEN)
-#define CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST         (1UL << _CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST)
-#define CCORE_BUILD_CONFIG_MODE_AFTER_REST             (1UL << _CCORE_BUILD_CONFIG_MODE_AFTER_REST)
-#define CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK                (1UL << _CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK)
-
+#define CCORE_BUILD_CONFIG_MAX_PRNG_LEN                  BIT(_CCORE_BUILD_CONFIG_MAX_PRNG_LEN)
+#define CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST   BIT(_CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST)
+#define CCORE_BUILD_CONFIG_MODE_AFTER_REST       BIT(_CCORE_BUILD_CONFIG_MODE_AFTER_REST)
+#define CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK          BIT(_CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK)
 
 #define CCORE_RAND_LEN 8
 #define CCORE_SEED_LEN 8
@@ -163,4 +142,3 @@ enum sec_trng_mode {
        PRNG_128BIT,  //PRNG set up for 128bit maximum
        PRNG_256BIT,  //PRNG set up for 256bit maximum
 };
-