for (def = &cpu_default[0]; def->name; ++def)
if (def->cpu == TARGET_CPU_DEFAULT)
break;
- if (! def->name)
- abort ();
+ gcc_assert (def->name);
sparc_select[0].string = def->name;
for (sel = &sparc_select[0]; sel->name; ++sel)
int
call_operand (rtx op, enum machine_mode mode)
{
- if (GET_CODE (op) != MEM)
- abort ();
+ gcc_assert (GET_CODE (op) == MEM);
op = XEXP (op, 0);
return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
}
{
HOST_WIDE_INT value = INTVAL (op1);
- if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
- || SPARC_SIMM13_P (value))
- abort ();
+ gcc_assert (! SPARC_SETHI_P (value & GET_MODE_MASK (mode))
+ && ! SPARC_SIMM13_P (value));
}
/* Full 2-insn decomposition is needed. */
it TImode). Pick the other one to use as our scratch. */
if (rtx_equal_p (temp, op0))
{
- if (ti_temp)
- temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
- else
- abort();
+ gcc_assert (ti_temp);
+ temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
}
temp1 = op0;
temp2 = temp; /* op0 is _not_ allowed, see above. */
it TImode). Pick the other one to use as our scratch. */
if (rtx_equal_p (temp, op0))
{
- if (ti_temp)
- temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
- else
- abort();
+ gcc_assert (ti_temp);
+ temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
}
temp1 = op0;
temp2 = temp; /* op0 is _not_ allowed, see above. */
break;
default:
- abort();
+ gcc_unreachable ();
}
}
}
/* If there are no bits set this should have gone out
as one instruction! */
- if (lowest_bit_set == -1
- || highest_bit_set == -1)
- abort ();
+ gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
all_bits_between_are_set = 1;
for (i = lowest_bit_set; i <= highest_bit_set; i++)
{
lo = 0;
hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
}
- if (hi & lo)
- abort ();
+ gcc_assert (! (hi & lo));
return (hi | lo);
}
rtx temp = 0;
/* Sanity check that we know what we are working with. */
- if (! TARGET_ARCH64)
- abort ();
+ gcc_assert (TARGET_ARCH64);
if (GET_CODE (op0) != SUBREG)
{
- if (GET_CODE (op0) != REG
- || (REGNO (op0) >= SPARC_FIRST_FP_REG
- && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
- abort ();
+ gcc_assert (GET_CODE (op0) == REG
+ && (REGNO (op0) < SPARC_FIRST_FP_REG
+ || REGNO (op0) > SPARC_LAST_V9_FP_REG));
}
if (reload_in_progress || reload_completed)
else if (lowest_bit_set == 0)
shift = -(63 - highest_bit_set);
- if (! SPARC_SIMM13_P (the_const))
- abort ();
+ gcc_assert (SPARC_SIMM13_P (the_const));
+ gcc_assert (shift != 0);
emit_insn (gen_safe_SET64 (temp, the_const));
if (shift > 0)
gen_rtx_LSHIFTRT (DImode,
temp,
GEN_INT (-shift))));
- else
- abort ();
return;
}
create_simple_focus_bits (high_bits, low_bits,
lowest_bit_set, 10);
- if (! SPARC_SETHI_P (focus_bits))
- abort ();
+ gcc_assert (SPARC_SETHI_P (focus_bits));
+ gcc_assert (lowest_bit_set != 10);
sparc_emit_set_safe_HIGH64 (temp, focus_bits);
op0,
gen_rtx_ASHIFT (DImode, temp,
GEN_INT (lowest_bit_set - 10))));
- else
- abort ();
return;
}
lowest_bit_set, 0);
/* We can't get here in this state. */
- if (highest_bit_set < 32
- || lowest_bit_set >= 32)
- abort ();
+ gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
/* So what we know is that the set bits straddle the
middle of the 64-bit word. */
return CCFPEmode;
default:
- abort ();
+ gcc_unreachable ();
}
}
else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
case CCFPmode :
break;
default :
- abort ();
+ gcc_unreachable ();
}
emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
int i;
/* We only expect to be called for conversions, unary, and binary ops. */
- if (nargs < 2 || nargs > 3)
- abort ();
+ gcc_assert (nargs == 2 || nargs == 3);
for (i = 0; i < nargs; ++i)
{
{
rtx ret;
- if (nargs != 2)
- abort ();
+ gcc_assert (nargs == 2);
ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
GET_MODE (operands[0]), 1,
func = "_Qp_div";
break;
default:
- abort ();
+ gcc_unreachable ();
}
emit_soft_tfmode_libcall (func, 3, operands);
{
const char *func;
- switch (code)
- {
- case SQRT:
- func = "_Qp_sqrt";
- break;
- default:
- abort ();
- }
+ gcc_assert (code == SQRT);
+ func = "_Qp_sqrt";
emit_soft_tfmode_libcall (func, 2, operands);
}
func = "_Qp_dtoq";
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
func = "_Qp_qtod";
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
func = "_Qp_xtoq";
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
func = "_Qp_uxtoq";
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
func = "_Qp_qtox";
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
func = "_Qp_qtoux";
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
emit_soft_tfmode_libcall (func, 2, operands);
case UNSPEC:
return true;
default:
- abort ();
+ gcc_unreachable ();
}
}
\f
switch (flag_pic)
{
case 1:
- if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
- || (GET_CODE (recog_data.operand[i]) == CONST
- && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
- && (XEXP (XEXP (recog_data.operand[i], 0), 0)
- == global_offset_table)
- && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
- == CONST))))
- abort ();
+ gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
+ && (GET_CODE (recog_data.operand[i]) != CONST
+ || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
+ && (XEXP (XEXP (recog_data.operand[i], 0), 0)
+ == global_offset_table)
+ && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
+ == CONST))));
case 2:
default:
return 1;
{
rtx temp1, temp2, temp3, ret, o0, got, insn;
- if (no_new_pseudos)
- abort ();
+ gcc_assert (! no_new_pseudos);
if (GET_CODE (addr) == SYMBOL_REF)
switch (SYMBOL_REF_TLS_MODEL (addr))
break;
default:
- abort ();
+ gcc_unreachable ();
}
else
- abort (); /* for now ... */
+ gcc_unreachable (); /* for now ... */
return ret;
}
if (reg == 0)
{
- if (reload_in_progress || reload_completed)
- abort ();
- else
- reg = gen_reg_rtx (Pmode);
+ gcc_assert (! reload_in_progress && ! reload_completed);
+ reg = gen_reg_rtx (Pmode);
}
if (flag_pic == 2)
if (reg == 0)
{
- if (reload_in_progress || reload_completed)
- abort ();
- else
- reg = gen_reg_rtx (Pmode);
+ gcc_assert (! reload_in_progress && ! reload_completed);
+ reg = gen_reg_rtx (Pmode);
}
- if (GET_CODE (XEXP (orig, 0)) == PLUS)
- {
- base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
- offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
- base == reg ? 0 : reg);
- }
- else
- abort ();
+ gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
+ base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
+ offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
+ base == reg ? 0 : reg);
if (GET_CODE (offset) == CONST_INT)
{
offset = force_reg (Pmode, offset);
else
/* If we reach here, then something is seriously wrong. */
- abort ();
+ gcc_unreachable ();
}
return gen_rtx_PLUS (Pmode, base, offset);
}
sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
/* Check that the assumption we made in sparc_expand_prologue is valid. */
- if (sparc_leaf_function_p != current_function_uses_only_leaf_regs)
- abort();
+ gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
sparc_output_scratch_registers (file);
}
return;
}
- if (GET_CODE (pat) != SET)
- abort ();
+ gcc_assert (GET_CODE (pat) == SET);
operands[0] = SET_DEST (pat);
pat = SET_SRC (pat);
break;
case ASHIFT:
operands[1] = XEXP (pat, 0);
- if (XEXP (pat, 1) != const1_rtx)
- abort();
+ gcc_assert (XEXP (pat, 1) == const1_rtx);
output_asm_insn (" restore %r1, %r1, %Y0", operands);
break;
default:
semantics of restore/return. We simply output the jump to the
return address and the insn in the delay slot (if any). */
- if (current_function_calls_eh_return)
- abort ();
+ gcc_assert (! current_function_calls_eh_return);
return "jmp\t%%o7+%)%#";
}
{
/* If the function uses __builtin_eh_return, the eh_return
machinery occupies the delay slot. */
- if (final_sequence)
- abort ();
+ gcc_assert (! final_sequence);
if (! flag_delayed_branch)
fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
rtx delay, pat;
delay = NEXT_INSN (insn);
- if (! delay)
- abort ();
+ gcc_assert (delay);
pat = PATTERN (delay);
{
rtx operands[1];
- if (! flag_delayed_branch)
- abort();
+ gcc_assert (flag_delayed_branch);
operands[0] = call_operand;
register window. We simply output the jump to the function and
the insn in the delay slot (if any). */
- if (LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)
- abort();
+ gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
if (final_sequence)
output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
if (final_sequence)
{
rtx delay = NEXT_INSN (insn);
- if (! delay)
- abort ();
+ gcc_assert (delay);
output_restore (PATTERN (delay));
if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
{
/* The SPARC port defines no floating-point vector modes. */
- if (mode != BLKmode)
- abort ();
+ gcc_assert (mode == BLKmode);
}
else
{
mode or an integral mode, because we are guaranteed
by pass_by_reference that their size is not greater
than 16 bytes and TImode is 16-byte wide. */
- if (mode == BLKmode)
- abort ();
+ gcc_assert (mode != BLKmode);
/* Vector integers are handled like floats according to
the Sun VIS SDK. */
/* MODE is VOIDmode when generating the actual call. */
return -1;
- if (mode != BLKmode)
- abort ();
+ gcc_assert (mode == BLKmode);
/* For SPARC64, objects requiring 16-byte alignment get it. */
if (TARGET_ARCH64
break;
default :
- abort ();
+ gcc_unreachable ();
}
*pregno = regno;
if (nregs + slotno > SPARC_INT_ARG_MAX)
nregs = SPARC_INT_ARG_MAX - slotno;
}
- if (nregs == 0)
- abort ();
+ gcc_assert (nregs != 0);
parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
function_arg_record_value_2 (type, 0, &parms, false);
function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
- if (parms.nregs != nregs)
- abort ();
+ gcc_assert (parms.nregs == nregs);
return parms.ret;
}
/* Structures up to 16 bytes in size are passed in arg slots on the
stack and are promoted to registers where possible. */
- if (int_size_in_bytes (type) > 16)
- abort (); /* shouldn't get here */
+ gcc_assert (int_size_in_bytes (type) <= 16);
return function_arg_record_value (type, mode, slotno, named, regbase);
}
{
HOST_WIDE_INT size = int_size_in_bytes (type);
- if (size > 16)
- abort (); /* shouldn't get here */
+ gcc_assert (size <= 16);
return function_arg_union_value (size, mode, slotno, regno);
}
instructions are enabled. */
HOST_WIDE_INT size = int_size_in_bytes (type);
- if (size > 16)
- abort (); /* shouldn't get here */
+ gcc_assert (size <= 16);
if (mode == BLKmode)
return function_arg_vector_value (size,
instructions are enabled. */
HOST_WIDE_INT size = int_size_in_bytes (type);
- if ((TARGET_ARCH32 && size > 8) || (TARGET_ARCH64 && size > 32))
- abort (); /* shouldn't get here */
+ gcc_assert ((TARGET_ARCH32 && size <= 8)
+ || (TARGET_ARCH64 && size <= 32));
if (mode == BLKmode)
return function_arg_vector_value (size,
/* Structures up to 32 bytes in size are passed in registers,
promoted to fp registers where possible. */
- if (int_size_in_bytes (type) > 32)
- abort (); /* shouldn't get here */
+ gcc_assert (int_size_in_bytes (type) <= 32);
return function_arg_record_value (type, mode, 0, 1, regbase);
}
{
HOST_WIDE_INT size = int_size_in_bytes (type);
- if (size > 32)
- abort (); /* shouldn't get here */
+ gcc_assert (size <= 32);
return function_arg_union_value (size, mode, 0, regbase);
}
in a mode corresponding to the size of the type. */
HOST_WIDE_INT bytes = int_size_in_bytes (type);
- if (bytes > 32)
- abort (); /* shouldn't get here */
+ gcc_assert (bytes <= 32);
mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* ??? !v9: FP branches cannot be preceded by another floating point
break;
default:
- abort ();
+ gcc_unreachable ();
}
strcpy (string, branch);
}
labelno = v9_fcc_labelno;
if (v8)
{
- if (REGNO (cc_reg) == SPARC_FCC_REG)
- labelno = "";
- else
- abort ();
+ gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
+ labelno = "";
}
}
else if (mode == CCXmode || mode == CCX_NOOVmode)
{
labelno = "%%xcc, ";
- if (v8)
- abort ();
+ gcc_assert (! v8);
}
else
{
break;
default:
- abort();
- break;
+ gcc_unreachable ();
}
if (TARGET_ARCH64)
code = reverse_condition (code);
/* Only 64 bit versions of these instructions exist. */
- if (mode != DImode)
- abort ();
+ gcc_assert (mode == DImode);
/* Start by writing the branch condition. */
break;
default:
- abort ();
+ gcc_unreachable ();
}
p = strchr (string, '\0');
sparc_splitdi_legitimate (rtx reg, rtx mem)
{
/* Punt if we are here by mistake. */
- if (! reload_completed)
- abort ();
+ gcc_assert (reload_completed);
/* We must have an offsettable memory reference. */
if (! offsettable_memref_p (mem))
else if (GET_MODE (x) == CCXmode)
fputs ("%xcc", file);
else
- abort ();
+ gcc_unreachable ();
}
else
/* %fccN register */
return qualifiers;
default:
- abort (); /* Not a type! */
+ gcc_unreachable (); /* Not a type! */
}
}
int set_once = 0;
rtx y = x;
- if (GET_CODE (x) != REG)
- abort ();
+ gcc_assert (GET_CODE (x) == REG);
if (GET_MODE (x) == DImode)
y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
rtx vcall_offset_rtx = GEN_INT (vcall_offset);
rtx scratch = gen_rtx_REG (Pmode, 1);
- if (vcall_offset >= 0)
- abort ();
+ gcc_assert (vcall_offset < 0);
/* SCRATCH = *THIS. */
emit_move_insn (scratch, gen_rtx_MEM (Pmode, this));
break;
default:
- abort();
+ gcc_unreachable ();
}
}
&& for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
return cfun->machine->some_ld_name;
- abort ();
+ gcc_unreachable ();
}
static int
fputs ("\t.xword\t%r_tls_dtpoff64(", file);
break;
default:
- abort ();
+ gcc_unreachable ();
}
output_addr_const (file, x);
fputs (")", file);
projects / platform / upstream / gcc.git / commitdiff