dt-bindings: Update Sibi Sankar's email address
authorSibi Sankar <quic_sibis@quicinc.com>
Thu, 2 Jun 2022 00:48:41 +0000 (06:18 +0530)
committerRob Herring <robh@kernel.org>
Thu, 2 Jun 2022 14:42:02 +0000 (09:42 -0500)
Update email address to the quicinc.com domain.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1654130923-18722-1-git-send-email-quic_sibis@quicinc.com
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml

index 116e434d0daa8c88ad90d8c5ec9aa8f5e0710c8c..bf538c0c5a811386cc33aac7093a5f07c2f7106c 100644 (file)
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
 
 maintainers:
-  - Sibi Sankar <sibis@codeaurora.org>
+  - Sibi Sankar <quic_sibis@quicinc.com>
 
 description:
   L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
index a054757f4d9f4e8931379c827e3c0a9aca7f107a..d92e2b3cc83f9c427a026d43072bd1f0c1e57d35 100644 (file)
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm AOSS Reset Controller
 
 maintainers:
-  - Sibi Sankar <sibis@codeaurora.org>
+  - Sibi Sankar <quic_sibis@quicinc.com>
 
 description:
   The bindings describe the reset-controller found on AOSS-CC (always on
index 831ea8d5d83f8df55bf7ba1295ca0dae7470adc1..ca5d79332189bc8b163e7ac345beef77e5b37168 100644 (file)
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm PDC Global
 
 maintainers:
-  - Sibi Sankar <sibis@codeaurora.org>
+  - Sibi Sankar <quic_sibis@quicinc.com>
 
 description:
   The bindings describes the reset-controller found on PDC-Global (Power Domain