src/shaders/post_processing/gen5_6/Makefile
src/shaders/post_processing/gen7/Makefile
src/shaders/render/Makefile
+ src/shaders/utils/Makefile
src/shaders/vme/Makefile
])
-SUBDIRS = h264 mpeg2 render post_processing vme
+SUBDIRS = h264 mpeg2 render post_processing vme utils
EXTRA_DIST = gpp.py
--- /dev/null
+MFC_CORE = \
+ end_thread.asm \
+ mfc_batchbuffer_head.asm \
+ mfc_batchbuffer_tail.asm
+MFC_CORE_AVC = \
+ mfc_batchbuffer_avc_intra.asm \
+ mfc_batchbuffer_avc_inter.asm
+
+INTEL_G6B = mfc_batchbuffer_avc_intra.g6b mfc_batchbuffer_avc_inter.g6b
+INTEL_G6A = mfc_batchbuffer_avc_intra.g6a mfc_batchbuffer_avc_inter.g6a
+INTEL_GEN6_INC = mfc_batchbuffer.inc
+INTEL_GEN6_ASM = $(INTEL_G6A:%.g6a=%.gen6.asm)
+
+INTEL_G7B = mfc_batchbuffer_avc_intra.g7b mfc_batchbuffer_avc_inter.g7b
+INTEL_G7A = mfc_batchbuffer_avc_intra.g7a mfc_batchbuffer_avc_inter.g7a
+INTEL_GEN7_INC = mfc_batchbuffer.inc
+INTEL_GEN7_ASM = $(INTEL_G7A:%.g7a=%.gen7.asm)
+
+TARGETS =
+if HAVE_GEN4ASM
+TARGETS += $(INTEL_G6B)
+TARGETS += $(INTEL_G7B)
+endif
+
+all-local: $(TARGETS)
+
+SUFFIXES = .g6a .g6b .g7a .g7b .gen6.asm .gen7.asm
+
+if HAVE_GEN4ASM
+$(INTEL_GEN6_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN6_INC)
+.g6a.gen6.asm:
+ $(AM_V_GEN)cpp -P -DDEV_SNB $< > _mfc0.$@ && \
+ m4 _mfc0.$@ > $@ && \
+ rm _mfc0.$@
+.gen6.asm.g6b:
+ $(AM_V_GEN)$(GEN4ASM) -g 6 -o $@ $<
+
+$(INTEL_GEN7_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN7_INC)
+.g7a.gen7.asm:
+ $(AM_V_GEN)cpp -P -DDEV_IVB $< > _mfc0.$@ && \
+ m4 _mfc0.$@ > $@ && \
+ rm _mfc0.$@
+.gen7.asm.g7b:
+ $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $<
+endif
+
+CLEANFILES = $(INTEL_GEN6_ASM) $(INTEL_GEN7_ASM)
+
+EXTRA_DIST = \
+ $(INTEL_G6A) \
+ $(INTEL_G6B) \
+ $(INTEL_G7A) \
+ $(INTEL_G7B) \
+ $(INTEL_GEN6_INC) \
+ $(INTEL_GEN7_INC) \
+ $(MFC_CORE) \
+ $(MFC_CORE_AVC) \
+ $(NULL)
+
+# Extra clean files so that maintainer-clean removes *everything*
+MAINTAINERCLEANFILES = Makefile.in
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+__EXIT:
+ mov (8) msg_reg0<1>:ud r0<8,8,1>:ud {align1} ;
+ send (16) msg_ind acc0<1>ud null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT} ;
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+define(`BIND_IDX_VME_OUTPUT', `0')
+define(`BIND_IDX_MFC_SLICE_HEADER', `1')
+define(`BIND_IDX_MFC_BATCHBUFFER', `2')
+
+#ifdef DEV_SNB
+
+define(`OB_CACHE_TYPE', `5')
+
+#else
+
+define(`OB_CACHE_TYPE', `10')
+
+#endif
+
+define(`OB_READ', `0')
+define(`OB_WRITE', `8')
+
+define(`OB_CONTROL_0', `0') /* 1 OWord, low 128 bits */
+define(`OB_CONTROL_1', `1') /* 1 OWord, high 128 bits */
+define(`OB_CONTROL_2', `2') /* 2 OWords */
+define(`OB_CONTROL_3', `3') /* 4 OWords */
+define(`OB_CONTROL_4', `4') /* 8 OWords */
+
+#ifdef DEV_SNB
+
+define(`OB_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */
+
+#else
+
+define(`OB_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */
+
+#endif
+
+define(`OB_HEADER_PRESENT', `1')
+
+define(`MFC_AVC_PAK_OBJECT_INTRA_DW0', `0x71490009:UD')
+define(`MFC_AVC_PAK_OBJECT_INTRA_DW3', `0x000e0000:UD') /* CbpDC (1 << 19 | 1 << 18 | 1 << 17) */
+define(`MFC_AVC_PAK_OBJECT_INTRA_DW4', `0xFFFF0000:UD') /* CBP for Y */
+define(`MFC_AVC_PAK_OBJECT_INTRA_DW5', `0x000F000F:UD')
+define(`MFC_AVC_PAK_OBJECT_INTRA_DW6', `0x04000000:UD') /* the flag of the last macroblock */
+
+define(`MFC_AVC_PAK_OBJECT_INTER_DW0', `MFC_AVC_PAK_OBJECT_INTRA_DW0')
+define(`MFC_AVC_PAK_OBJECT_INTER_DW1', `0x20:UD') /* 32 MVs */
+define(`MFC_AVC_PAK_OBJECT_INTER_DW2', `0x40:UD') /* offset, in bytes */
+define(`MFC_AVC_PAK_OBJECT_INTER_DW3', `0x014e0120:UD') /*
+ * (1 << 24) | PackedMvNum, Debug
+ * (4 << 20) | 8 MV, SNB don't use it
+ * (1 << 19) | CbpDcY
+ * (1 << 18) | CbpDcU
+ * (1 << 17) | CbpDcV
+ * (0 << 15) | Transform8x8Flag = 0
+ * (0 << 14) | Frame based
+ * (0 << 13) | Inter MB
+ * (1 << 8) | MbType = P_L0_16x16
+ * (0 << 7) | MBZ for frame
+ * (0 << 6) | MBZ
+ * (2 << 4) | MBZ for inter
+ * (0 << 3) | MBZ
+ * (0 << 2) | SkipMbFlag
+ * (0 << 0) InterMbMode
+ */
+define(`MFC_AVC_PAK_OBJECT_INTER_DW4', `MFC_AVC_PAK_OBJECT_INTRA_DW4')
+define(`MFC_AVC_PAK_OBJECT_INTER_DW5', `MFC_AVC_PAK_OBJECT_INTRA_DW5')
+define(`MFC_AVC_PAK_OBJECT_INTER_DW6', `MFC_AVC_PAK_OBJECT_INTRA_DW6')
+
+define(`MI_BATCH_BUFFER_END', `0x05000000:UD')
+
+/* GRF registers
+ * r0 header
+ * r1~r4 constant buffer (reserved)
+ * r5 inline data
+ * r6~r7 reserved
+ * r8~r15 temporary registers
+ * r16 write back of Oword Block Write
+ */
+/*
+ * GRF 0 -- header
+ */
+define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */
+
+/*
+ * GRF 1~4 -- Constant Buffer (reserved)
+ */
+
+define(`FLAG_MASK_LAST_SLICE', `0x0001:uw')
+define(`FLAG_MASK_LAST_OBJECT', `0x0002:uw')
+define(`FLAG_MASK_FIRST_OBJECT', `0x0004:uw')
+
+/*
+ * GRF 5 -- inline data
+ */
+define(`inline_reg0', `r5')
+define(`head_offset', `inline_reg0.0') /* :ud, in units of Owords */
+define(`batchbuffer_offset', `inline_reg0.4') /* :ud, in units of Owords */
+define(`tail_size', `inline_reg0.8') /* :w, in units of Owords */
+define(`head_size', `inline_reg0.10') /* :w, in units of Owords */
+define(`flags', `inline_reg0.12') /* :uw,
+ * bit0 the flag of the last slice
+ * bit1 the flag of the last object in a slice
+ * bit2 the flag of the first object in a slice
+ */
+define(`total_mbs', `inline_reg0.14') /* :w, the number of macroblock commands
+ * being processed by the kernel
+ */
+define(`mb_x', `inline_reg0.16') /* :ub, */
+define(`mb_y', `inline_reg0.17') /* :ub, */
+define(`mb_xy', `inline_reg0.16') /* :uw, */
+define(`width_in_mb', `inline_reg0.20') /* :uw, the picture width in macroblocks */
+define(`qp', `inline_reg0.22') /* :ub, */
+
+/*
+ * GRF 8~15 -- temporary registers
+ */
+define(`tmp_reg0', `r8')
+define(`tmp_reg1', `r9')
+define(`tmp_reg2', `r10')
+define(`tmp_reg3', `r11')
+define(`tmp_reg4', `r12')
+define(`tmp_reg5', `r13')
+define(`tmp_reg6', `r14')
+define(`tmp_reg7', `r15')
+
+define(`tmp_vme_output', `tmp_reg0')
+define(`tmp_slice_header', `tmp_reg1')
+define(`tmp_mfc_batchbuffer', `tmp_reg2')
+
+/*
+ * GRF 16~23 write back for Oword Block Read message
+ */
+define(`ob_read_wb', `r16<1>:uw')
+define(`ob_read_wb0', `r16')
+define(`ob_read_wb1', `r17')
+define(`ob_read_wb2', `r18')
+define(`ob_read_wb3', `r19')
+define(`ob_read_wb4', `r20')
+define(`ob_read_wb5', `r21')
+define(`ob_read_wb6', `r22')
+define(`ob_read_wb7', `r23')
+
+define(`ob_read_wb_len_slice_header', `1')
+define(`ob_read_wb_len_vme_intra', `1')
+define(`ob_read_wb_len_vme_inter', `4')
+
+#ifdef DEV_SNB
+
+/*
+ * GRF 24~25 write back for Oword Block Write message
+ */
+
+define(`ob_write_wb', `r24')
+define(`ob_write_wb_length', `1')
+
+#else
+
+/*
+ * GRF 24~25 -- reserved
+ */
+define(`ob_write_wb', `null<1>:W')
+define(`ob_write_wb_length', `0')
+
+#endif
+
+/*
+ * GRF 26~27
+ */
+define(`pak_object_ud', `r26.0')
+define(`pak_object0_ud', `r26.0')
+define(`pak_object1_ud', `r26.4')
+define(`pak_object2_ud', `r26.8')
+define(`pak_object3_ud', `r26.12')
+define(`pak_object4_ud', `r26.16')
+define(`pak_object5_ud', `r26.20')
+define(`pak_object6_ud', `r26.24')
+define(`pak_object7_ud', `r26.28')
+define(`pak_object8_ud', `r27.0')
+define(`pak_object9_ud', `r27.4')
+define(`pak_object10_ud', `r27.8')
+define(`pak_object11_ud', `r27.12')
+
+#ifdef DEV_SNB
+
+/*
+ * Message Payload registers
+ */
+define(`msg_ind', `0')
+define(`msg_reg0', `m0')
+define(`msg_reg1', `m1')
+define(`msg_reg2', `m2')
+define(`msg_reg3', `m3')
+define(`msg_reg4', `m4')
+define(`msg_reg5', `m5')
+define(`msg_reg6', `m6')
+define(`msg_reg7', `m7')
+define(`msg_reg8', `m8')
+
+#else
+
+/*
+ * Message Payload registers
+ */
+define(`msg_ind', `64')
+define(`msg_reg0', `g64')
+define(`msg_reg1', `g65')
+define(`msg_reg2', `g66')
+define(`msg_reg3', `g67')
+define(`msg_reg4', `g68')
+define(`msg_reg5', `g69')
+define(`msg_reg6', `g70')
+define(`msg_reg7', `g71')
+define(`msg_reg8', `g72')
+
+#endif
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+__PAK_OBJECT:
+ mov (16) pak_object_ud<1>:ud 0x0:ud {align1} ;
+ /* DW0 */
+ mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW0 ;
+ /* DW1 */
+ mov (1) pak_object1_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW1 ;
+ /* DW2 */
+ mul (1) pak_object2_ud<1>:ud width_in_mb<0,1,0>:uw mb_y<0,1,0>:ub {align1};
+ add (1) pak_object2_ud<1>:ud pak_object2_ud<0,1,0>:ud mb_x<0,1,0>:ub {align1};
+ shl (1) pak_object2_ud<1>:ud pak_object2_ud<0,1,0>:ud 6:uw {align1} ;
+ /* DW3 */
+ mov (1) pak_object3_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW3 ;
+ /* DW5 */
+ mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ;
+
+ and.z.f0.1 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_OBJECT {align1};
+
+__PAK_OBJECT_LOOP:
+ /* DW4 */
+ add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTER_DW4 {align1} ;
+ add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1};
+ cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1};
+ (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ;
+ (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ;
+
+ /* DW6 */
+ mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ;
+ (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW6 {align1} ;
+ cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1};
+ (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ;
+ add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ;
+
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (8) msg_reg1.0<1>:ud pak_object_ud<8,8,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_2,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
+
+ /* the new offset */
+ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 2:ud {align1} ;
+
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (4) msg_reg1.0<1>:ud pak_object8_ud<4,4,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
+
+ /* the new offset */
+ /* DW2 */
+ add (1) pak_object2_ud<1>:ud pak_object2_ud<0,1,0>:ud MFC_AVC_PAK_OBJECT_INTER_DW2 {align1} ;
+ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ;
+
+ add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -1:w {align1};
+ (-f0.0)jmpi (1) __PAK_OBJECT_LOOP ;
+
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+#include "mfc_batchbuffer.inc"
+#include "mfc_batchbuffer_head.asm"
+#include "mfc_batchbuffer_avc_inter.asm"
+#include "mfc_batchbuffer_tail.asm"
+#include "end_thread.asm"
+
--- /dev/null
+ { 0x00800001, 0x21000061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x21400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x21340231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 },
+ { 0x00000001, 0x21540231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 },
+ { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 },
+ { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x00800001, 0x23400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x23400061, 0x00000000, 0x71490009 },
+ { 0x00000001, 0x23440061, 0x00000000, 0x00000020 },
+ { 0x00000041, 0x23484521, 0x000000b4, 0x000000b1 },
+ { 0x00000040, 0x23484421, 0x00000348, 0x000000b0 },
+ { 0x00000009, 0x23482c21, 0x00000348, 0x00060006 },
+ { 0x00000001, 0x234c0061, 0x00000000, 0x014e0120 },
+ { 0x00000001, 0x23540061, 0x00000000, 0x000f000f },
+ { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 },
+ { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 },
+ { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 },
+ { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 },
+ { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 },
+ { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 },
+ { 0x00000001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00110001, 0x23580061, 0x02000000, 0x04000000 },
+ { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 },
+ { 0x00110001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x20200022, 0x008d0340, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0202 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000002 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x20200022, 0x00690360, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00000040, 0x23480c21, 0x00000348, 0x00000040 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffd6 },
+ { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e },
+ { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 },
+ { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x20200062, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x20240062, 0x00000000, 0x05000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 },
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+#include "mfc_batchbuffer.inc"
+#include "mfc_batchbuffer_head.asm"
+#include "mfc_batchbuffer_avc_inter.asm"
+#include "mfc_batchbuffer_tail.asm"
+#include "end_thread.asm"
+
--- /dev/null
+ { 0x00800001, 0x21000061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x21400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x21340231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 },
+ { 0x00000001, 0x21540231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 },
+ { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 },
+ { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x00800001, 0x23400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x23400061, 0x00000000, 0x71490009 },
+ { 0x00000001, 0x23440061, 0x00000000, 0x00000020 },
+ { 0x00000041, 0x23484521, 0x000000b4, 0x000000b1 },
+ { 0x00000040, 0x23484421, 0x00000348, 0x000000b0 },
+ { 0x00000009, 0x23482c21, 0x00000348, 0x00060006 },
+ { 0x00000001, 0x234c0061, 0x00000000, 0x014e0120 },
+ { 0x00000001, 0x23540061, 0x00000000, 0x000f000f },
+ { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 },
+ { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 },
+ { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 },
+ { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 },
+ { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 },
+ { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 },
+ { 0x00000001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00110001, 0x23580061, 0x02000000, 0x04000000 },
+ { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 },
+ { 0x00110001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0202 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000002 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x28200021, 0x00690360, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00000040, 0x23480c21, 0x00000348, 0x00000040 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffd6 },
+ { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e },
+ { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 },
+ { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x28200061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x28240061, 0x00000000, 0x05000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 },
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+__PAK_OBJECT:
+ mul (1) tmp_vme_output.8<1>:ud width_in_mb<0,1,0>:uw mb_y<0,1,0>:ub {align1};
+ add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud mb_x<0,1,0>:ub {align1};
+
+ mov (16) pak_object_ud<1>:ud 0x0:ud {align1} ;
+ mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW0 ;
+ mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ;
+
+ and.z.f0.1 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_OBJECT {align1};
+
+__PAK_OBJECT_LOOP:
+ mov (8) msg_reg0.0<1>:ud tmp_vme_output<8,8,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_read_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_READ,
+ OB_CONTROL_0,
+ BIND_IDX_VME_OUTPUT,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 1
+ rlen ob_read_wb_len_vme_intra
+ {align1};
+
+ /* DW4 */
+ add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTRA_DW4 {align1} ;
+ add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1};
+ cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1};
+ (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ;
+ (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ;
+
+ /* DW6 */
+ mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ;
+ (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW6 {align1} ;
+ cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1};
+ (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ;
+ add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ;
+
+ /* DW3 */
+ and (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud 0xFFFF {align1} ;
+ add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_OBJECT_INTRA_DW3 {align1} ;
+
+ /* DW7 */
+ mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ;
+
+ /* DW8 */
+ mov (1) pak_object8_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ;
+
+ /* DW9 */
+ and (1) pak_object9_ud<1>:ud ob_read_wb0.12<0,1,0>:ud 0xFC:ud {align1} ;
+
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (8) msg_reg1.0<1>:ud pak_object_ud<8,8,1>:ud {align1} ;
+
+ /* the new offset */
+ add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud 1:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_2,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
+
+ /* the new offset */
+ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 2:ud {align1} ;
+
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (4) msg_reg1.0<1>:ud pak_object8_ud<4,4,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
+
+ /* the new offset */
+ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ;
+
+ add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -1:w {align1};
+ (-f0.0)jmpi (1) __PAK_OBJECT_LOOP ;
+
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+#include "mfc_batchbuffer.inc"
+#include "mfc_batchbuffer_head.asm"
+#include "mfc_batchbuffer_avc_intra.asm"
+#include "mfc_batchbuffer_tail.asm"
+#include "end_thread.asm"
+
--- /dev/null
+ { 0x00800001, 0x21000061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x21400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x21340231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 },
+ { 0x00000001, 0x21540231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 },
+ { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 },
+ { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x00000041, 0x21084521, 0x000000b4, 0x000000b1 },
+ { 0x00000040, 0x21084421, 0x00000108, 0x000000b0 },
+ { 0x00800001, 0x23400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x23400061, 0x00000000, 0x71490009 },
+ { 0x00000001, 0x23540061, 0x00000000, 0x000f000f },
+ { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 },
+ { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 },
+ { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0000 },
+ { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 },
+ { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 },
+ { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 },
+ { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 },
+ { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 },
+ { 0x00000001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00110001, 0x23580061, 0x02000000, 0x04000000 },
+ { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 },
+ { 0x00110001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 },
+ { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff },
+ { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 },
+ { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 },
+ { 0x00000001, 0x23600021, 0x00000208, 0x00000000 },
+ { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x20200022, 0x008d0340, 0x00000000 },
+ { 0x00000040, 0x21080c21, 0x00000108, 0x00000001 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0202 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000002 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x20200022, 0x00690360, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffc8 },
+ { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e },
+ { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 },
+ { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 },
+ { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x20200062, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x20240062, 0x00000000, 0x05000000 },
+ { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 },
+ { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 },
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+#include "mfc_batchbuffer.inc"
+#include "mfc_batchbuffer_head.asm"
+#include "mfc_batchbuffer_avc_intra.asm"
+#include "mfc_batchbuffer_tail.asm"
+#include "end_thread.asm"
+
--- /dev/null
+ { 0x00800001, 0x21000061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x21400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x21340231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 },
+ { 0x00000001, 0x21540231, 0x00000014, 0x00000000 },
+ { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 },
+ { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 },
+ { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x00000041, 0x21084521, 0x000000b4, 0x000000b1 },
+ { 0x00000040, 0x21084421, 0x00000108, 0x000000b0 },
+ { 0x00800001, 0x23400061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x23400061, 0x00000000, 0x71490009 },
+ { 0x00000001, 0x23540061, 0x00000000, 0x000f000f },
+ { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 },
+ { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 },
+ { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180000 },
+ { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 },
+ { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 },
+ { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 },
+ { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 },
+ { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 },
+ { 0x00000001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00110001, 0x23580061, 0x02000000, 0x04000000 },
+ { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 },
+ { 0x00110001, 0x23580061, 0x00000000, 0x00000000 },
+ { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 },
+ { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff },
+ { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 },
+ { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 },
+ { 0x00000001, 0x23600021, 0x00000208, 0x00000000 },
+ { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 },
+ { 0x00000040, 0x21080c21, 0x00000108, 0x00000001 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0202 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000002 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x28200021, 0x00690360, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffc8 },
+ { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e },
+ { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 },
+ { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 },
+ { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 },
+ { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff },
+ { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee },
+ { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 },
+ { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 },
+ { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 },
+ { 0x00400001, 0x28200061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x28240061, 0x00000000, 0x05000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 },
+ { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 },
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+/*
+ * __START
+ */
+__START:
+ mov (16) tmp_reg0<1>:ud 0x0:ud {align1} ;
+ mov (16) tmp_reg2<1>:ud 0x0:ud {align1} ;
+
+ mov (1) tmp_slice_header.20<1>:ub thread_id_ub {align1}; /* dispatch id */
+ mov (1) tmp_slice_header.8<1>:ud head_offset<0,1,0>:ud {align1};
+ mov (1) tmp_mfc_batchbuffer.20<1>:ub thread_id_ub {align1}; /* dispatch id */
+ mov (1) tmp_mfc_batchbuffer.8<1>:ud batchbuffer_offset<0,1,0>:ud {align1};
+
+__HEAD:
+ and.z.f0.0 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_FIRST_OBJECT {align1};
+ (f0.0)jmpi (1) __PAK_OBJECT ;
+
+__HEAD_LOOP:
+ mov (8) msg_reg0.0<1>:ud tmp_slice_header<8,8,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_read_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_READ,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_SLICE_HEADER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 1
+ rlen ob_read_wb_len_slice_header
+ {align1};
+
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (8) msg_reg1.0<1>:ud ob_read_wb0<8,8,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
+
+ /* the new offset */
+ add (1) tmp_slice_header.8<1>:ud tmp_slice_header.8<0,1,0>:ud 1:ud {align1} ;
+ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ;
+
+ add.z.f0.0 (1) head_size<1>:w head_size<0,1,0>:w -1:w {align1};
+ (-f0.0)jmpi (1) __HEAD_LOOP ;
+
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Xiang Haihao <haihao.xiang@intel.com>
+ */
+
+__TAIL:
+ (f0.1)jmpi (1) __EXIT ;
+
+__TAIL_LOOP:
+ mov (8) msg_reg0.0<1>:ud tmp_slice_header<8,8,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_read_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_READ,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_SLICE_HEADER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 1
+ rlen ob_read_wb_len_slice_header
+ {align1};
+
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (8) msg_reg1.0<1>:ud ob_read_wb0<8,8,1>:ud {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
+
+ /* the new offset */
+ add (1) tmp_slice_header.8<1>:ud tmp_slice_header.8<0,1,0>:ud 1:ud {align1} ;
+ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ;
+
+ add.z.f0.0 (1) tail_size<1>:w tail_size<0,1,0>:w -1:w {align1};
+ (-f0.0)jmpi (1) __TAIL_LOOP ;
+
+
+__DONE:
+
+ and.z.f0.0 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_SLICE {align1};
+ (f0.0)jmpi (1) __EXIT ;
+
+/* bind index 5, write 1 oword, msg type: 8(OWord Block Write) */
+ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ;
+ mov (4) msg_reg1.0<1>:ud 0x0:ud {align1} ;
+ mov (1) msg_reg1.4<1>:ud MI_BATCH_BUFFER_END {align1} ;
+
+send (16)
+ msg_ind
+ ob_write_wb
+ null
+ data_port(
+ OB_CACHE_TYPE,
+ OB_WRITE,
+ OB_CONTROL_0,
+ BIND_IDX_MFC_BATCHBUFFER,
+ OB_WRITE_COMMIT_CATEGORY,
+ OB_HEADER_PRESENT
+ )
+ mlen 2
+ rlen ob_write_wb_length
+ {align1};
projects / platform / upstream / libva-intel-driver.git / commitdiff