arm64: dts: ls1012a: Add QSPI node properties

Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS,
LS1012A-FRDM and LS1012A-FRWY boards.

LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only
one can be accessed at a time.
LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M.
LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M.

Use generic compatibles as "jedec,spi-nor" for automatic detection of
flash. Configure RX and TX buswidth values as 2 as only two I/O lines are
available for data transfer.

Add ls1012a(si) node alongwith flash nodes.

Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
index f90c040..6770266 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -74,6 +74,21 @@
        };
 };
 
+&qspi {
+       status = "okay";
+
+       s25fs512s0: flash@0 {
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <50000000>;
+               m25p,fast-read;
+               reg = <0>;
+               spi-rx-bus-width = <2>;
+               spi-tx-bus-width = <2>;
+       };
+};
+
 &sai2 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
index 8749634..6290e2f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -23,3 +23,18 @@
 &i2c0 {
        status = "okay";
 };
+
+&qspi {
+       status = "okay";
+
+       w25q16dw0: flash@0 {
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               m25p,fast-read;
+               spi-max-frequency = <50000000>;
+               reg = <0>;
+               spi-rx-bus-width = <2>;
+               spi-tx-bus-width = <2>;
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index 2fb1cb1..449475a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -128,6 +128,21 @@
        };
 };
 
+&qspi {
+       status = "okay";
+
+       s25fs512s0: flash@0 {
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <50000000>;
+               m25p,fast-read;
+               reg = <0>;
+               spi-rx-bus-width = <2>;
+               spi-tx-bus-width = <2>;
+       };
+};
+
 &sai2 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
index 5edb1e1..d45c176 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -35,6 +35,21 @@
        status = "okay";
 };
 
+&qspi {
+       status = "okay";
+
+       s25fs512s0: flash@0 {
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <50000000>;
+               m25p,fast-read;
+               reg = <0>;
+               spi-rx-bus-width = <2>;
+               spi-tx-bus-width = <2>;
+       };
+};
+
 &sata {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 3379193..006e544 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -137,6 +137,19 @@
                #size-cells = <2>;
                ranges;
 
+               qspi: spi@1550000 {
+                       compatible = "fsl,ls1021a-qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x1550000 0x0 0x10000>,
+                               <0x0 0x40000000 0x0 0x10000000>;
+                       reg-names = "QuadSPI", "QuadSPI-memory";
+                       interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "qspi_en", "qspi";
+                       clocks = <&clockgen 4 0>, <&clockgen 4 0>;
+                       status = "disabled";
+               };
+
                esdhc0: esdhc@1560000 {
                        compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
                        reg = <0x0 0x1560000 0x0 0x10000>;