freedreno: Document CP_UNK_A6XX_55

Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 8e68f01..2cfa49f 100644 (file)
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -3432,18 +3432,6 @@ with a better name.
        </reg32>
 </domain>
 
-<domain name="CP_UNK_A6XX_55" width="32">
-       <reg32 offset="0" name="0">
-               <bitfield name="BASE_LO" low="0" high="31"/>
-       </reg32>
-       <reg32 offset="1" name="1">
-               <bitfield name="BASE_HI" low="0" high="16"/>
-       </reg32>
-       <reg32 offset="2" name="2">
-               <bitfield name="SIZE" low="0" high="15"/>
-       </reg32>
-</domain>
-
 <domain name="A6XX_PDC" width="32">
        <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
        <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>

diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index 3a1a034..48f77f6 100644 (file)
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -422,14 +422,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
        <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
        <value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
        <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
-<!--
-unknown a6xx opcodes:
-
-opcode: (null) (14) (5 dwords)
-opcode: (null) (55) (4 dwords)
-opcode: (null) (6d) (4 dwords)
- -->
-       <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
+       <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
 
        <!--
        Seems to always have the payload:
@@ -1387,13 +1380,22 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
                <value value="4" name="RM6_GMEM"/>
                <value value="5" name="RM6_BLIT2D"/>
                <value value="6" name="RM6_RESOLVE"/>
+               <value value="7" name="RM6_YIELD"/>
                <value value="0xc" name="RM6_BLIT2DSCALE"/>
+
+               <!--
+                       These values come from a6xx_set_marker() in the
+                       downstream kernel, and they can only be set by the kernel
+               -->
+               <value value="0xd" name="RM6_IB1LIST_START"/>
+               <value value="0xe" name="RM6_IB1LIST_END"/>
+               <!-- IFPC - inter-frame power collapse -->
+               <value value="0x100" name="RM6_IFPC_ENABLE"/>
+               <value value="0x101" name="RM6_IFPC_DISABLE"/>
        </enum>
        <reg32 offset="0" name="0">
                <bitfield name="MARKER" low="0" high="3"/>
-               <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
-               <!-- IFPC - inter-frame power collapse -->
-               <bitfield name="IFPC" pos="8" type="boolean"/>
+               <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
        </reg32>
 </domain>
 
@@ -1507,5 +1509,54 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
        </reg32>
 </domain>
 
+<domain name="CP_SET_CTXSWITCH_IB" width="32">
+       <doc>
+                Used by the userspace driver to set various IB's which are
+                executed during context save/restore for handling
+                state that isn't restored by the
+                context switch routine itself.
+       </doc>
+       <enum name="ctxswitch_ib">
+               <value name="RESTORE_IB" value="0">
+                       <doc>Executed unconditionally when switching back to the context.</doc>
+               </value>
+               <value name="YIELD_RESTORE_IB" value="1">
+                        <doc>
+                               Executed when switching back after switching
+                               away during execution of
+                               a CP_SET_MARKER packet with RM6_YIELD as the
+                               payload *and* the normal save routine was
+                               bypassed for a shorter one. I think this is
+                               connected to the "skipsaverestore" bit set by
+                               the kernel when preempting.
+                       </doc>
+               </value>
+               <value name="SAVE_IB" value="2">
+                        <doc>
+                               Executed when switching away from the context,
+                               except for context switches initiated via
+                               CP_YIELD.
+                        </doc>
+               </value>
+               <value name="RB_SAVE_IB" value="3">
+                       <doc>
+                               This can only be set by the RB (i.e. the kernel)
+                               and executes with protected mode off, but
+                               is otherwise similar to SAVE_IB.
+                       </doc>
+               </value>
+       </enum>
+       <reg32 offset="0" name="0">
+               <bitfield name="ADDR_LO" low="0" high="31"/>
+       </reg32>
+       <reg32 offset="1" name="1">
+               <bitfield name="ADDR_HI" low="0" high="31"/>
+       </reg32>
+       <reg32 offset="2" name="2">
+               <bitfield name="DWORDS" low="0" high="19" type="uint"/>
+               <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
+       </reg32>
+</domain>
+
 </database>