clk: rockchip: rk3399: Set 400MHz ddr clock

Add support for setting 400MHz ddr clock.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 2c00166..d9950c1 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
                dpll_cfg = (struct pll_div)
                {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
                break;
+       case 400 * MHz:
+               dpll_cfg = (struct pll_div)
+               {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+               break;
        case 666 * MHz:
                dpll_cfg = (struct pll_div)
                {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};