iommu/amd: Consolidate PPR log enablement
authorVasant Hegde <vasant.hegde@amd.com>
Wed, 28 Jun 2023 05:45:53 +0000 (05:45 +0000)
committerJoerg Roedel <jroedel@suse.de>
Fri, 14 Jul 2023 14:21:41 +0000 (16:21 +0200)
Move PPR log interrupt bit setting to iommu_enable_ppr_log(). Also
rearrange iommu_enable_ppr_log() such that PPREn bit is enabled
before enabling PPRLog and PPRInt bits. So that when PPRLog bit is
set it will clear the PPRLogOverflow bit and sets the PPRLogRun bit
in the IOMMU Status Register [MMIO Offset 2020h].

Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Link: https://lore.kernel.org/r/20230628054554.6131-3-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/amd/init.c

index 94c91b6..f26c077 100644 (file)
@@ -934,6 +934,8 @@ static void iommu_enable_ppr_log(struct amd_iommu *iommu)
        if (iommu->ppr_log == NULL)
                return;
 
+       iommu_feature_enable(iommu, CONTROL_PPR_EN);
+
        entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
 
        memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
@@ -944,7 +946,7 @@ static void iommu_enable_ppr_log(struct amd_iommu *iommu)
        writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
 
        iommu_feature_enable(iommu, CONTROL_PPRLOG_EN);
-       iommu_feature_enable(iommu, CONTROL_PPR_EN);
+       iommu_feature_enable(iommu, CONTROL_PPRINT_EN);
 }
 
 static void __init free_ppr_log(struct amd_iommu *iommu)
@@ -2526,8 +2528,6 @@ enable_faults:
 
        iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
 
-       if (iommu->ppr_log != NULL)
-               iommu_feature_enable(iommu, CONTROL_PPRINT_EN);
        return 0;
 }