I took the "Permitted"/"Not Permitted" combo from the `Tag_ARM_ISA_use` case (GNU tools print "Yes").
Reviewed By: compnerd, MaskRay, simon_tatham
Differential Revision: https://reviews.llvm.org/D90305
}
Error ARMAttributeParser::THUMB_ISA_use(AttrType tag) {
- static const char *strings[] = {"Not Permitted", "Thumb-1", "Thumb-2"};
+ static const char *strings[] = {"Not Permitted", "Thumb-1", "Thumb-2", "Permitted"};
return parseStringAttribute("THUMB_ISA_use", tag, makeArrayRef(strings));
}
// RUN: llvm-mc -triple armv6m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v6M
// RUN: llvm-mc -triple armv7m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7M
// RUN: llvm-mc -triple armv7a -mcpu=cortex-a15 < %s -arm-add-build-attributes | FileCheck %s --check-prefix=Cortex-A15
+// RUN: llvm-mc -triple armv8m.base < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v8M_Baseline
+// RUN: llvm-mc -triple armv8m.main < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v8M_Mainline
// This isn't intended to be a through check of the build attributes emitted
// for each target (that's tested elsewhere), but just to check that the
// v7M: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
// v7M: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+// v8M_Baseline-NOT: .cpu
+// v8M_Baseline: .eabi_attribute 6, 16 @ Tag_CPU_arch
+// v8M_Baseline: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
+// v8M_Baseline: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
+// v8M_Baseline: .eabi_attribute 9, 3 @ Tag_THUMB_ISA_use
+// v8M_Baseline: .eabi_attribute 34, 0 @ Tag_CPU_unaligned_access
+
+// v8M_Mainline-NOT: .cpu
+// v8M_Mainline: .eabi_attribute 6, 17 @ Tag_CPU_arch
+// v8M_Mainline: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
+// v8M_Mainline: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
+// v8M_Mainline: .eabi_attribute 9, 3 @ Tag_THUMB_ISA_use
+// v8M_Mainline: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+
// Cortex-A15: .cpu cortex-a15
// Cortex-A15: .eabi_attribute 6, 10 @ Tag_CPU_arch
// Cortex-A15: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
--- /dev/null
+@ Test the .arch directive for armv8m
+
+@ This test case will check the default .ARM.attributes value for the
+@ armv8-a architecture when using the armv8m.base alias.
+
+@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
+@ RUN: | FileCheck %s -check-prefix CHECK-ASM
+@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
+@ RUN: | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
+
+ .syntax unified
+ .arch armv8m.base
+
+@ CHECK-ASM: .arch armv8-m.base
+
+@ CHECK-ATTR: FileAttributes {
+@ CHECK-ATTR: Attribute {
+@ CHECK-ATTR: TagName: CPU_name
+@ CHECK-ATTR: Value: 8-M.Baseline
+@ CHECK-ATTR: }
+@ CHECK-ATTR: Attribute {
+@ CHECK-ATTR: TagName: CPU_arch
+@ CHECK-ATTR: Description: ARM v8
+@ CHECK-ATTR: }
+@ CHECK-ATTR: Attribute {
+@ CHECK-ATTR: TagName: CPU_arch_profile
+@ CHECK-ATTR: Description: Microcontroller
+@ CHECK-ATTR: }
+@ CHECK-ATTR: Attribute {
+@ CHECK-ATTR: TagName: THUMB_ISA_use
+@ CHECK-ATTR: Description: Permitted
+@ CHECK-ATTR: }
+@ CHECK-ATTR: }
+
ARMBuildAttrs::Not_Allowed));
EXPECT_TRUE(testBuildAttr(9, 1, ARMBuildAttrs::THUMB_ISA_use,
ARMBuildAttrs::Allowed));
+ EXPECT_TRUE(testBuildAttr(9, 2, ARMBuildAttrs::THUMB_ISA_use,
+ ARMBuildAttrs::AllowThumb32));
+ EXPECT_TRUE(testBuildAttr(9, 3, ARMBuildAttrs::THUMB_ISA_use,
+ ARMBuildAttrs::AllowThumbDerived));
}
TEST(FPArchBuildAttr, testBuildAttr) {