[RISCV] Add H extension

`h` was the prefix of multi-letter extension name, but it become a
extension name in later RISC-V isa spec.

Fortunately we don't have any extension really defined is prefixed
with `h`, so we can just change that.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136817

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index c514ad889d0b2b50418942df50931461aab452d8..91ab4219ea344572e90a67f39e568cd34345a946 100644 (file)
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -46,6 +46,7 @@
 // CHECK-NOT: __riscv_xventanacondops
 // CHECK-NOT: __riscv_zcd
 // CHECK-NOT: __riscv_zcf
+// CHECK-NOT: __riscv_h
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -449,6 +450,12 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
 // CHECK-SVINVAL-EXT: __riscv_svinval 1000000{{$}}
 
+// RUN: %clang -target riscv32 -march=rv32ih -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s
+// RUN: %clang -target riscv64 -march=rv64ih -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s
+// CHECK-H-EXT: __riscv_h 1000000{{$}}
+
 // RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
 // CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 25dc17d44c89e26a720a6d67569d6ac52b6518ff..3ba0d887ca77e48608e7bd324a370b85f6143f54 100644 (file)
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -51,6 +51,7 @@ on support follow.
      ``C``            Supported
      ``D``            Supported
      ``F``            Supported
+     ``H``            Assembly Support
      ``M``            Supported
      ``Svinval``      Assembly Support
      ``Svnapot``      Assembly Support

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a55837aa3f808522553705cc3cd22201b52a4f6..d82f337feb534ac51f196d971f85bd5cdd230948 100644 (file)
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -37,7 +37,7 @@ struct RISCVSupportedExtension {
 
 } // end anonymous namespace
 
-static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvn";
+static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
 
 static const RISCVSupportedExtension SupportedExtensions[] = {
     {"i", RISCVExtensionVersion{2, 0}},
@@ -48,6 +48,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"d", RISCVExtensionVersion{2, 0}},
     {"c", RISCVExtensionVersion{2, 0}},
 
+    {"h", RISCVExtensionVersion{1, 0}},
+
     {"zihintpause", RISCVExtensionVersion{2, 0}},
 
     {"zfhmin", RISCVExtensionVersion{1, 0}},
@@ -284,17 +286,14 @@ static int multiLetterExtensionRank(const std::string &ExtName) {
   case 's':
     HighOrder = 0;
     break;
-  case 'h':
-    HighOrder = 1;
-    break;
   case 'z':
-    HighOrder = 2;
+    HighOrder = 1;
     // `z` extension must be sorted by canonical order of second letter.
     // e.g. zmx has higher rank than zax.
     LowOrder = singleLetterExtensionRank(ExtName[1]);
     break;
   case 'x':
-    HighOrder = 3;
+    HighOrder = 2;
     break;
   default:
     llvm_unreachable("Unknown prefix for multi-char extension");
@@ -611,8 +610,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
 
     // The order is OK, then push it into features.
     // TODO: Use version number when setting target features
-    // Currently LLVM supports only "mafdcv".
-    StringRef SupportedStandardExtension = "mafdcv";
+    // Currently LLVM supports only "mafdcvh".
+    StringRef SupportedStandardExtension = "mafdcvh";
     if (!SupportedStandardExtension.contains(C))
       return createStringError(errc::invalid_argument,
                                "unsupported standard user-level extension '%c'",

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index eb851a7e1ed92b0885a123503e2c000493755054..0e9b88b7876f44b322c5491b32f00c31d4bae41a 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -51,6 +51,14 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
                            AssemblerPredicate<(all_of FeatureStdExtD),
                            "'D' (Double-Precision Floating-Point)">;
 
+def FeatureStdExtH
+    : SubtargetFeature<"h", "HasStdExtH", "true",
+                       "'H' (Hypervisor)">;
+
+def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
+                           AssemblerPredicate<(all_of FeatureStdExtH),
+                           "'H' (Hypervisor)">;
+
 def FeatureStdExtZihintpause
     : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
                        "'zihintpause' (Pause Hint)">;

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9885a3e555ad0faaf2b9aa7d571ad33d6433cc0c..c699a94943d82084d3d6b6f5f023d9e65ba2e3ac 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -833,6 +833,8 @@ def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
 } // Predicates = [HasStdExtSvinval]
 
 def SFENCE_VMA  : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>;
+
+let Predicates = [HasStdExtH] in {
 def HFENCE_VVMA : Priv_rr<"hfence.vvma", 0b0010001>, Sched<[]>;
 def HFENCE_GVMA : Priv_rr<"hfence.gvma", 0b0110001>, Sched<[]>;
 
@@ -846,8 +848,8 @@ def HLVX_WU : HLoad_r<0b0110100, 0b00011, "hlvx.wu">, Sched<[]>;
 def HSV_B   : HStore_rr<0b0110001, "hsv.b">, Sched<[]>;
 def HSV_H   : HStore_rr<0b0110011, "hsv.h">, Sched<[]>;
 def HSV_W   : HStore_rr<0b0110101, "hsv.w">, Sched<[]>;
-
-let Predicates = [IsRV64] in {
+}
+let Predicates = [IsRV64, HasStdExtH] in {
 def HLV_WU  : HLoad_r<0b0110100, 0b00001, "hlv.wu">, Sched<[]>;
 def HLV_D   : HLoad_r<0b0110110, 0b00000, "hlv.d">, Sched<[]>;
 def HSV_D   : HStore_rr<0b0110111, "hsv.d">, Sched<[]>;

diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 4acb1ad2fc3bb4c3e609d23e2dffc05993f1fcb8..664bc0ed368cdf50ea9daa3ceb9dc94db657f7ed 100644 (file)
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -16,6 +16,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - | FileCheck --check-prefix=RV32V %s
+; RUN: llc -mtriple=riscv32 -mattr=+h %s -o - | FileCheck --check-prefix=RV32H %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s
@@ -57,6 +58,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - | FileCheck --check-prefix=RV64V %s
+; RUN: llc -mtriple=riscv64 -mattr=+h %s -o - | FileCheck --check-prefix=RV64H %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s
@@ -102,6 +104,7 @@
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32H: .attribute 5, "rv32i2p0_h1p0"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
 ; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
@@ -143,6 +146,7 @@
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64H: .attribute 5, "rv64i2p0_h1p0"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
 ; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"

diff --git a/llvm/test/MC/RISCV/priv-aliases-valid.s b/llvm/test/MC/RISCV/priv-aliases-valid.s
deleted file mode 100644 (file)
index 0f3b2c0..0000000
--- a/llvm/test/MC/RISCV/priv-aliases-valid.s
+++ /dev/null
@@ -1,50 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -M no-aliases -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -M no-aliases -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
-
-# CHECK-INST: hlv.b a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x05,0x60]
-hlv.b   a0, 0(a1)
-
-# CHECK-INST: hlv.bu a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x15,0x60]
-hlv.bu  a0, 0(a1)
-
-# CHECK-INST: hlv.h a1, (a2)
-# CHECK: encoding: [0xf3,0x45,0x06,0x64]
-hlv.h   a1, 0(a2)
-
-# CHECK-INST: hlv.hu a1, (a1)
-# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
-hlv.hu  a1, 0(a1)
-
-# CHECK-INST: hlvx.hu a1, (a2)
-# CHECK: encoding: [0xf3,0x45,0x36,0x64]
-hlvx.hu a1, 0(a2)
-
-# CHECK-INST: hlv.w a2, (a2)
-# CHECK: encoding: [0x73,0x46,0x06,0x68]
-hlv.w   a2, 0(a2)
-
-# CHECK-INST: hlvx.wu a2, (a3)
-# CHECK: encoding: [0x73,0xc6,0x36,0x68]
-hlvx.wu a2, 0(a3)
-
-# CHECK-INST: hsv.b a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
-hsv.b   a0, 0(a1)
-
-# CHECK-INST: hsv.h a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
-hsv.h   a0, 0(a1)
-
-# CHECK-INST: hsv.w a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x6a]
-hsv.w   a0, 0(a1)

diff --git a/llvm/test/MC/RISCV/priv-rv64-valid.s b/llvm/test/MC/RISCV/priv-rv64-valid.s
deleted file mode 100644 (file)
index 76992a1..0000000
--- a/llvm/test/MC/RISCV/priv-rv64-valid.s
+++ /dev/null
@@ -1,38 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:     | llvm-objdump -M no-aliases -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
-
-# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
-# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
-
-# CHECK-INST: hlv.wu a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x15,0x68]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-hlv.wu   a0, (a1)
-
-# CHECK-INST: hlv.wu a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x15,0x68]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-hlv.wu   a0, 0(a1)
-
-# CHECK-INST: hlv.d a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-hlv.d  a0, (a1)
-
-# CHECK-INST: hlv.d a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-hlv.d  a0, 0(a1)
-
-# CHECK-INST: hsv.d a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-hsv.d   a0, (a1)
-
-# CHECK-INST: hsv.d a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-hsv.d   a0, 0(a1)

diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s
index a40950810aedeaf65398a76c2f42efa7a1eaefe3..323acc500d383fa6dbf21f78898d86b9d3b81eac 100644 (file)
--- a/llvm/test/MC/RISCV/priv-valid.s
+++ b/llvm/test/MC/RISCV/priv-valid.s
@@ -48,75 +48,3 @@ sfence.w.inval
 # CHECK-INST: sfence.inval.ir
 # CHECK: encoding: [0x73,0x00,0x10,0x18]
 sfence.inval.ir
-
-# CHECK-INST: hfence.vvma zero, zero
-# CHECK: encoding: [0x73,0x00,0x00,0x22]
-hfence.vvma zero, zero
-
-# CHECK-INST: hfence.vvma a0, a1
-# CHECK: encoding: [0x73,0x00,0xb5,0x22]
-hfence.vvma a0, a1
-
-# CHECK-INST: hfence.gvma zero, zero
-# CHECK: encoding: [0x73,0x00,0x00,0x62]
-hfence.gvma zero, zero
-
-# CHECK-INST: hfence.gvma a0, a1
-# CHECK: encoding: [0x73,0x00,0xb5,0x62]
-hfence.gvma a0, a1
-
-# CHECK-INST: hinval.vvma zero, zero
-# CHECK: encoding: [0x73,0x00,0x00,0x26]
-hinval.vvma zero, zero
-
-# CHECK-INST: hinval.vvma a0, a1
-# CHECK: encoding: [0x73,0x00,0xb5,0x26]
-hinval.vvma a0, a1
-
-# CHECK-INST: hinval.gvma zero, zero
-# CHECK: encoding: [0x73,0x00,0x00,0x66]
-hinval.gvma zero, zero
-
-# CHECK-INST: hinval.gvma a0, a1
-# CHECK: encoding: [0x73,0x00,0xb5,0x66]
-hinval.gvma a0, a1
-
-# CHECK-INST: hlv.b a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x05,0x60]
-hlv.b   a0, (a1)
-
-# CHECK-INST: hlv.bu a0, (a1)
-# CHECK: encoding: [0x73,0xc5,0x15,0x60]
-hlv.bu  a0, (a1)
-
-# CHECK-INST: hlv.h a1, (a2)
-# CHECK: encoding: [0xf3,0x45,0x06,0x64]
-hlv.h   a1, (a2)
-
-# CHECK-INST: hlv.hu a1, (a1)
-# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
-hlv.hu  a1, (a1)
-
-# CHECK-INST: hlvx.hu a1, (a2)
-# CHECK: encoding: [0xf3,0x45,0x36,0x64]
-hlvx.hu a1, (a2)
-
-# CHECK-INST: hlv.w a2, (a2)
-# CHECK: encoding: [0x73,0x46,0x06,0x68]
-hlv.w   a2, (a2)
-
-# CHECK-INST: hlvx.wu a2, (a3)
-# CHECK: encoding: [0x73,0xc6,0x36,0x68]
-hlvx.wu a2, (a3)
-
-# CHECK-INST: hsv.b a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
-hsv.b   a0, (a1)
-
-# CHECK-INST: hsv.h a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
-hsv.h   a0, (a1)
-
-# CHECK-INST: hsv.w a0, (a1)
-# CHECK: encoding: [0x73,0xc0,0xa5,0x6a]
-hsv.w   a0, (a1)

diff --git a/llvm/test/MC/RISCV/rv32h-invalid.s b/llvm/test/MC/RISCV/rv32h-invalid.s
new file mode 100644 (file)
index 0000000..3dcfea4
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32h-invalid.s
@@ -0,0 +1,12 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+h < %s 2>&1 \
+# RUN:     | FileCheck %s -check-prefixes=CHECK-OFFSET
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
+# RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-OFFSET
+
+hfence.vvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hlv.h   a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hlv.wu   a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor), RV64I Base Instruction Set
+
+hlv.b   a0, 100(a1) # CHECK-OFFSET: :[[@LINE]]:13: error: optional integer offset must be 0

diff --git a/llvm/test/MC/RISCV/rv32ih-aliases-valid.s b/llvm/test/MC/RISCV/rv32ih-aliases-valid.s
new file mode 100644 (file)
index 0000000..85af8cf
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32ih-aliases-valid.s
@@ -0,0 +1,70 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-ALIAS-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-ALIAS-INST %s
+# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv32 < %s \
+# RUN:     | llvm-objdump --mattr=+h -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS-INST %s
+# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv64 < %s \
+# RUN:     | llvm-objdump --mattr=+h -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS-INST %s
+
+# CHECK-ALIAS-INST: hfence.gvma
+# CHECK-NOALIAS-INST: hfence.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x62]
+hfence.gvma
+
+# CHECK-ALIAS-INST: hfence.gvma a0
+# CHECK-NOALIAS-INST: hfence.gvma a0, zero
+# CHECK: encoding: [0x73,0x00,0x05,0x62]
+hfence.gvma a0
+
+# CHECK-ALIAS-INST: hfence.vvma
+# CHECK-NOALIAS-INST: hfence.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x22]
+hfence.vvma
+
+# CHECK-ALIAS-INST: hfence.vvma a0
+# CHECK-NOALIAS-INST: hfence.vvma a0, zero
+# CHECK: encoding: [0x73,0x00,0x05,0x22]
+hfence.vvma a0
+
+# CHECK-INST: hlv.b a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x60]
+hlv.b   a0, 0(a1)
+
+# CHECK-INST: hlv.bu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x60]
+hlv.bu  a0, 0(a1)
+
+# CHECK-INST: hlv.h a1, (a2)
+# CHECK: encoding: [0xf3,0x45,0x06,0x64]
+hlv.h   a1, 0(a2)
+
+# CHECK-INST: hlv.hu a1, (a1)
+# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
+hlv.hu  a1, 0(a1)
+
+# CHECK-INST: hlvx.hu a1, (a2)
+# CHECK: encoding: [0xf3,0x45,0x36,0x64]
+hlvx.hu a1, 0(a2)
+
+# CHECK-INST: hlv.w a2, (a2)
+# CHECK: encoding: [0x73,0x46,0x06,0x68]
+hlv.w   a2, 0(a2)
+
+# CHECK-INST: hlvx.wu a2, (a3)
+# CHECK: encoding: [0x73,0xc6,0x36,0x68]
+hlvx.wu a2, 0(a3)
+
+# CHECK-INST: hsv.b a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
+hsv.b   a0, 0(a1)
+
+# CHECK-INST: hsv.h a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
+hsv.h   a0, 0(a1)
+
+# CHECK-INST: hsv.w a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6a]
+hsv.w   a0, 0(a1)

diff --git a/llvm/test/MC/RISCV/rv32ih-valid.s b/llvm/test/MC/RISCV/rv32ih-valid.s
new file mode 100644 (file)
index 0000000..6f80a24
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32ih-valid.s
@@ -0,0 +1,66 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+h < %s \
+# RUN:     | llvm-objdump --mattr=+h -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+h < %s \
+# RUN:     | llvm-objdump --mattr=+h -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: hfence.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x22]
+hfence.vvma zero, zero
+
+# CHECK-INST: hfence.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x22]
+hfence.vvma a0, a1
+
+# CHECK-INST: hfence.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x62]
+hfence.gvma zero, zero
+
+# CHECK-INST: hfence.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x62]
+hfence.gvma a0, a1
+
+# CHECK-INST: hlv.b a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x60]
+hlv.b   a0, (a1)
+
+# CHECK-INST: hlv.bu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x60]
+hlv.bu  a0, (a1)
+
+# CHECK-INST: hlv.h a1, (a2)
+# CHECK: encoding: [0xf3,0x45,0x06,0x64]
+hlv.h   a1, (a2)
+
+# CHECK-INST: hlv.hu a1, (a1)
+# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
+hlv.hu  a1, (a1)
+
+# CHECK-INST: hlvx.hu a1, (a2)
+# CHECK: encoding: [0xf3,0x45,0x36,0x64]
+hlvx.hu a1, (a2)
+
+# CHECK-INST: hlv.w a2, (a2)
+# CHECK: encoding: [0x73,0x46,0x06,0x68]
+hlv.w   a2, (a2)
+
+# CHECK-INST: hlvx.wu a2, (a3)
+# CHECK: encoding: [0x73,0xc6,0x36,0x68]
+hlvx.wu a2, (a3)
+
+# CHECK-INST: hsv.b a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
+hsv.b   a0, (a1)
+
+# CHECK-INST: hsv.h a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
+hsv.h   a0, (a1)
+
+# CHECK-INST: hsv.w a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6a]
+hsv.w   a0, (a1)

diff --git a/llvm/test/MC/RISCV/rv64h-invalid.s b/llvm/test/MC/RISCV/rv64h-invalid.s
new file mode 100644 (file)
index 0000000..4838cbd
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64h-invalid.s
@@ -0,0 +1,12 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+h < %s 2>&1 \
+# RUN:     | FileCheck %s -check-prefixes=CHECK-OFFSET
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
+# RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-OFFSET
+
+hfence.vvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hlv.h   a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hlv.wu   a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hlv.b   a0, 100(a1) # CHECK-OFFSET: :[[@LINE]]:13: error: optional integer offset must be 0

diff --git a/llvm/test/MC/RISCV/rv64ih-valid.s b/llvm/test/MC/RISCV/rv64ih-valid.s
new file mode 100644 (file)
index 0000000..be8ccf9
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64ih-valid.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv64 < %s \
+# RUN:     | llvm-objdump --mattr=+h -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# RUN: not llvm-mc -triple riscv32 -mattr=+h < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-INST: hlv.wu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x68]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+hlv.wu   a0, (a1)
+
+# CHECK-INST: hlv.wu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x68]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+hlv.wu   a0, 0(a1)
+
+# CHECK-INST: hlv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+hlv.d  a0, (a1)
+
+# CHECK-INST: hlv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+hlv.d  a0, 0(a1)
+
+# CHECK-INST: hsv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+hsv.d   a0, (a1)
+
+# CHECK-INST: hsv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+hsv.d   a0, 0(a1)

diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
index 69e4d31740a577e006d2a9297d846b831999ad50..8b166d48992eeba1ea7e88e783610b08e35943f0 100644 (file)
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -256,18 +256,6 @@ sfence.vma
 # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero
 # CHECK-S-OBJ: sfence.vma a0
 sfence.vma a0
-# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero
-# CHECK-S-OBJ: hfence.gvma
-hfence.gvma
-# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero
-# CHECK-S-OBJ: hfence.gvma a0
-hfence.gvma a0
-# CHECK-S-OBJ-NOALIAS: hfence.vvma zero, zero
-# CHECK-S-OBJ: hfence.vvma
-hfence.vvma
-# CHECK-S-OBJ-NOALIAS: hfence.vvma a0, zero
-# CHECK-S-OBJ: hfence.vvma a0
-hfence.vvma a0
 
 # The following aliases are accepted as input but the canonical form
 # of the instruction will always be printed.