imx8m: add clk support for i.MX8MN

i.MX8MN has similar architecture with i.MX8MM, so it could reuse
the clock code of i.MX8MM, but i.MX8MN has different CCM root
configurations, so need a separate root entry.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index dded6e0..c910b61 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -9,7 +9,7 @@
 
 #ifdef CONFIG_IMX8MQ
 #include <asm/arch/clock_imx8mq.h>
-#elif defined(CONFIG_IMX8MM)
+#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
 #include <asm/arch/clock_imx8mm.h>
 #else
 #error "Error no clock.h"

diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index 305514a..76c73ed 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -52,6 +52,83 @@ enum pll_clocks {
        ANATOP_DRAM_PLL,
 };
 
+#ifdef CONFIG_IMX8MN
+enum clk_root_index {
+       ARM_A53_CLK_ROOT                = 0,
+       ARM_M7_CLK_ROOT                 = 1,
+       GPU_CORE_CLK_ROOT               = 3,
+       GPU_SHADER_CLK_ROOT             = 4,
+       MAIN_AXI_CLK_ROOT               = 16,
+       ENET_AXI_CLK_ROOT               = 17,
+       NAND_USDHC_BUS_CLK_ROOT         = 18,
+       DISPLAY_AXI_CLK_ROOT            = 20,
+       DISPLAY_APB_CLK_ROOT            = 21,
+       USB_BUS_CLK_ROOT                = 23,
+       GPU_AXI_CLK_ROOT                = 24,
+       GPU_AHB_CLK_ROOT                = 25,
+       NOC_CLK_ROOT                    = 26,
+       AHB_CLK_ROOT                    = 32,
+       IPG_CLK_ROOT                    = 33,
+       AUDIO_AHB_CLK_ROOT              = 34,
+       DRAM_SEL_CFG                    = 48,
+       CORE_SEL_CFG                    = 49,
+       DRAM_ALT_CLK_ROOT               = 64,
+       DRAM_APB_CLK_ROOT               = 65,
+       DISPLAY_PIXEL_CLK_ROOT          = 74,
+       SAI2_CLK_ROOT                   = 76,
+       SAI3_CLK_ROOT                   = 77,
+       SAI5_CLK_ROOT                   = 79,
+       SAI6_CLK_ROOT                   = 80,
+       SPDIF1_CLK_ROOT                 = 81,
+       ENET_REF_CLK_ROOT               = 83,
+       ENET_TIMER_CLK_ROOT             = 84,
+       ENET_PHY_REF_CLK_ROOT           = 85,
+       NAND_CLK_ROOT                   = 86,
+       QSPI_CLK_ROOT                   = 87,
+       USDHC1_CLK_ROOT                 = 88,
+       USDHC2_CLK_ROOT                 = 89,
+       I2C1_CLK_ROOT                   = 90,
+       I2C2_CLK_ROOT                   = 91,
+       I2C3_CLK_ROOT                   = 92,
+       I2C4_CLK_ROOT                   = 93,
+       UART1_CLK_ROOT                  = 94,
+       UART2_CLK_ROOT                  = 95,
+       UART3_CLK_ROOT                  = 96,
+       UART4_CLK_ROOT                  = 97,
+       USB_CORE_REF_CLK_ROOT           = 98,
+       USB_PHY_REF_CLK_ROOT            = 99,
+       GIC_CLK_ROOT                    = 100,
+       ECSPI1_CLK_ROOT                 = 101,
+       ECSPI2_CLK_ROOT                 = 102,
+       PWM1_CLK_ROOT                   = 103,
+       PWM2_CLK_ROOT                   = 104,
+       PWM3_CLK_ROOT                   = 105,
+       PWM4_CLK_ROOT                   = 106,
+       GPT1_CLK_ROOT                   = 107,
+       GPT2_CLK_ROOT                   = 108,
+       GPT3_CLK_ROOT                   = 109,
+       GPT4_CLK_ROOT                   = 110,
+       GPT5_CLK_ROOT                   = 111,
+       GPT6_CLK_ROOT                   = 112,
+       TRACE_CLK_ROOT                  = 113,
+       WDOG_CLK_ROOT                   = 114,
+       WRCLK_CLK_ROOT                  = 115,
+       IPP_DO_CLKO1                    = 116,
+       IPP_DO_CLKO2                    = 117,
+       MIPI_DSI_CORE_CLK_ROOT          = 118,
+       DISPLAY_DSI_PHY_REF_CLK_ROOT    = 119,
+       MIPI_DSI_DBI_CLK_ROOT           = 120,
+       USDHC3_CLK_ROOT                 = 121,
+       DISPLAY_CAMERA_PIXEL_CLK_ROOT   = 122,
+       MIPI_CSI1_PHY_REF_CLK_ROOT      = 123,
+       MIPI_CSI2_PHY_REF_CLK_ROOT      = 126,
+       MIPI_CSI2_ESC_CLK_ROOT          = 127,
+       ECSPI3_CLK_ROOT                 = 131,
+       PDM_CLK_ROOT                    = 132,
+       SAI7_CLK_ROOT                   = 134,
+       CLK_ROOT_MAX,
+};
+#else
 enum clk_root_index {
        ARM_A53_CLK_ROOT                = 0,
        ARM_M4_CLK_ROOT                 = 1,
@@ -148,6 +225,7 @@ enum clk_root_index {
        VPU_H1_CLK_ROOT                 = 133,
        CLK_ROOT_MAX,
 };
+#endif
 
 enum clk_root_src {
        OSC_24M_CLK,

diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index 92184f3..db4ba30 100644 (file)
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -5,4 +5,4 @@
 obj-y += lowlevel_init.o
 obj-y += clock_slice.o soc.o
 obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
-obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
+obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN) += clock_imx8mm.o

diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 780f643..09c5615 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -475,7 +475,7 @@ static struct clk_root_map root_array[] = {
         {DRAM_PLL1_CLK}
        },
 };
-#elif defined(CONFIG_IMX8MM)
+#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
 static struct clk_root_map root_array[] = {
        {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
         {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
@@ -487,11 +487,13 @@ static struct clk_root_map root_array[] = {
          SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
          AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
        },
+#ifdef CONFIG_IMX8MM
        {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
         {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
          SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
          SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
        },
+#endif
        {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
         {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
          SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,