util_range_set_empty(&res->valid_buffer_range);
res->TC_L2_dirty = false;
+ /* Set expected VRAM and GART usage for the buffer. */
+ res->vram_usage = 0;
+ res->gart_usage = 0;
+
+ if (res->domains & RADEON_DOMAIN_VRAM)
+ res->vram_usage = size;
+ else if (res->domains & RADEON_DOMAIN_GTT)
+ res->gart_usage = size;
+
+ /* Print debug information. */
if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
res->gpu_address, res->gpu_address + res->buf->size,
uint64_t vram = 0, gtt = 0;
if (dst) {
- if (dst->domains & RADEON_DOMAIN_VRAM)
- vram += dst->buf->size;
- else if (dst->domains & RADEON_DOMAIN_GTT)
- gtt += dst->buf->size;
+ vram += dst->vram_usage;
+ gtt += dst->gart_usage;
}
if (src) {
- if (src->domains & RADEON_DOMAIN_VRAM)
- vram += src->buf->size;
- else if (src->domains & RADEON_DOMAIN_GTT)
- gtt += src->buf->size;
+ vram += src->vram_usage;
+ gtt += src->gart_usage;
}
/* Flush the GFX IB if DMA depends on it. */
* In practice this gave very good estimate (+/- 10% of the target
* memory limit).
*/
- if (rr->domains & RADEON_DOMAIN_VRAM)
- rctx->vram += rr->buf->size;
- else if (rr->domains & RADEON_DOMAIN_GTT)
- rctx->gtt += rr->buf->size;
+ rctx->vram += rr->vram_usage;
+ rctx->gtt += rr->gart_usage;
}
/*