Before I start to make a complete mess out of this, crank up
the paranoia level a bit.
v2: Kill the has_pch_encoder check in put_shared_dpll - it's invalid
as spotted by Ville since we currently only put the dpll when we
already have the new pipe config. So a direct pch port -> cpu edp
transition will hit this.
v3: Now that I've lifted my blinders add the WARN_ON Ville requested.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
assert_pch_pll_enabled(dev_priv, pll, NULL);
return;
}
+ WARN_ON(pll->on);
DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
}
assert_pch_pll_enabled(dev_priv, pll, NULL);
+ WARN_ON(!pll->on);
if (--pll->active)
return;
return;
}
- --pll->refcount;
+ if (--pll->refcount == 0) {
+ WARN_ON(pll->on);
+ WARN_ON(pll->active);
+ }
+
intel_crtc->pch_pll = NULL;
}