use FileCheck and auto-check-generation script for exact checking

1. Removed the run line for mingw32 and made the Darwin triples unknown.
   This is a test of 32-bit vs. 64-bit platform and the underlying hardware.
   We have other tests for checking behavioral differences of the OS platform.

2. Changed the CPU specifiers to the attributes they were meant to represent.
   Any CPU that doesn't have SSE4.2 is assumed to have slow unaligned 16-byte accesses,
   so it won't use those here.

3. Although the stores really could all be CHECK-DAG, I left them as CHECK-NEXT to
   show the strange behavior of the instruction scheduler in the SLOW_32 case.

4. The odd-looking instructions are due to the use of a null pointer in the IR, so
   we have integer immediate store addresses. Cute.

llvm-svn: 264796

diff --git a/llvm/test/CodeGen/X86/memset64-on-x86-32.ll b/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
index 8cfa032..610986c 100644 (file)
--- a/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
+++ b/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
@@ -1,12 +1,57 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin   -mcpu=nehalem | grep movups | count 5
-; RUN: llc < %s -mtriple=i386-apple-darwin   -mcpu=core2   | grep movl   | count 20
-; RUN: llc < %s -mtriple=i386-pc-mingw32   -mcpu=core2   | grep movl   | count 20
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2   | grep movq   | count 10
+; NOTE: Assertions have been autogenerated by update_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-unknown   -mattr=sse4.2 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown   -mattr=ssse3   | FileCheck %s --check-prefix=SLOW_32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=ssse3   | FileCheck %s --check-prefix=SLOW_64
 
 define void @bork() nounwind {
-entry:
+; FAST-LABEL: bork:
+; FAST:         xorps %xmm0, %xmm0
+; FAST-NEXT:    movups %xmm0, 64
+; FAST-NEXT:    movups %xmm0, 48
+; FAST-NEXT:    movups %xmm0, 32
+; FAST-NEXT:    movups %xmm0, 16
+; FAST-NEXT:    movups %xmm0, 0
+; FAST-NEXT:    retl
+;
+; SLOW_32-LABEL: bork:
+; SLOW_32:         movl $0, 4
+; SLOW_32-NEXT:    movl $0, 0
+; SLOW_32-NEXT:    movl $0, 12
+; SLOW_32-NEXT:    movl $0, 8
+; SLOW_32-NEXT:    movl $0, 20
+; SLOW_32-NEXT:    movl $0, 16
+; SLOW_32-NEXT:    movl $0, 28
+; SLOW_32-NEXT:    movl $0, 24
+; SLOW_32-NEXT:    movl $0, 36
+; SLOW_32-NEXT:    movl $0, 32
+; SLOW_32-NEXT:    movl $0, 44
+; SLOW_32-NEXT:    movl $0, 40
+; SLOW_32-NEXT:    movl $0, 52
+; SLOW_32-NEXT:    movl $0, 48
+; SLOW_32-NEXT:    movl $0, 60
+; SLOW_32-NEXT:    movl $0, 56
+; SLOW_32-NEXT:    movl $0, 68
+; SLOW_32-NEXT:    movl $0, 64
+; SLOW_32-NEXT:    movl $0, 76
+; SLOW_32-NEXT:    movl $0, 72
+; SLOW_32-NEXT:    retl
+;
+; SLOW_64-LABEL: bork:
+; SLOW_64:         movq $0, 72
+; SLOW_64-NEXT:    movq $0, 64
+; SLOW_64-NEXT:    movq $0, 56
+; SLOW_64-NEXT:    movq $0, 48
+; SLOW_64-NEXT:    movq $0, 40
+; SLOW_64-NEXT:    movq $0, 32
+; SLOW_64-NEXT:    movq $0, 24
+; SLOW_64-NEXT:    movq $0, 16
+; SLOW_64-NEXT:    movq $0, 8
+; SLOW_64-NEXT:    movq $0, 0
+; SLOW_64-NEXT:    retq
+;
   call void @llvm.memset.p0i8.i64(i8* null, i8 0, i64 80, i32 4, i1 false)
   ret void
 }
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
+