.map_io = smdk4x12_map_io,
.handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init,
+ .init_late = exynos_init_late,
.timer = &exynos4_timer,
.restart = exynos4_restart,
+ .reserve = &smdk4x12_reserve,
MACHINE_END
.map_io = universal_map_io,
.handle_irq = gic_handle_irq,
.init_machine = universal_machine_init,
- .timer = &exynos4_timer,
+ .init_late = exynos_init_late,
+ .timer = &s5p_timer,
.reserve = &universal_reserve,
.restart = exynos4_restart,
MACHINE_END
}
#endif
+ #ifdef CONFIG_OMAP_SERIAL_WAKE
+ int omap_serial_wakeup_init(void);
+ #else
+ static inline int omap_serial_wakeup_init(void)
+ {
+ return 0;
+ }
+ #endif
+
void omap1_init_early(void);
void omap1_init_irq(void);
+ void omap1_init_late(void);
void omap1_restart(char, const char *);
+extern void __init omap_check_revision(void);
+
+extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl);
+
extern struct sys_timer omap1_timer;
-extern bool omap_32k_timer_init(void);
-extern void __init omap_init_consistent_dma_size(void);
+#ifdef CONFIG_OMAP_32K_TIMER
+extern int omap_32k_timer_init(void);
+#else
+static inline int __init omap_32k_timer_init(void)
+{
+ return -ENODEV;
+}
+#endif
+
+extern u32 omap_irq_flags;
+
+#ifdef CONFIG_ARCH_OMAP16XX
+extern int ocpi_enable(void);
+#else
+static inline int ocpi_enable(void) { return 0; }
+#endif
#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
.init_early = omap4430_init_early,
.init_irq = omap_init_irq,
.handle_irq = gic_handle_irq,
- .init_machine = omap4_init,
+ .init_machine = omap_generic_init,
+ .init_late = omap4430_init_late,
.timer = &omap4_timer,
.dt_compat = omap4_boards_compat,
.restart = omap_prcm_restart,
}
}
- static int __init omap3_pm_init(void)
+ int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
- struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+ struct clockdomain *neon_clkdm, *mpu_clkdm;
int ret;
- if (!cpu_is_omap34xx())
- return -ENODEV;
-
if (!omap3_has_io_chain_ctrl())
pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
extern void r8a7779_secondary_init(unsigned int cpu);
extern int r8a7779_boot_secondary(unsigned int cpu);
extern void r8a7779_smp_prepare_cpus(void);
+extern void r8a7779_register_twd(void);
+ extern void shmobile_init_late(void);
+
+ #ifdef CONFIG_SUSPEND
+ int shmobile_suspend_init(void);
+ #else
+ static inline int shmobile_suspend_init(void) { return 0; }
+ #endif
+
+ #ifdef CONFIG_CPU_IDLE
+ int shmobile_cpuidle_init(void);
+ #else
+ static inline int shmobile_cpuidle_init(void) { return 0; }
+ #endif
+
#endif /* __ARCH_MACH_COMMON_H */
extern struct device * __init u8500_init_devices(void);
extern void __init ux500_init_irq(void);
+ extern void __init ux500_init_late(void);
-extern void __init u5500_sdi_init(struct device *parent);
-
-extern void __init db5500_dma_init(struct device *parent);
-
extern struct device *ux500_soc_device_init(const char *soc_id);
struct amba_device;