* sim/fr30/ldres.cgs: New testcase.
* sim/fr30/stres.cgs: New testcase.
* sim/fr30/copop.cgs: New testcase.
* sim/fr30/copld.cgs: New testcase.
* sim/fr30/copst.cgs: New testcase.
* sim/fr30/copsv.cgs: New testcase.
* sim/fr30/nop.cgs: New testcase.
* sim/fr30/andccr.cgs: New testcase.
* sim/fr30/orccr.cgs: New testcase.
* sim/fr30/addsp.cgs: New testcase.
* sim/fr30/stilm.cgs: New testcase.
* sim/fr30/extsb.cgs: New testcase.
* sim/fr30/extub.cgs: New testcase.
* sim/fr30/extsh.cgs: New testcase.
* sim/fr30/extuh.cgs: New testcase.
* sim/fr30/enter.cgs: New testcase.
* sim/fr30/leave.cgs: New testcase.
* sim/fr30/xchb.cgs: New testcase.
* sim/fr30/dmovb.cgs: New testcase.
* sim/fr30/dmov.cgs: New testcase.
* sim/fr30/dmovh.cgs: New testcase.
--- /dev/null
+# fr30 testcase for addsp $s10
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global addsp
+addsp:
+ ; Test addsp $s10
+ mvr_h_gr sp,r7 ; save stack pointer permanently
+ mvr_h_gr sp,r8 ; Shadow updated sp
+ set_cc 0x0f ; Condition codes are irrelevent
+ addsp 508
+ test_cc 1 1 1 1
+ inci_h_gr 508,r8
+ testr_h_gr r8,sp
+
+ set_cc 0x0e ; Condition codes are irrelevent
+ addsp 0
+ test_cc 1 1 1 0
+ testr_h_gr r8,sp
+
+ set_cc 0x0d ; Condition codes are irrelevent
+ addsp -512
+ test_cc 1 1 0 1
+ inci_h_gr -512,r8
+ testr_h_gr r8,sp
+
+ pass
--- /dev/null
+# fr30 testcase for andccr $u8
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global andccr
+andccr:
+ set_cc 0x00
+ set_i 0
+ set_s_system
+ andccr 0xff
+ test_cc 0 0 0 0
+ test_i 0
+ test_s_system
+
+ set_cc 0x0f
+ set_i 1
+ set_s_user
+ andccr 0xff
+ test_cc 1 1 1 1
+ test_i 1
+ test_s_user
+
+ set_cc 0x0f
+ set_i 1
+ set_s_user
+ andccr 0xaa
+ test_cc 1 0 1 0
+ test_i 0
+ test_s_user
+
+ set_cc 0x0f
+ set_i 1
+ set_s_user
+ andccr 0xc0
+ test_cc 0 0 0 0
+ test_i 0
+ test_s_system
+
+ set_cc 0x0f
+ set_i 1
+ set_s_user
+ andccr 0x3f ; no effect
+ test_cc 1 1 1 1
+ test_i 1
+ test_s_user
+
+ pass
--- /dev/null
+# fr30 testcase for copld $u4,$cc,$Rj,CRi
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global copld
+copld:
+ ; Test copld copld $u4,$cc,$Rj,CRi
+ ; The current implementation is a noop
+ set_cc 0x0f ; Condition codes are irrelevent
+ copld 0,0,r0,cr15
+ test_cc 1 1 1 1
+
+ set_cc 0x0e ; Condition codes are irrelevent
+ copld 15,255,r15,cr0
+ test_cc 1 1 1 0
+
+ pass
--- /dev/null
+# fr30 testcase for copop $u4,$cc,$CRj,CRi
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global copop
+copop:
+ ; Test copop copop $u4,$cc,$CRj,CRi
+ ; The current implementation is a noop
+ set_cc 0x0f ; Condition codes are irrelevent
+ copop 0,0,cr0,cr15
+ test_cc 1 1 1 1
+
+ set_cc 0x0e ; Condition codes are irrelevent
+ copop 15,255,cr0,cr15
+ test_cc 1 1 1 0
+
+ pass
--- /dev/null
+# fr30 testcase for copst $u4,$cc,$CRj,Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global copst
+copst:
+ ; Test copst copst $u4,$cc,$CRj,Ri
+ ; The current implementation is a noop
+ set_cc 0x0f ; Condition codes are irrelevent
+ copst 0,0,cr0,r15
+ test_cc 1 1 1 1
+
+ set_cc 0x0e ; Condition codes are irrelevent
+ copst 15,255,cr15,r0
+ test_cc 1 1 1 0
+
+ pass
--- /dev/null
+# fr30 testcase for copsv $u4,$cc,$CRj,Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global copsv
+copsv:
+ ; Test copsv copsv $u4,$cc,$CRj,Ri
+ ; The current implementation is a noop
+ set_cc 0x0f ; Condition codes are irrelevent
+ copsv 0,0,cr0,r15
+ test_cc 1 1 1 1
+
+ set_cc 0x0e ; Condition codes are irrelevent
+ copsv 15,255,cr15,r0
+ test_cc 1 1 1 0
+
+ pass
--- /dev/null
+# fr30 testcase for dmov
+# mach(): fr30
+
+ .include "testutils.inc"
+ START
+
+ .text
+ .global dmov
+dmov:
+ ; Test dmov @$dir10,$R13
+ mvi_h_gr 0xdeadbeef,r1
+ mvi_h_gr 0x200,r2
+ mvr_h_mem r1,r2
+ set_cc 0x0f ; Condition codes shouldn't change
+ dmov @0x200,r13
+ test_cc 1 1 1 1
+ test_h_gr 0xdeadbeef,r13
+
+ ; Test dmov $R13,@$dir10
+ mvi_h_gr 0xbeefdead,r13
+ set_cc 0x0e ; Condition codes shouldn't change
+ dmov r13,@0x200
+ test_cc 1 1 1 0
+ test_h_mem 0xbeefdead,r2
+
+ ; Test dmov @$dir10,@R13+
+ mvi_h_gr 0x1fc,r13
+ set_cc 0x0d ; Condition codes shouldn't change
+ dmov @0x200,@r13+
+ test_cc 1 1 0 1
+ mvi_h_gr 0x1fc,r2
+ test_h_mem 0xbeefdead,r2
+ inci_h_gr 4,r2
+ test_h_mem 0xbeefdead,r2
+ test_h_gr 0x200,r13
+
+ ; Test dmov @$R13+,@$dir10
+ mvi_h_gr 0x1fc,r13
+ mvi_h_mem 0xdeadbeef,r13
+ set_cc 0x0c ; Condition codes shouldn't change
+ dmov @r13+,@0x200
+ test_cc 1 1 0 0
+ mvi_h_gr 0x1fc,r2
+ test_h_mem 0xdeadbeef,r2
+ inci_h_gr 4,r2
+ test_h_mem 0xdeadbeef,r2
+ test_h_gr 0x200,r13
+
+ ; Test dmov @$dir10,@-R15
+ mvi_h_gr 0x200,r15
+ mvi_h_mem 0xdeadbeef,r15
+ set_cc 0x0b ; Condition codes shouldn't change
+ dmov @0x200,@-r15
+ test_cc 1 0 1 1
+ mvi_h_gr 0x1fc,r2
+ test_h_mem 0xdeadbeef,r2
+ inci_h_gr 4,r2
+ test_h_mem 0xdeadbeef,r2
+ test_h_gr 0x1fc,r15
+
+ ; Test dmov @$R15+,@$dir10
+ mvi_h_gr 0x1fc,r15
+ mvi_h_mem 0xbeefdead,r15
+ set_cc 0x0a ; Condition codes shouldn't change
+ dmov @r15+,@0x200
+ test_cc 1 0 1 0
+ mvi_h_gr 0x1fc,r2
+ test_h_mem 0xbeefdead,r2
+ inci_h_gr 4,r2
+ test_h_mem 0xbeefdead,r2
+ test_h_gr 0x200,r15
+
+ pass
--- /dev/null
+# fr30 testcase for dmovb
+# mach(): fr30
+
+ .include "testutils.inc"
+ START
+
+ .text
+ .global dmovb
+dmovb:
+ ; Test dmovb @$dir8,$R13
+ mvi_h_gr 0xdeadbeef,r1
+ mvi_h_gr 0x80,r2
+ mvr_h_mem r1,r2
+ set_cc 0x0f ; Condition codes shouldn't change
+ dmovb @0x80,r13
+ test_cc 1 1 1 1
+ test_h_gr 0xffffffde,r13
+
+ ; Test dmovb $R13,@$dir8
+ mvi_h_gr 0xbeefdead,r13
+ set_cc 0x0e ; Condition codes shouldn't change
+ dmovb r13,@0x80
+ test_cc 1 1 1 0
+ test_h_mem 0xadadbeef,r2
+
+ ; Test dmovb @$dir8,@R13+
+ mvi_h_gr 0x7c,r13
+ mvi_h_mem 0xdeadbeef,r13
+ set_cc 0x0d ; Condition codes shouldn't change
+ dmovb @0x7f,@r13+
+ test_cc 1 1 0 1
+ mvi_h_gr 0x7c,r2
+ test_h_mem 0xefadbeef,r2
+ test_h_gr 0x7d,r13
+
+ ; Test dmovb @$R13+,@$dir8
+ mvi_h_gr 0x7c,r13
+ mvi_h_mem 0xbeefdead,r13
+ set_cc 0x0c ; Condition codes shouldn't change
+ dmovb @r13+,@0x7f
+ test_cc 1 1 0 0
+ mvi_h_gr 0x7c,r2
+ test_h_mem 0xbeefdebe,r2
+ test_h_gr 0x7d,r13
+
+ pass
--- /dev/null
+# fr30 testcase for dmovh
+# mach(): fr30
+
+ .include "testutils.inc"
+ START
+
+ .text
+ .global dmovh
+dmovh:
+ ; Test dmovh @$dir9,$R13
+ mvi_h_gr 0xdeadbeef,r1
+ mvi_h_gr 0x100,r2
+ mvr_h_mem r1,r2
+ set_cc 0x0f ; Condition codes shouldn't change
+ dmovh @0x100,r13
+ test_cc 1 1 1 1
+ test_h_gr 0xffffdead,r13
+
+ ; Test dmovh $R13,@$dir9
+ mvi_h_gr 0xdeadbeef,r13
+ set_cc 0x0e ; Condition codes shouldn't change
+ dmovh r13,@0x100
+ test_cc 1 1 1 0
+ test_h_mem 0xbeefbeef,r2
+
+ ; Test dmovh @$dir9,@R13+
+ mvi_h_gr 0x1fc,r13
+ mvi_h_mem 0xdeadbeef,r13
+ set_cc 0x0d ; Condition codes shouldn't change
+ dmovh @0x1fe,@r13+
+ test_cc 1 1 0 1
+ mvi_h_gr 0x1fc,r2
+ test_h_mem 0xbeefbeef,r2
+ test_h_gr 0x1fe,r13
+
+ ; Test dmovh @$R13+,@$dir9
+ mvi_h_gr 0x1fc,r13
+ mvi_h_mem 0xbeefdead,r13
+ set_cc 0x0c ; Condition codes shouldn't change
+ dmovh @r13+,@0x1fe
+ test_cc 1 1 0 0
+ mvi_h_gr 0x1fc,r2
+ test_h_mem 0xbeefbeef,r2
+ test_h_gr 0x1fe,r13
+
+ pass
--- /dev/null
+# fr30 testcase for extsb $Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global extsb
+extsb:
+ ; Test extsb $Ri
+ mvi_h_gr 0,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ extsb r7
+ test_cc 1 1 1 1
+ test_h_gr 0,r7
+
+ mvi_h_gr 0x7f,r7
+ set_cc 0x0e ; Condition codes are irrelevent
+ extsb r7
+ test_cc 1 1 1 0
+ test_h_gr 0x7f,r7
+
+ mvi_h_gr 0x80,r7
+ set_cc 0x0d ; Condition codes are irrelevent
+ extsb r7
+ test_cc 1 1 0 1
+ test_h_gr 0xffffff80,r7
+
+ mvi_h_gr 0xffffff7f,r7
+ set_cc 0x0c ; Condition codes are irrelevent
+ extsb r7
+ test_cc 1 1 0 0
+ test_h_gr 0x7f,r7
+
+ pass
--- /dev/null
+# fr30 testcase for extsh $Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global extsh
+extsh:
+ ; Test extsh $Ri
+ mvi_h_gr 0,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ extsh r7
+ test_cc 1 1 1 1
+ test_h_gr 0,r7
+
+ mvi_h_gr 0x7f,r7
+ set_cc 0x0e ; Condition codes are irrelevent
+ extsh r7
+ test_cc 1 1 1 0
+ test_h_gr 0x7f,r7
+
+ mvi_h_gr 0x80,r7
+ set_cc 0x0d ; Condition codes are irrelevent
+ extsh r7
+ test_cc 1 1 0 1
+ test_h_gr 0x80,r7
+
+ mvi_h_gr 0x7fff,r7
+ set_cc 0x0c ; Condition codes are irrelevent
+ extsh r7
+ test_cc 1 1 0 0
+ test_h_gr 0x7fff,r7
+
+ mvi_h_gr 0x8000,r7
+ set_cc 0x0b ; Condition codes are irrelevent
+ extsh r7
+ test_cc 1 0 1 1
+ test_h_gr 0xffff8000,r7
+
+ mvi_h_gr 0xffff7fff,r7
+ set_cc 0x0a ; Condition codes are irrelevent
+ extsh r7
+ test_cc 1 0 1 0
+ test_h_gr 0x7fff,r7
+
+ pass
--- /dev/null
+# fr30 testcase for extub $Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global extub
+extub:
+ ; Test extub $Ri
+ mvi_h_gr 0,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ extub r7
+ test_cc 1 1 1 1
+ test_h_gr 0,r7
+
+ mvi_h_gr 0x7f,r7
+ set_cc 0x0e ; Condition codes are irrelevent
+ extub r7
+ test_cc 1 1 1 0
+ test_h_gr 0x7f,r7
+
+ mvi_h_gr 0x80,r7
+ set_cc 0x0d ; Condition codes are irrelevent
+ extub r7
+ test_cc 1 1 0 1
+ test_h_gr 0x80,r7
+
+ mvi_h_gr 0xffffff7f,r7
+ set_cc 0x0c ; Condition codes are irrelevent
+ extub r7
+ test_cc 1 1 0 0
+ test_h_gr 0x7f,r7
+
+ mvi_h_gr 0xffffff80,r7
+ set_cc 0x0b ; Condition codes are irrelevent
+ extub r7
+ test_cc 1 0 1 1
+ test_h_gr 0x80,r7
+
+ pass
--- /dev/null
+# fr30 testcase for extuh $Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global extuh
+extuh:
+ ; Test extuh $Ri
+ mvi_h_gr 0,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 1 1 1
+ test_h_gr 0,r7
+
+ mvi_h_gr 0x7f,r7
+ set_cc 0x0e ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 1 1 0
+ test_h_gr 0x7f,r7
+
+ mvi_h_gr 0x80,r7
+ set_cc 0x0d ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 1 0 1
+ test_h_gr 0x80,r7
+
+ mvi_h_gr 0x7fff,r7
+ set_cc 0x0e ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 1 1 0
+ test_h_gr 0x7fff,r7
+
+ mvi_h_gr 0x8000,r7
+ set_cc 0x0d ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 1 0 1
+ test_h_gr 0x8000,r7
+
+ mvi_h_gr 0xffff7fff,r7
+ set_cc 0x0c ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 1 0 0
+ test_h_gr 0x7fff,r7
+
+ mvi_h_gr 0xffff8000,r7
+ set_cc 0x0b ; Condition codes are irrelevent
+ extuh r7
+ test_cc 1 0 1 1
+ test_h_gr 0x8000,r7
+
+ pass
--- /dev/null
+# fr30 testcase for ldres $@Ri+,$u4
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global ldres
+ldres:
+ ; Test ldres $@Ri+,$u4
+ ; The current implementation simply increments Ri
+ mvi_h_gr 0x1000,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ ldres @r7+,0
+ test_cc 1 1 1 1
+ test_h_gr 0x1004,r7
+
+ mvi_h_gr 0x1000,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ ldres @r7+,0xf
+ test_cc 1 1 1 1
+ test_h_gr 0x1004,r7
+
+ pass
--- /dev/null
+# fr30 testcase for leave
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global leave
+leave:
+ ; Test leave $u10
+ mvr_h_gr sp,r7 ; save Stack pointer
+ mvr_h_gr sp,r14
+ inci_h_gr -4,r14
+ mvi_h_mem 0xdeadbeef,r14
+ mvi_h_gr 0xbeefdead,r15
+ set_cc 0x0f ; Condition codes are irrelevent
+ leave
+ test_cc 1 1 1 1
+ testr_h_gr sp,r7
+ test_h_gr 0xdeadbeef,r14
+
+ pass
--- /dev/null
+# fr30 testcase for nop
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global nop
+nop:
+ ; Test nop
+ set_cc 0x0f ; Condition codes are irrelevent
+ nop
+ test_cc 1 1 1 1
+
+ pass
--- /dev/null
+# fr30 testcase for orccr $u8
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global orccr
+orccr:
+ orccr 0xff
+ test_cc 1 1 1 1
+ test_i 1
+ test_s_user
+
+ set_cc 0x0f
+ orccr 0x00
+ test_cc 1 1 1 1
+ test_i 1
+ test_s_user
+
+ set_cc 0x00
+ set_i 0
+ set_s_system
+ orccr 0xaa
+ test_cc 1 0 1 0
+ test_i 0
+ test_s_user
+
+ set_cc 0x00
+ set_i 0
+ set_s_system
+ orccr 0xc0
+ test_cc 0 0 0 0
+ test_i 0
+ test_s_system
+
+ pass
--- /dev/null
+# fr30 testcase for stilm $i8
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global stilm
+stilm:
+ stilm 0
+ test_ilm 0
+
+ stilm 0xe0
+ test_ilm 0
+
+ stilm 1
+ test_ilm 1
+
+ stilm 15
+ test_ilm 15
+
+ stilm 16
+ test_ilm 16
+
+ stilm 0
+ test_ilm 16
+
+ stilm 1
+ test_ilm 17
+
+ stilm 18
+ test_ilm 18
+
+ stilm 31
+ test_ilm 31
+
+ stilm 0xff
+ test_ilm 31
+
+ pass
--- /dev/null
+# fr30 testcase for stres $@Ri+,$u4
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global stres
+stres:
+ ; Test stres $@Ri+,$u4
+ ; The current implementation simply increments Ri
+ mvi_h_gr 0x1000,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ stres 0,@r7+
+ test_cc 1 1 1 1
+ test_h_gr 0x1004,r7
+
+ mvi_h_gr 0x1000,r7
+ set_cc 0x0f ; Condition codes are irrelevent
+ stres 0xf,@r7+
+ test_cc 1 1 1 1
+ test_h_gr 0x1004,r7
+
+ pass
--- /dev/null
+# fr30 testcase for xchb @$Rj,Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global xchb
+xchb:
+ ; Test xchb @$Rj,Ri
+ mvi_h_mem 0xdeadbeef,sp
+ mvi_h_gr 0xbeefdead,r0
+ set_cc 0x0f ; Condition codes are irrelevent
+ xchb @sp,r0
+ test_cc 1 1 1 1
+ test_h_gr 0xde,r0
+ test_h_mem 0xadadbeef,sp
+
+ pass
projects / external / binutils.git / commitdiff