amd: remove ac_check_shadowed_regs

not useful anymore

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23687>

diff --git a/src/amd/common/ac_shadowed_regs.c b/src/amd/common/ac_shadowed_regs.c
index 586a4fe..89eaaa6 100644 (file)
--- a/src/amd/common/ac_shadowed_regs.c
+++ b/src/amd/common/ac_shadowed_regs.c
@@ -3706,50 +3706,6 @@ void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf
    }
 }
 
-/* Debug helper to find if any registers are missing in the tables above.
- * Call this in the driver whenever you set a register.
- */
-void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family,
-                            unsigned reg_offset, unsigned count)
-{
-   bool found = false;
-   bool shadowed = false;
-
-   for (unsigned type = 0; type < SI_NUM_REG_RANGES && !found; type++) {
-      const struct ac_reg_range *ranges;
-      unsigned num_ranges;
-
-      ac_get_reg_ranges(gfx_level, family, type, &num_ranges, &ranges);
-
-      for (unsigned i = 0; i < num_ranges; i++) {
-         unsigned end_reg_offset = reg_offset + count * 4;
-         unsigned end_range_offset = ranges[i].offset + ranges[i].size;
-
-         /* Test if the ranges intersect. */
-         if (MAX2(ranges[i].offset, reg_offset) < MIN2(end_range_offset, end_reg_offset)) {
-            /* Assertion: A register can be listed only once. */
-            assert(!found);
-            found = true;
-            shadowed = true;
-         }
-      }
-   }
-
-   if (reg_offset == R_00B858_COMPUTE_DESTINATION_EN_SE0 ||
-       reg_offset == R_00B864_COMPUTE_DESTINATION_EN_SE2)
-      return;
-
-   if (!found || !shadowed) {
-      printf("register %s: ", !found ? "not found" : "not shadowed");
-      if (count > 1) {
-         printf("%s .. %s\n", ac_get_register_name(gfx_level, family, reg_offset),
-                ac_get_register_name(gfx_level, family, reg_offset + (count - 1) * 4));
-      } else {
-         printf("%s\n", ac_get_register_name(gfx_level, family, reg_offset));
-      }
-   }
-}
-
 /* Debug helper to print all shadowed registers and their current values read
  * by umr. This can be used to verify whether register shadowing doesn't affect
  * apps that don't enable it, because the shadowed register tables might contain

diff --git a/src/amd/common/ac_shadowed_regs.h b/src/amd/common/ac_shadowed_regs.h
index 4ebbec5..c940b26 100644 (file)
--- a/src/amd/common/ac_shadowed_regs.h
+++ b/src/amd/common/ac_shadowed_regs.h
@@ -39,8 +39,6 @@ void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family,
                        const struct ac_reg_range **ranges);
 void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf *cs,
                             set_context_reg_seq_array_fn set_context_reg_seq_array);
-void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family,
-                            unsigned reg_offset, unsigned count);
 void ac_print_shadowed_regs(const struct radeon_info *info);
 
 void ac_create_shadowing_ib_preamble(const struct radeon_info *info,

diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
index 7481727..64eb3c9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_build_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -14,13 +14,6 @@
 #include "si_pipe.h"
 #include "sid.h"
 
-#if 0
-#include "ac_shadowed_regs.h"
-#define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_offset, count)
-#else
-#define SI_CHECK_SHADOWED_REGS(reg_offset, count)
-#endif
-
 #define radeon_begin(cs) struct radeon_cmdbuf *__cs = (cs); \
                          unsigned __cs_num = __cs->current.cdw; \
                          UNUSED unsigned __cs_num_initial = __cs_num; \
@@ -64,7 +57,6 @@
 } while (0)
 
 #define radeon_set_config_reg_seq(reg, num) do { \
-   SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) < SI_CONTEXT_REG_OFFSET); \
    radeon_emit(PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
    radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
@@ -76,7 +68,6 @@
 } while (0)
 
 #define radeon_set_context_reg_seq(reg, num) do { \
-   SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) >= SI_CONTEXT_REG_OFFSET); \
    radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
    radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
@@ -93,7 +84,6 @@
 } while (0)
 
 #define radeon_set_context_reg_idx(reg, idx, value) do { \
-   SI_CHECK_SHADOWED_REGS(reg, 1); \
    assert((reg) >= SI_CONTEXT_REG_OFFSET); \
    radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
    radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2 | ((idx) << 28)); \
@@ -101,14 +91,12 @@
 } while (0)
 
 #define radeon_set_sh_reg_seq(reg, num) do { \
-   SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
    radeon_emit(PKT3(PKT3_SET_SH_REG, num, 0)); \
    radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
 } while (0)
 
 #define radeon_set_sh_reg_idx3_seq(sctx, reg, num) do { \
-   SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
    if ((sctx)->screen->info.uses_kernel_cu_mask) { \
       assert((sctx)->gfx_level >= GFX10); \
@@ -131,7 +119,6 @@
 } while (0)
 
 #define radeon_set_uconfig_reg_seq(reg, num, perfctr) do { \
-   SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
    radeon_emit(PKT3(PKT3_SET_UCONFIG_REG, num, perfctr)); \
    radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \
@@ -148,7 +135,6 @@
 } while (0)
 
 #define radeon_set_uconfig_reg_idx(screen, gfx_level, reg, idx, value) do { \
-   SI_CHECK_SHADOWED_REGS(reg, 1); \
    assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
    assert((idx) != 0); \
    unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \

diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index 807f8d6..2898f9a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -61,8 +61,6 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
 {
    unsigned opcode;
 
-   SI_CHECK_SHADOWED_REGS(reg, 1);
-
    if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
       opcode = PKT3_SET_CONFIG_REG;
       reg -= SI_CONFIG_REG_OFFSET;
@@ -90,8 +88,6 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
 void si_pm4_set_reg_idx3(struct si_screen *sscreen, struct si_pm4_state *state,
                          unsigned reg, uint32_t val)
 {
-   SI_CHECK_SHADOWED_REGS(reg, 1);
-
    if (sscreen->info.uses_kernel_cu_mask) {
       assert(sscreen->info.gfx_level >= GFX10);
       si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG_INDEX, 3);