}
}
-/* Debug helper to find if any registers are missing in the tables above.
- * Call this in the driver whenever you set a register.
- */
-void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family,
- unsigned reg_offset, unsigned count)
-{
- bool found = false;
- bool shadowed = false;
-
- for (unsigned type = 0; type < SI_NUM_REG_RANGES && !found; type++) {
- const struct ac_reg_range *ranges;
- unsigned num_ranges;
-
- ac_get_reg_ranges(gfx_level, family, type, &num_ranges, &ranges);
-
- for (unsigned i = 0; i < num_ranges; i++) {
- unsigned end_reg_offset = reg_offset + count * 4;
- unsigned end_range_offset = ranges[i].offset + ranges[i].size;
-
- /* Test if the ranges intersect. */
- if (MAX2(ranges[i].offset, reg_offset) < MIN2(end_range_offset, end_reg_offset)) {
- /* Assertion: A register can be listed only once. */
- assert(!found);
- found = true;
- shadowed = true;
- }
- }
- }
-
- if (reg_offset == R_00B858_COMPUTE_DESTINATION_EN_SE0 ||
- reg_offset == R_00B864_COMPUTE_DESTINATION_EN_SE2)
- return;
-
- if (!found || !shadowed) {
- printf("register %s: ", !found ? "not found" : "not shadowed");
- if (count > 1) {
- printf("%s .. %s\n", ac_get_register_name(gfx_level, family, reg_offset),
- ac_get_register_name(gfx_level, family, reg_offset + (count - 1) * 4));
- } else {
- printf("%s\n", ac_get_register_name(gfx_level, family, reg_offset));
- }
- }
-}
-
/* Debug helper to print all shadowed registers and their current values read
* by umr. This can be used to verify whether register shadowing doesn't affect
* apps that don't enable it, because the shadowed register tables might contain
#include "si_pipe.h"
#include "sid.h"
-#if 0
-#include "ac_shadowed_regs.h"
-#define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_offset, count)
-#else
-#define SI_CHECK_SHADOWED_REGS(reg_offset, count)
-#endif
-
#define radeon_begin(cs) struct radeon_cmdbuf *__cs = (cs); \
unsigned __cs_num = __cs->current.cdw; \
UNUSED unsigned __cs_num_initial = __cs_num; \
} while (0)
#define radeon_set_config_reg_seq(reg, num) do { \
- SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) < SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_context_reg_seq(reg, num) do { \
- SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) >= SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_context_reg_idx(reg, idx, value) do { \
- SI_CHECK_SHADOWED_REGS(reg, 1); \
assert((reg) >= SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2 | ((idx) << 28)); \
} while (0)
#define radeon_set_sh_reg_seq(reg, num) do { \
- SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
radeon_emit(PKT3(PKT3_SET_SH_REG, num, 0)); \
radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_sh_reg_idx3_seq(sctx, reg, num) do { \
- SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
if ((sctx)->screen->info.uses_kernel_cu_mask) { \
assert((sctx)->gfx_level >= GFX10); \
} while (0)
#define radeon_set_uconfig_reg_seq(reg, num, perfctr) do { \
- SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
radeon_emit(PKT3(PKT3_SET_UCONFIG_REG, num, perfctr)); \
radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_uconfig_reg_idx(screen, gfx_level, reg, idx, value) do { \
- SI_CHECK_SHADOWED_REGS(reg, 1); \
assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
assert((idx) != 0); \
unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \
{
unsigned opcode;
- SI_CHECK_SHADOWED_REGS(reg, 1);
-
if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
opcode = PKT3_SET_CONFIG_REG;
reg -= SI_CONFIG_REG_OFFSET;
void si_pm4_set_reg_idx3(struct si_screen *sscreen, struct si_pm4_state *state,
unsigned reg, uint32_t val)
{
- SI_CHECK_SHADOWED_REGS(reg, 1);
-
if (sscreen->info.uses_kernel_cu_mask) {
assert(sscreen->info.gfx_level >= GFX10);
si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG_INDEX, 3);