TARGET_NODE_CASE(GLOBAL_BASE_REG)
TARGET_NODE_CASE(Hi)
TARGET_NODE_CASE(Lo)
- TARGET_NODE_CASE(MEMBARRIER)
TARGET_NODE_CASE(RET_FLAG)
TARGET_NODE_CASE(TS1AM)
TARGET_NODE_CASE(VEC_UNPACK_LO)
}
// MEMBARRIER is a compiler barrier; it codegens to a no-op.
- return DAG.getNode(VEISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
+ return DAG.getNode(ISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
}
TargetLowering::AtomicExpansionKind
GLOBAL_BASE_REG, // Global base reg for PIC.
Hi, // Hi/Lo operations, typically on a global address.
Lo, // Hi/Lo operations, typically on a global address.
- MEMBARRIER, // Compiler barrier only; generate a no-op.
RET_FLAG, // Return with a flag operand.
TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
VEC_UNPACK_LO, // unpack the lo v256 slice of a packed v512 vector.
def GetStackTop : SDNode<"VEISD::GETSTACKTOP", SDTNone,
[SDNPHasChain, SDNPSideEffect]>;
-// MEMBARRIER
-def MemBarrier : SDNode<"VEISD::MEMBARRIER", SDTNone,
- [SDNPHasChain, SDNPSideEffect]>;
-
// TS1AM
def SDT_TS1AM : SDTypeProfile<1, 3, [SDTCisSameAs<0, 3>, SDTCisPtrTy<1>,
SDTCisVT<2, i32>, SDTCisInt<3>]>;
// MEMBARRIER
let hasSideEffects = 1 in
-def MEMBARRIER : Pseudo<(outs), (ins), "# MEMBARRIER", [(MemBarrier)] >;
+def MEMBARRIER : Pseudo<(outs), (ins), "# MEMBARRIER", [(membarrier)] >;
//===----------------------------------------------------------------------===//
// Other patterns