This option enables support for the Maple 970FX Evaluation Board.
For more informations, refer to <http://www.970eval.com>
-config PPC_BPA
- bool " Broadband Processor Architecture"
+config PPC_CELL
+ bool " Cell Broadband Processor Architecture"
depends on PPC_MULTIPLATFORM && PPC64
select PPC_RTAS
depends on PPC_MAPLE
default y
-config BPA_IIC
- depends on PPC_BPA
+config CELL_IIC
+ depends on PPC_CELL
bool
default y
#endif
/*
- * On pSeries and BPA, copy the CPU hold code
+ * Copy the CPU hold code
*/
if (RELOC(of_platform) != PLATFORM_POWERMAC)
copy_and_flush(0, KERNELBASE + offset, 0x100, 0);
extern struct machdep_calls pSeries_md;
extern struct machdep_calls pmac_md;
extern struct machdep_calls maple_md;
-extern struct machdep_calls bpa_md;
+extern struct machdep_calls cell_md;
extern struct machdep_calls iseries_md;
/* Ultimately, stuff them in an elf section like initcalls... */
#ifdef CONFIG_PPC_MAPLE
&maple_md,
#endif /* CONFIG_PPC_MAPLE */
-#ifdef CONFIG_PPC_BPA
- &bpa_md,
+#ifdef CONFIG_PPC_CELL
+ &cell_md,
#endif
#ifdef CONFIG_PPC_ISERIES
&iseries_md,
printk("POWERMAC ");
nl = 1;
break;
- case PLATFORM_BPA:
- printk("BPA ");
+ case PLATFORM_CELL:
+ printk("CELL ");
nl = 1;
break;
}
obj-$(CONFIG_PPC_PSERIES) += rtasd.o udbg_16550.o
-obj-$(CONFIG_PPC_BPA) += bpa_setup.o bpa_iommu.o bpa_nvram.o \
+obj-$(CONFIG_PPC_CELL) += bpa_setup.o bpa_iommu.o bpa_nvram.o \
bpa_iic.o spider-pic.o
obj-$(CONFIG_KEXEC) += machine_kexec.o
/*
- * BPA Internal Interrupt Controller
+ * Cell Internal Interrupt Controller
*
* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
*
#include <asm/prom.h>
#include <asm/ptrace.h>
-#include "bpa_iic.h"
+#include "interrupt.h"
struct iic_pending_bits {
u32 data;
}
static struct hw_interrupt_type iic_pic = {
- .typename = " BPA-IIC ",
+ .typename = " CELL-IIC ",
.startup = iic_startup,
.enable = iic_enable,
.disable = iic_disable,
irq = -1;
/*
- * This mapping is specific to the Broadband
+ * This mapping is specific to the Cell Broadband
* Engine. We might need to get the numbers
* from the device tree to support future CPUs.
*/
-#ifndef ASM_BPA_IIC_H
-#define ASM_BPA_IIC_H
+#ifndef ASM_CELL_PIC_H
+#define ASM_CELL_PIC_H
#ifdef __KERNEL__
/*
* Mapping of IIC pending bits into per-node
* + node number
* * don't care
*
- * A node consists of a Broadband Engine and an optional
+ * A node consists of a Cell Broadband Engine and an optional
* south bridge device providing a maximum of 64 IRQs.
* The south bridge may be connected to either IOIF0
* or IOIF1.
extern int spider_get_irq(unsigned long int_pending);
#endif
-#endif /* ASM_BPA_IIC_H */
+#endif /* ASM_CELL_PIC_H */
/*
- * IOMMU implementation for Broadband Processor Architecture
+ * IOMMU implementation for Cell Broadband Processor Architecture
* We just establish a linear mapping at boot by setting all the
* IOPT cache entries in the CPU.
* The mapping functions should be identical to pci_direct_iommu,
#include <asm/system.h>
#include <asm/ppc-pci.h>
-#include "bpa_iommu.h"
+#include "iommu.h"
static inline unsigned long
get_iopt_entry(unsigned long real_address, unsigned long ioid,
* for each DMA window used by any device. For now, we
* happen to know that there is only one DMA window in use,
* starting at iopt_phys_offset. */
-static void bpa_map_iommu(void)
+static void cell_map_iommu(void)
{
unsigned long address;
void __iomem *base;
}
-static void *bpa_alloc_coherent(struct device *hwdev, size_t size,
+static void *cell_alloc_coherent(struct device *hwdev, size_t size,
dma_addr_t *dma_handle, gfp_t flag)
{
void *ret;
ret = (void *)__get_free_pages(flag, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
- *dma_handle = virt_to_abs(ret) | BPA_DMA_VALID;
+ *dma_handle = virt_to_abs(ret) | CELL_DMA_VALID;
}
return ret;
}
-static void bpa_free_coherent(struct device *hwdev, size_t size,
+static void cell_free_coherent(struct device *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long)vaddr, get_order(size));
}
-static dma_addr_t bpa_map_single(struct device *hwdev, void *ptr,
+static dma_addr_t cell_map_single(struct device *hwdev, void *ptr,
size_t size, enum dma_data_direction direction)
{
- return virt_to_abs(ptr) | BPA_DMA_VALID;
+ return virt_to_abs(ptr) | CELL_DMA_VALID;
}
-static void bpa_unmap_single(struct device *hwdev, dma_addr_t dma_addr,
+static void cell_unmap_single(struct device *hwdev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
-static int bpa_map_sg(struct device *hwdev, struct scatterlist *sg,
+static int cell_map_sg(struct device *hwdev, struct scatterlist *sg,
int nents, enum dma_data_direction direction)
{
int i;
for (i = 0; i < nents; i++, sg++) {
sg->dma_address = (page_to_phys(sg->page) + sg->offset)
- | BPA_DMA_VALID;
+ | CELL_DMA_VALID;
sg->dma_length = sg->length;
}
return nents;
}
-static void bpa_unmap_sg(struct device *hwdev, struct scatterlist *sg,
+static void cell_unmap_sg(struct device *hwdev, struct scatterlist *sg,
int nents, enum dma_data_direction direction)
{
}
-static int bpa_dma_supported(struct device *dev, u64 mask)
+static int cell_dma_supported(struct device *dev, u64 mask)
{
return mask < 0x100000000ull;
}
-void bpa_init_iommu(void)
+void cell_init_iommu(void)
{
- bpa_map_iommu();
+ cell_map_iommu();
/* Direct I/O, IOMMU off */
ppc_md.iommu_dev_setup = iommu_dev_setup_null;
ppc_md.iommu_bus_setup = iommu_bus_setup_null;
- pci_dma_ops.alloc_coherent = bpa_alloc_coherent;
- pci_dma_ops.free_coherent = bpa_free_coherent;
- pci_dma_ops.map_single = bpa_map_single;
- pci_dma_ops.unmap_single = bpa_unmap_single;
- pci_dma_ops.map_sg = bpa_map_sg;
- pci_dma_ops.unmap_sg = bpa_unmap_sg;
- pci_dma_ops.dma_supported = bpa_dma_supported;
+ pci_dma_ops.alloc_coherent = cell_alloc_coherent;
+ pci_dma_ops.free_coherent = cell_free_coherent;
+ pci_dma_ops.map_single = cell_map_single;
+ pci_dma_ops.unmap_single = cell_unmap_single;
+ pci_dma_ops.map_sg = cell_map_sg;
+ pci_dma_ops.unmap_sg = cell_unmap_sg;
+ pci_dma_ops.dma_supported = cell_dma_supported;
}
-#ifndef BPA_IOMMU_H
-#define BPA_IOMMU_H
+#ifndef CELL_IOMMU_H
+#define CELL_IOMMU_H
/* some constants */
enum {
/* The high bit needs to be set on every DMA address,
only 2GB are addressable */
- BPA_DMA_VALID = 0x80000000,
- BPA_DMA_MASK = 0x7fffffff,
+ CELL_DMA_VALID = 0x80000000,
+ CELL_DMA_MASK = 0x7fffffff,
};
-void bpa_init_iommu(void);
+void cell_init_iommu(void);
#endif
/*
- * NVRAM for CPBW
+ * memory mapped NVRAM
*
* (C) Copyright IBM Corp. 2005
*
#include <asm/nvram.h>
#include <asm/prom.h>
-static void __iomem *bpa_nvram_start;
-static long bpa_nvram_len;
-static spinlock_t bpa_nvram_lock = SPIN_LOCK_UNLOCKED;
+static void __iomem *mmio_nvram_start;
+static long mmio_nvram_len;
+static spinlock_t mmio_nvram_lock = SPIN_LOCK_UNLOCKED;
-static ssize_t bpa_nvram_read(char *buf, size_t count, loff_t *index)
+static ssize_t mmio_nvram_read(char *buf, size_t count, loff_t *index)
{
unsigned long flags;
- if (*index >= bpa_nvram_len)
+ if (*index >= mmio_nvram_len)
return 0;
- if (*index + count > bpa_nvram_len)
- count = bpa_nvram_len - *index;
+ if (*index + count > mmio_nvram_len)
+ count = mmio_nvram_len - *index;
- spin_lock_irqsave(&bpa_nvram_lock, flags);
+ spin_lock_irqsave(&mmio_nvram_lock, flags);
- memcpy_fromio(buf, bpa_nvram_start + *index, count);
+ memcpy_fromio(buf, mmio_nvram_start + *index, count);
- spin_unlock_irqrestore(&bpa_nvram_lock, flags);
+ spin_unlock_irqrestore(&mmio_nvram_lock, flags);
*index += count;
return count;
}
-static ssize_t bpa_nvram_write(char *buf, size_t count, loff_t *index)
+static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index)
{
unsigned long flags;
- if (*index >= bpa_nvram_len)
+ if (*index >= mmio_nvram_len)
return 0;
- if (*index + count > bpa_nvram_len)
- count = bpa_nvram_len - *index;
+ if (*index + count > mmio_nvram_len)
+ count = mmio_nvram_len - *index;
- spin_lock_irqsave(&bpa_nvram_lock, flags);
+ spin_lock_irqsave(&mmio_nvram_lock, flags);
- memcpy_toio(bpa_nvram_start + *index, buf, count);
+ memcpy_toio(mmio_nvram_start + *index, buf, count);
- spin_unlock_irqrestore(&bpa_nvram_lock, flags);
+ spin_unlock_irqrestore(&mmio_nvram_lock, flags);
*index += count;
return count;
}
-static ssize_t bpa_nvram_get_size(void)
+static ssize_t mmio_nvram_get_size(void)
{
- return bpa_nvram_len;
+ return mmio_nvram_len;
}
-int __init bpa_nvram_init(void)
+int __init mmio_nvram_init(void)
{
struct device_node *nvram_node;
unsigned long *buffer;
ret = -ENODEV;
nvram_addr = buffer[0];
- bpa_nvram_len = buffer[1];
- if ( (!bpa_nvram_len) || (!nvram_addr) )
+ mmio_nvram_len = buffer[1];
+ if ( (!mmio_nvram_len) || (!nvram_addr) )
goto out;
- bpa_nvram_start = ioremap(nvram_addr, bpa_nvram_len);
- if (!bpa_nvram_start)
+ mmio_nvram_start = ioremap(nvram_addr, mmio_nvram_len);
+ if (!mmio_nvram_start)
goto out;
- printk(KERN_INFO "BPA NVRAM, %luk mapped to %p\n",
- bpa_nvram_len >> 10, bpa_nvram_start);
+ printk(KERN_INFO "mmio NVRAM, %luk mapped to %p\n",
+ mmio_nvram_len >> 10, mmio_nvram_start);
- ppc_md.nvram_read = bpa_nvram_read;
- ppc_md.nvram_write = bpa_nvram_write;
- ppc_md.nvram_size = bpa_nvram_get_size;
+ ppc_md.nvram_read = mmio_nvram_read;
+ ppc_md.nvram_write = mmio_nvram_write;
+ ppc_md.nvram_size = mmio_nvram_get_size;
out:
of_node_put(nvram_node);
/*
- * linux/arch/ppc/kernel/bpa_setup.c
+ * linux/arch/powerpc/platforms/cell/cell_setup.c
*
* Copyright (C) 1995 Linus Torvalds
* Adapted from 'alpha' version by Gary Thomas
* Modified by Cort Dougan (cort@cs.nmt.edu)
* Modified by PPC64 Team, IBM Corp
- * Modified by BPA Team, IBM Deutschland Entwicklung GmbH
+ * Modified by Cell Team, IBM Deutschland Entwicklung GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#include <asm/ppc-pci.h>
#include <asm/irq.h>
-#include "bpa_iic.h"
-#include "bpa_iommu.h"
+#include "interrupt.h"
+#include "iommu.h"
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#define DBG(fmt...)
#endif
-void bpa_show_cpuinfo(struct seq_file *m)
+void cell_show_cpuinfo(struct seq_file *m)
{
struct device_node *root;
const char *model = "";
root = of_find_node_by_path("/");
if (root)
model = get_property(root, "model", NULL);
- seq_printf(m, "machine\t\t: BPA %s\n", model);
+ seq_printf(m, "machine\t\t: CHRP %s\n", model);
of_node_put(root);
}
-static void bpa_progress(char *s, unsigned short hex)
+static void cell_progress(char *s, unsigned short hex)
{
printk("*** %04x : %s\n", hex, s ? s : "");
}
-static void __init bpa_setup_arch(void)
+static void __init cell_setup_arch(void)
{
ppc_md.init_IRQ = iic_init_IRQ;
ppc_md.get_irq = iic_get_irq;
#ifdef CONFIG_SMP
- smp_init_pSeries();
+ smp_init_cell();
#endif
/* init to some ~sane value until calibrate_delay() runs */
conswitchp = &dummy_con;
#endif
- bpa_nvram_init();
+ mmio_nvram_init();
}
/*
* Early initialization. Relocation is on but do not reference unbolted pages
*/
-static void __init bpa_init_early(void)
+static void __init cell_init_early(void)
{
- DBG(" -> bpa_init_early()\n");
+ DBG(" -> cell_init_early()\n");
hpte_init_native();
- bpa_init_iommu();
+ cell_init_iommu();
- ppc64_interrupt_controller = IC_BPA_IIC;
+ ppc64_interrupt_controller = IC_CELL_PIC;
- DBG(" <- bpa_init_early()\n");
+ DBG(" <- cell_init_early()\n");
}
-static int __init bpa_probe(int platform)
+static int __init cell_probe(int platform)
{
- if (platform != PLATFORM_BPA)
+ if (platform != PLATFORM_CELL)
return 0;
return 1;
}
-struct machdep_calls __initdata bpa_md = {
- .probe = bpa_probe,
- .setup_arch = bpa_setup_arch,
- .init_early = bpa_init_early,
- .show_cpuinfo = bpa_show_cpuinfo,
+struct machdep_calls __initdata cell_md = {
+ .probe = cell_probe,
+ .setup_arch = cell_setup_arch,
+ .init_early = cell_init_early,
+ .show_cpuinfo = cell_show_cpuinfo,
.restart = rtas_restart,
.power_off = rtas_power_off,
.halt = rtas_halt,
.get_rtc_time = rtas_get_rtc_time,
.set_rtc_time = rtas_set_rtc_time,
.calibrate_decr = generic_calibrate_decr,
- .progress = bpa_progress,
+ .progress = cell_progress,
};
if (ppc64_interrupt_controller == IC_OPEN_PIC)
return real_irq; /* no mapping for openpic (for now) */
- if (ppc64_interrupt_controller == IC_BPA_IIC)
+ if (ppc64_interrupt_controller == IC_CELL_PIC)
return real_irq; /* no mapping for iic either */
/* don't map interrupts < MIN_VIRT_IRQ */
if (!root)
return 1;
- if (!(systemcfg->platform & (PLATFORM_PSERIES | PLATFORM_BPA)))
+ if (!(systemcfg->platform & (PLATFORM_PSERIES | PLATFORM_CELL)))
return 0;
if (!proc_mkdir("rtas", root))
prom_send_capabilities();
/*
- * On pSeries and BPA, copy the CPU hold code
+ * On pSeries and Cell, copy the CPU hold code
*/
- if (RELOC(of_platform) & (PLATFORM_PSERIES | PLATFORM_BPA))
+ if (RELOC(of_platform) & (PLATFORM_PSERIES | PLATFORM_CELL))
copy_and_flush(0, KERNELBASE - offset, 0x100, 0);
/*
#include <asm/prom.h>
#include <asm/io.h>
-#include "bpa_iic.h"
+#include "interrupt.h"
/* register layout taken from Spider spec, table 7.4-4 */
enum {
#define IC_INVALID 0
#define IC_OPEN_PIC 1
#define IC_PPC_XIC 2
-#define IC_BPA_IIC 3
+#define IC_CELL_PIC 3
#define IC_ISERIES 4
extern u64 ppc64_interrupt_controller;
#define PLATFORM_LPAR 0x0001
#define PLATFORM_POWERMAC 0x0400
#define PLATFORM_MAPLE 0x0500
-#define PLATFORM_BPA 0x1000
+#define PLATFORM_CELL 0x1000
/* Compatibility with drivers coming from PPC32 world */
#define _machine (systemcfg->platform)
extern int pSeries_nvram_init(void);
extern int pmac_nvram_init(void);
-extern int bpa_nvram_init(void);
+extern int mmio_nvram_init(void);
/* PowerMac specific nvram stuffs */
projects / profile / ivi / kernel-x86-ivi.git / commitdiff