fix: remove asm code

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index b7be5e1..9d54201 100644 (file)
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,8 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)lib$(CPU).a
 
 START  = start.o
-#SOBJS = dcache.o icache.o irq.o disable_int.o enable_int.o
-SOBJS  = dcache.o icache.o irq.o
+SOBJS  = irq.o
 COBJS  = cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)

diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
index fc388eb..683044c 100644 (file)
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -45,4 +45,20 @@ int icache_status (void)
        __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
        return i;
 }
+
+void   icache_enable (void) {
+       __asm__ __volatile__ ("msrset r0, 0x80");
+}
+
+void   icache_disable(void) {
+       __asm__ __volatile__ ("msrclr r0, 0x80");
+}
+
+void   dcache_enable (void) {
+       __asm__ __volatile__ ("msrset r0, 0x20");
+}
+
+void   dcache_disable(void) {
+       __asm__ __volatile__ ("msrclr r0, 0x20");
+}
 #endif

diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S
deleted file mode 100644 (file)
index eaf9671..0000000
--- a/cpu/microblaze/dcache.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-       .text
-       .globl  dcache_enable
-       .ent    dcache_enable
-       .align  2
-dcache_enable:
-       /* Make space on stack for a temporary */
-       addi    r1, r1, -4
-       /* Save register r12 */
-       swi     r12, r1, 0
-       /* Read the MSR register */
-       mfs     r12, rmsr
-       /* Set the instruction enable bit */
-       ori     r12, r12, 0x80
-       /* Save the MSR register */
-       mts     rmsr, r12
-       /* Load register r12 */
-       lwi     r12, r1, 0
-       /* Return */
-       rtsd    r15, 8
-       /* Update stack in the delay slot */
-       addi    r1, r1, 4
-       .end    dcache_enable
-
-       .text
-       .globl  dcache_disable
-       .ent    dcache_disable
-       .align  2
-dcache_disable:
-       /* Make space on stack for a temporary */
-       addi    r1, r1, -4
-       /* Save register r12 */
-       swi     r12, r1, 0
-       /* Read the MSR register */
-       mfs     r12, rmsr
-       /* Clear the data cache enable bit */
-       andi    r12, r12, ~0x80
-       /* Save the MSR register */
-       mts     rmsr, r12
-       /* Load register r12 */
-       lwi     r12, r1, 0
-       /* Return */
-       rtsd    r15, 8
-       /* Update stack in the delay slot */
-       addi    r1, r1, 4
-       .end    dcache_disable

diff --git a/cpu/microblaze/disable_int.S b/cpu/microblaze/disable_int.S
deleted file mode 100644 (file)
index aecd795..0000000
--- a/cpu/microblaze/disable_int.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-       .text
-       .globl  microblaze_disable_interrupts
-       .ent    microblaze_disable_interrupts
-       .align  2
-microblaze_disable_interrupts:
-       #Make space on stack for a temporary
-       addi    r1, r1, -4
-       #Save register r12
-       swi     r12, r1, 0
-       #Read the MSR register
-       mfs     r12, rmsr
-       #Clear the interrupt enable bit
-       andi    r12, r12, ~2
-       #Save the MSR register
-       mts     rmsr, r12
-       #Load register r12
-       lwi     r12, r1, 0
-       #Return
-       rtsd    r15, 8
-       #Update stack in the delay slot
-       addi    r1, r1, 4
-       .end    microblaze_disable_interrupts

diff --git a/cpu/microblaze/enable_int.S b/cpu/microblaze/enable_int.S
deleted file mode 100644 (file)
index c096c6c..0000000
--- a/cpu/microblaze/enable_int.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstrmonstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-       .text
-       .globl  microblaze_enable_interrupts
-       .ent    microblaze_enable_interrupts
-       .align  2
-microblaze_enable_interrupts:
-       addi    r1, r1, -4
-       swi     r12, r1, 0
-       mfs     r12, rmsr
-       ori     r12, r12, 2
-       mts     rmsr, r12
-       lwi     r12, r1, 0
-       rtsd    r15, 8
-       addi    r1, r1, 4
-       .end    microblaze_enable_interrupts

diff --git a/cpu/microblaze/icache.S b/cpu/microblaze/icache.S
deleted file mode 100644 (file)
index 25940d1..0000000
--- a/cpu/microblaze/icache.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-       .text
-       .globl  icache_enable
-       .ent    icache_enable
-       .align  2
-icache_enable:
-       /* Make space on stack for a temporary */
-       addi    r1, r1, -4
-       /* Save register r12 */
-       swi     r12, r1, 0
-       /* Read the MSR register */
-       mfs     r12, rmsr
-       /* Set the instruction enable bit */
-       ori     r12, r12, 0x20
-       /* Save the MSR register */
-       mts     rmsr, r12
-       /* Load register r12 */
-       lwi     r12, r1, 0
-       /* Return */
-       rtsd    r15, 8
-       /* Update stack in the delay slot */
-       addi    r1, r1, 4
-       .end    icache_enable
-
-       .text
-       .globl  icache_disable
-       .ent    icache_disable
-       .align  2
-icache_disable:
-       /* Make space on stack for a temporary */
-       addi    r1, r1, -4
-       /* Save register r12 */
-       swi     r12, r1, 0
-       /* Read the MSR register */
-       mfs     r12, rmsr
-       /* Clear the instruction enable bit */
-       andi    r12, r12, ~0x20
-       /* Save the MSR register */
-       mts     rmsr, r12
-       /* Load register r12 */
-       lwi     r12, r1, 0
-       /* Return */
-       rtsd    r15, 8
-       /* Update stack in the delay slot */
-       addi    r1, r1, 4
-       .end    icache_disable