arm64: dts: qcom: sc8180x: Add interconnects and lmh
authorVinod Koul <vkoul@kernel.org>
Tue, 30 May 2023 16:24:46 +0000 (21:54 +0530)
committerBjorn Andersson <andersson@kernel.org>
Tue, 30 May 2023 17:18:29 +0000 (10:18 -0700)
This add interconnect nodes and add LMH to sc8180x SoC dtsi

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230530162454.51708-8-vkoul@kernel.org
arch/arm64/boot/dts/qcom/sc8180x.dtsi

index e38ea25..08f5ad6 100644 (file)
@@ -6,6 +6,8 @@
 
 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
+#include <dt-bindings/interconnect/qcom,sc8180x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -44,6 +46,8 @@
                        next-level-cache = <&L2_0>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
@@ -70,6 +74,8 @@
                        next-level-cache = <&L2_100>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD1>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
@@ -93,6 +99,8 @@
                        next-level-cache = <&L2_200>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD2>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_300>;
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD3>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_400>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        operating-points-v2 = <&cpu4_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD4>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_500>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        operating-points-v2 = <&cpu4_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD5>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_600>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        operating-points-v2 = <&cpu4_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD6>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
                        next-level-cache = <&L2_700>;
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        operating-points-v2 = <&cpu4_opp_table>;
+                       interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD7>;
                        power-domain-names = "psci";
                        #cooling-cells = <2>;
                };
        };
 
+       camnoc_virt: interconnect-camnoc-virt {
+               compatible = "qcom,sc8180x-camnoc-virt";
+               #interconnect-cells = <2>;
+               qcom,bcm-voters = <&apps_bcm_voter>;
+       };
+
+       mc_virt: interconnect-mc-virt {
+               compatible = "qcom,sc8180x-mc-virt";
+               #interconnect-cells = <2>;
+               qcom,bcm-voters = <&apps_bcm_voter>;
+       };
+
+       qup_virt: interconnect-qup-virt {
+               compatible = "qcom,sc8180x-qup-virt";
+               #interconnect-cells = <2>;
+               qcom,bcm-voters = <&apps_bcm_voter>;
+       };
+
        memory@80000000 {
                device_type = "memory";
                /* We expect the bootloader to fill in the size */
                                      "sleep_clk";
                };
 
+               config_noc: interconnect@1500000 {
+                       compatible = "qcom,sc8180x-config-noc";
+                       reg = <0 0x01500000 0 0x7400>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
+               system_noc: interconnect@1620000 {
+                       compatible = "qcom,sc8180x-system-noc";
+                       reg = <0 0x01620000 0 0x19400>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
+               aggre1_noc: interconnect@16e0000 {
+                       compatible = "qcom,sc8180x-aggre1-noc";
+                       reg = <0 0x016e0000 0 0xd080>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
+               aggre2_noc: interconnect@1700000 {
+                       compatible = "qcom,sc8180x-aggre2-noc";
+                       reg = <0 0x01700000 0 0x20000>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
+               compute_noc: interconnect@1720000 {
+                       compatible = "qcom,sc8180x-compute-noc";
+                       reg = <0 0x01720000 0 0x7000>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
+               mmss_noc: interconnect@1740000 {
+                       compatible = "qcom,sc8180x-mmss-noc";
+                       reg = <0 0x01740000 0 0x1c100>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
                ufs_mem_hc: ufshc@1d84000 {
                        compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
                                     "jedec,ufs-2.0";
                        };
                };
 
+               ipa_virt: interconnect@1e00000 {
+                       compatible = "qcom,sc8180x-ipa-virt";
+                       reg = <0 0x01e00000 0 0x1000>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x40000>;
                        interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               gem_noc: interconnect@9680000 {
+                       compatible = "qcom,sc8180x-gem-noc";
+                       reg = <0 0x09680000 0 0x58200>;
+                       #interconnect-cells = <2>;
+                       qcom,bcm-voters = <&apps_bcm_voter>;
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sc8180x-pdc", "qcom,pdc";
                        reg = <0 0x0b220000 0 0x30000>;
                        };
                };
 
+               osm_l3: interconnect@18321000 {
+                       compatible = "qcom,sc8180x-osm-l3";
+                       reg = <0 0x18321000 0 0x1400>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #interconnect-cells = <1>;
+               };
+
+               lmh@18350800 {
+                       compatible = "qcom,sc8180x-lmh";
+                       reg = <0 0x18350800 0 0x400>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       cpus = <&CPU4>;
+                       qcom,lmh-temp-arm-millicelsius = <65000>;
+                       qcom,lmh-temp-low-millicelsius = <94500>;
+                       qcom,lmh-temp-high-millicelsius = <95000>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+               };
+
+               lmh@18358800 {
+                       compatible = "qcom,sc8180x-lmh";
+                       reg = <0 0x18358800 0 0x400>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       cpus = <&CPU0>;
+                       qcom,lmh-temp-arm-millicelsius = <65000>;
+                       qcom,lmh-temp-low-millicelsius = <94500>;
+                       qcom,lmh-temp-high-millicelsius = <95000>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+               };
+
                cpufreq_hw: cpufreq@18323000 {
                        compatible = "qcom,cpufreq-hw";
                        reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;