intel/fs: Rework dynamic coarse handling

Use 2 flags for PI & RT messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 63562a2..0efcaa1 100644 (file)
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -865,10 +865,17 @@ enum brw_wm_msaa_flags {
 
    /** True if this shader has been dispatched coarse
     *
-    * This is intentionally chose to be bit 18 to correspond to the coarse
-    * write bit in the FB write message descriptor.
+    * This is intentionally chose to be bit 15 to correspond to the coarse bit
+    * in the pixel interpolator messages.
     */
-   BRW_WM_MSAA_FLAG_COARSE_DISPATCH = (1 << 18),
+   BRW_WM_MSAA_FLAG_COARSE_PI_MSG = (1 << 15),
+
+   /** True if this shader has been dispatched coarse
+    *
+    * This is intentionally chose to be bit 18 to correspond to the coarse bit
+    * in the render target messages.
+    */
+   BRW_WM_MSAA_FLAG_COARSE_RT_WRITES = (1 << 18),
 };
 MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(enum brw_wm_msaa_flags)
 
@@ -1154,12 +1161,12 @@ brw_wm_prog_data_is_coarse(const struct brw_wm_prog_data *prog_data,
                            enum brw_wm_msaa_flags pushed_msaa_flags)
 {
    if (pushed_msaa_flags & BRW_WM_MSAA_FLAG_ENABLE_DYNAMIC) {
-      if (pushed_msaa_flags & BRW_WM_MSAA_FLAG_COARSE_DISPATCH)
+      if (pushed_msaa_flags & BRW_WM_MSAA_FLAG_COARSE_RT_WRITES)
          assert(prog_data->coarse_pixel_dispatch != BRW_NEVER);
       else
          assert(prog_data->coarse_pixel_dispatch != BRW_ALWAYS);
 
-      return pushed_msaa_flags & BRW_WM_MSAA_FLAG_COARSE_DISPATCH;
+      return pushed_msaa_flags & BRW_WM_MSAA_FLAG_COARSE_RT_WRITES;
    }
 
    assert(prog_data->coarse_pixel_dispatch == BRW_ALWAYS ||

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index ab37b87..792432a 100644 (file)
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1468,7 +1468,7 @@ fs_visitor::emit_shading_rate_setup()
       return rate;
 
    check_dynamic_msaa_flag(abld, wm_prog_data,
-                           BRW_WM_MSAA_FLAG_COARSE_DISPATCH);
+                           BRW_WM_MSAA_FLAG_COARSE_RT_WRITES);
    set_predicate(BRW_PREDICATE_NORMAL, abld.SEL(rate, rate, brw_imm_ud(0)));
 
    return rate;

diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index 953c4ed..d21be91 100644 (file)
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -407,7 +407,7 @@ fs_visitor::emit_interpolation_setup_gfx6()
          abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0);
 
       check_dynamic_msaa_flag(dbld, wm_prog_data,
-                              BRW_WM_MSAA_FLAG_COARSE_DISPATCH);
+                              BRW_WM_MSAA_FLAG_COARSE_RT_WRITES);
 
       int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW);
       set_predicate(BRW_PREDICATE_NORMAL,

diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index dfbb823..a83ce22 100644 (file)
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -359,17 +359,17 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
       inst->desc =
          (inst->group / 16) << 11 | /* rt slot group */
          brw_fb_write_desc(devinfo, inst->target, msg_ctl, inst->last_rt,
-                           0 /* coarse_write */);
+                           0 /* coarse_rt_write */);
 
       fs_reg desc = brw_imm_ud(0);
       if (prog_data->coarse_pixel_dispatch == BRW_ALWAYS) {
          inst->desc |= (1 << 18);
       } else if (prog_data->coarse_pixel_dispatch == BRW_SOMETIMES) {
-         STATIC_ASSERT(BRW_WM_MSAA_FLAG_COARSE_DISPATCH == (1 << 18));
+         STATIC_ASSERT(BRW_WM_MSAA_FLAG_COARSE_RT_WRITES == (1 << 18));
          const fs_builder &ubld = bld.exec_all().group(8, 0);
          desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
          ubld.AND(desc, dynamic_msaa_flags(prog_data),
-                  brw_imm_ud(BRW_WM_MSAA_FLAG_COARSE_DISPATCH));
+                  brw_imm_ud(BRW_WM_MSAA_FLAG_COARSE_RT_WRITES));
          desc = component(desc, 0);
       }
 
@@ -2499,15 +2499,12 @@ lower_interpolator_logical_send(const fs_builder &bld, fs_inst *inst,
    if (wm_prog_data->coarse_pixel_dispatch == BRW_ALWAYS) {
       desc_imm |= (1 << 15);
    } else if (wm_prog_data->coarse_pixel_dispatch == BRW_SOMETIMES) {
+      STATIC_ASSERT(BRW_WM_MSAA_FLAG_COARSE_PI_MSG == (1 << 15));
       fs_reg orig_desc = desc;
       const fs_builder &ubld = bld.exec_all().group(8, 0);
       desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
       ubld.AND(desc, dynamic_msaa_flags(wm_prog_data),
-               brw_imm_ud(BRW_WM_MSAA_FLAG_COARSE_DISPATCH));
-
-      /* The uniform is in bit 18 but we need it in bit 15 */
-      STATIC_ASSERT(BRW_WM_MSAA_FLAG_COARSE_DISPATCH == (1 << 18));
-      ubld.SHR(desc, desc, brw_imm_ud(3));
+               brw_imm_ud(BRW_WM_MSAA_FLAG_COARSE_PI_MSG));
 
    /* And, if it's AT_OFFSET, we might have a non-trivial descriptor */
       if (orig_desc.file == IMM) {