This prevents clang from inlining and returning inconsistent results.
R=bmeurer@chromium.org
BUG=v8:3802
LOG=N
Review URL: https://codereview.chromium.org/
831393006
Cr-Commit-Position: refs/heads/master@{#26158}
} else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
// vsqrt
double dm_value = get_double_from_d_register(vm);
- double dd_value = std::sqrt(dm_value);
+ double dd_value = fast_sqrt(dm_value);
dd_value = canonicalizeNaN(dd_value);
set_d_register_from_double(vd, dd_value);
} else if (instr->Opc3Value() == 0x0) {
#include "src/arm64/decoder-arm64-inl.h"
#include "src/arm64/simulator-arm64.h"
#include "src/assembler.h"
+#include "src/codegen.h"
#include "src/disasm.h"
#include "src/macro-assembler.h"
#include "src/ostreams.h"
} else if (op < 0.0) {
return FPDefaultNaN<T>();
} else {
- return std::sqrt(op);
+ return fast_sqrt(op);
}
}
#include "src/assembler.h"
#include "src/base/bits.h"
+#include "src/codegen.h"
#include "src/disasm.h"
#include "src/mips/constants-mips.h"
#include "src/mips/simulator-mips.h"
set_fpu_register_double(fd_reg, -fs);
break;
case SQRT_D:
- set_fpu_register_double(fd_reg, sqrt(fs));
+ set_fpu_register_double(fd_reg, fast_sqrt(fs));
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
#include "src/assembler.h"
#include "src/base/bits.h"
+#include "src/codegen.h"
#include "src/disasm.h"
#include "src/mips64/constants-mips64.h"
#include "src/mips64/simulator-mips64.h"
set_fpu_register_double(fd_reg, -fs);
break;
case SQRT_D:
- set_fpu_register_double(fd_reg, sqrt(fs));
+ set_fpu_register_double(fd_reg, fast_sqrt(fs));
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
int frt = instr->RTValue();
int frb = instr->RBValue();
double frb_val = get_double_from_d_register(frb);
- double frt_val = std::sqrt(frb_val);
+ double frt_val = fast_sqrt(frb_val);
set_d_register_from_double(frt, frt_val);
return;
}