board: phytec: phycore-imx8mm: Add SPI-NOR flash support

Adds SPI-NOR flash support to erase, read and write in bootloader.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>

diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts
index a433261..e57dfd3 100644 (file)
--- a/arch/arm/dts/phycore-imx8mm.dts
+++ b/arch/arm/dts/phycore-imx8mm.dts
@@ -54,6 +54,23 @@
        };
 };
 
+/* SPI nor flash */
+&flexspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       flash0: norflash@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <80000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+};
+
 /* i2c eeprom */
 &i2c1 {
        clock-frequency = <400000>;
@@ -140,6 +157,17 @@
                >;
        };
 
+       pinctrl_flexspi0: flexspi0grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
+                       MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
+                       MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
+                       MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
+                       MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
+                       MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3

diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 91360b7..6cb2d36 100644 (file)
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
@@ -44,6 +45,7 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
@@ -78,6 +80,20 @@ CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_ESDHC_IMX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=3
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=80000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_DM_ETH=y
@@ -91,6 +107,9 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y