drm/vc4: Set AXI panic modes for the HVS

The HVS can change AXI request mode based on how full the COB
FIFOs are.
Until now the vc4 driver has been relying on the firmware to
have set these to sensible values.

With HVS channel 2 now being used for live video, change the
panic mode for all channels to be explicitly set by the driver,
and the same for all channels.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 8bfb9dcb4ba76e6dda2b7618702fdfa56ba25b7e..4e67dbf6c8ba59547e84daa5c4d2431492fe2953 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -1001,6 +1001,17 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
                      SCALER_DISPCTRL_DSPEISLUR(2) |
                      SCALER_DISPCTRL_SCLEIRQ);
 
+       /* Set AXI panic mode.
+        * VC4 panics when < 2 lines in FIFO.
+        * VC5 panics when less than 1 line in the FIFO.
+        */
+       dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
+                     SCALER_DISPCTRL_PANIC1_MASK |
+                     SCALER_DISPCTRL_PANIC2_MASK);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
+
        HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 
        /* Recompute Composite Output Buffer (COB) allocations for the displays

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 82b0fdabe2a02e90db7a4d7b4f0ed74355bf498b..0b61f09c925ccb7e23ebaa9ae1aab88fca63dca9 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -220,6 +220,12 @@
 #define SCALER_DISPCTRL                         0x00000000
 /* Global register for clock gating the HVS */
 # define SCALER_DISPCTRL_ENABLE                        BIT(31)
+# define SCALER_DISPCTRL_PANIC0_MASK           VC4_MASK(25, 24)
+# define SCALER_DISPCTRL_PANIC0_SHIFT          24
+# define SCALER_DISPCTRL_PANIC1_MASK           VC4_MASK(27, 26)
+# define SCALER_DISPCTRL_PANIC1_SHIFT          26
+# define SCALER_DISPCTRL_PANIC2_MASK           VC4_MASK(29, 28)
+# define SCALER_DISPCTRL_PANIC2_SHIFT          28
 # define SCALER_DISPCTRL_DSP3_MUX_MASK         VC4_MASK(19, 18)
 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT                18