MIPS: Add support for the M5150 processor

The M5150 core is a 32-bit MIPS RISC which implements the
MIPS Architecture Release-5  in a 5-stage pipeline.
In addition, it includes the MIPS Architecture Virtualization Module
that enables virtualization of operating systems,
which provides a scalable, trusted, and secure execution environment.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 61f803b..760c9cf 100644 (file)
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -47,6 +47,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
        case CPU_P5600:
+       case CPU_M5150:
 #endif
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 1611132..64b4b69 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -298,7 +298,7 @@ enum cpu_type_enum {
        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
-       CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
+       CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
 
        /*
         * MIPS64 class processors

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 04ea1c7..9f904ed 100644 (file)
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -188,6 +188,7 @@ void __init check_wait(void)
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
        case CPU_P5600:
+       case CPU_M5150:
                cpu_wait = r4k_wait;
                if (read_c0_config7() & MIPS_CONF7_WII)
                        cpu_wait = r4k_wait_irqoff;

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a62b637..3e53f1b 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1173,6 +1173,7 @@ static void probe_pcache(void)
        case CPU_INTERAPTIV:
        case CPU_P5600:
        case CPU_PROAPTIV:
+       case CPU_M5150:
                if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K))
                        alias_74k_erratum(c);
                if (!(read_c0_config7() & MIPS_CONF7_IAR) &&

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ccae9a4..be407d5 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -512,6 +512,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
                case CPU_1074K:
                case CPU_PROAPTIV:
                case CPU_P5600:
+               case CPU_M5150:
                        break;
 
                default:

diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index e4ca70b..e747324 100644 (file)
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -90,6 +90,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
        case CPU_P5600:
+       case CPU_M5150:
        case CPU_LOONGSON1:
        case CPU_SB1:
        case CPU_SB1A:

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 9797493..42821ae 100644 (file)
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -389,6 +389,10 @@ static int __init mipsxx_init(void)
                op_model_mipsxx_ops.cpu_type = "mips/P5600";
                break;
 
+       case CPU_M5150:
+               op_model_mipsxx_ops.cpu_type = "mips/M5150";
+               break;
+
        case CPU_5KC:
                op_model_mipsxx_ops.cpu_type = "mips/5K";
                break;