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ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
author
Russell King
<rmk+kernel@arm.linux.org.uk>
Fri, 26 Aug 2011 23:37:38 +0000
(
00:37
+0100)
committer
Russell King
<rmk+kernel@arm.linux.org.uk>
Sun, 28 Aug 2011 09:39:54 +0000
(10:39 +0100)
Add a dsb after the isb to ensure that the previous writes to the
CP15 registers take effect before we enable the MMU.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/proc-v7.S
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diff --git
a/arch/arm/mm/proc-v7.S
b/arch/arm/mm/proc-v7.S
index
dec72ee
..
a773f4e
100644
(file)
--- a/
arch/arm/mm/proc-v7.S
+++ b/
arch/arm/mm/proc-v7.S
@@
-255,6
+255,7
@@
ENTRY(cpu_v7_do_resume)
mcr p15, 0, r4, c10, c2, 0 @ write PRRR
mcr p15, 0, r5, c10, c2, 1 @ write NMRR
isb
+ dsb
mov r0, r9 @ control register
mov r2, r7, lsr #14 @ get TTB0 base
mov r2, r2, lsl #14