Merge branch 'drm-fixes-5.0' of git://people.freedesktop.org/~agd5f/linux into drm...

- Powerplay fixes
- Virtual display pinning fixes
- Golden register updates for vega
- Pitch and gem size validation fixes
- Fix for error case in sr-iov init
- Disable page tables in system memory on RV due to issues with IOMMU
  reported on some platforms

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190109204336.3315-1-alexander.deucher@amd.com

diff --combined drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e73d152,a0a11d3..d2ea5ce
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@@ -181,7 -181,7 +181,7 @@@ static unsigned amdgpu_vm_num_entries(s
  
        if (level == adev->vm_manager.root_level)
                /* For the root directory */
 -              return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
 +              return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
        else if (level != AMDGPU_VM_PTB)
                /* Everything in between */
                return 512;
@@@ -847,9 -847,6 +847,6 @@@ static void amdgpu_vm_bo_param(struct a
        bp->size = amdgpu_vm_bo_size(adev, level);
        bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
        bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-       if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 &&
-           adev->flags & AMD_IS_APU)
-               bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
        bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
        bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
                AMDGPU_GEM_CREATE_CPU_GTT_USWC;
@@@ -1653,11 -1650,9 +1650,11 @@@ static int amdgpu_vm_update_ptes(struc
                        if (!amdgpu_vm_pt_descendant(adev, &cursor))
                                return -ENOENT;
                        continue;
 -              } else if (frag >= parent_shift) {
 +              } else if (frag >= parent_shift &&
 +                         cursor.level - 1 != adev->vm_manager.root_level) {
                        /* If the fragment size is even larger than the parent
 -                       * shift we should go up one level and check it again.
 +                       * shift we should go up one level and check it again
 +                       * unless one level up is the root level.
                         */
                        if (!amdgpu_vm_pt_ancestor(&cursor))
                                return -ENOENT;
@@@ -1665,10 -1660,10 +1662,10 @@@
                }
  
                /* Looks good so far, calculate parameters for the update */
 -              incr = AMDGPU_GPU_PAGE_SIZE << shift;
 +              incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
                mask = amdgpu_vm_entries_mask(adev, cursor.level);
                pe_start = ((cursor.pfn >> shift) & mask) * 8;
 -              entry_end = (mask + 1) << shift;
 +              entry_end = (uint64_t)(mask + 1) << shift;
                entry_end += cursor.pfn & ~(entry_end - 1);
                entry_end = min(entry_end, end);
  
@@@ -1681,7 -1676,7 +1678,7 @@@
                                              flags | AMDGPU_PTE_FRAG(frag));
  
                        pe_start += nptes * 8;
 -                      dst += nptes * AMDGPU_GPU_PAGE_SIZE << shift;
 +                      dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
  
                        frag_start = upd_end;
                        if (frag_start >= frag_end) {

diff --combined drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7556716,59a5d8f..fbca049
--- 1/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@@ -113,7 -113,10 +113,10 @@@ static const struct soc15_reg_golden go
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
  };
  
  static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
@@@ -135,10 -138,7 +138,7 @@@
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
  };
  
  static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
@@@ -2340,13 -2340,12 +2340,13 @@@ static void gfx_v9_0_rlc_start(struct a
  #endif
  
        WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
 +      udelay(50);
  
        /* carrizo do enable cp interrupt after cp inited */
 -      if (!(adev->flags & AMD_IS_APU))
 +      if (!(adev->flags & AMD_IS_APU)) {
                gfx_v9_0_enable_gui_idle_interrupt(adev, true);
 -
 -      udelay(50);
 +              udelay(50);
 +      }
  
  #ifdef AMDGPU_RLC_DEBUG_RETRY
        /* RLC_GPM_GENERAL_6 : RLC Ucode version */
@@@ -3587,6 -3586,8 +3587,8 @@@ static void gfx_v9_0_update_medium_grai
  {
        uint32_t data, def;
  
+       amdgpu_gfx_rlc_enter_safe_mode(adev);
+ 
        /* It is disabled by HW by default */
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
                /* 1 - RLC_CGTT_MGCG_OVERRIDE */
@@@ -3651,6 -3652,8 +3653,8 @@@
                        WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
                }
        }
+ 
+       amdgpu_gfx_rlc_exit_safe_mode(adev);
  }
  
  static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,

diff --combined drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 0173d04,472263a..310b102
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@@ -64,17 -64,19 +64,19 @@@ static int ci_set_asic_special_caps(str
  
  static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
  {
-       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
-       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
-       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
-       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
-       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
+       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
+       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
+       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
+       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
+       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
+       hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
  
-       hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
-       hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
-       hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
-       hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
-       hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
+       hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+       hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+       hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
+       hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
+       hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
+       hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
  }
  
  int hwmgr_early_init(struct pp_hwmgr *hwmgr)
@@@ -352,9 -354,6 +354,9 @@@ int hwmgr_handle_task(struct pp_hwmgr *
  
        switch (task_id) {
        case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
 +              ret = phm_pre_display_configuration_changed(hwmgr);
 +              if (ret)
 +                      return ret;
                ret = phm_set_cpu_power_state(hwmgr);
                if (ret)
                        return ret;

diff --combined drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index d913904,13d65fd..c8f5c00
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@@ -77,8 -77,9 +77,9 @@@
  #define PCIE_BUS_CLK                10000
  #define TCLK                        (PCIE_BUS_CLK / 10)
  
- static const struct profile_mode_setting smu7_profiling[6] =
-                                       {{1, 0, 100, 30, 1, 0, 100, 10},
+ static const struct profile_mode_setting smu7_profiling[7] =
+                                       {{0, 0, 0, 0, 0, 0, 0, 0},
+                                        {1, 0, 100, 30, 1, 0, 100, 10},
                                         {1, 10, 0, 30, 0, 0, 0, 0},
                                         {0, 0, 0, 0, 1, 10, 16, 31},
                                         {1, 0, 11, 50, 1, 0, 100, 10},
@@@ -3592,10 -3593,8 +3593,10 @@@ static int smu7_find_dpm_states_clocks_
        }
  
        if (i >= sclk_table->count) {
 -              data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
 -              sclk_table->dpm_levels[i-1].value = sclk;
 +              if (sclk > sclk_table->dpm_levels[i-1].value) {
 +                      data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
 +                      sclk_table->dpm_levels[i-1].value = sclk;
 +              }
        } else {
        /* TODO: Check SCLK in DAL's minimum clocks
         * in case DeepSleep divider update is required.
@@@ -3612,10 -3611,8 +3613,10 @@@
        }
  
        if (i >= mclk_table->count) {
 -              data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
 -              mclk_table->dpm_levels[i-1].value = mclk;
 +              if (mclk > mclk_table->dpm_levels[i-1].value) {
 +                      data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
 +                      mclk_table->dpm_levels[i-1].value = mclk;
 +              }
        }
  
        if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
@@@ -4889,7 -4886,8 +4890,8 @@@ static int smu7_get_power_profile_mode(
        uint32_t i, size = 0;
        uint32_t len;
  
-       static const char *profile_name[6] = {"3D_FULL_SCREEN",
+       static const char *profile_name[7] = {"BOOTUP_DEFAULT",
+                                       "3D_FULL_SCREEN",
                                        "POWER_SAVING",
                                        "VIDEO",
                                        "VR",

diff --combined drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 79c8624,a4221b9..91e3bbe
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@@ -804,9 -804,9 +804,9 @@@ static int vega10_hwmgr_backend_init(st
  
        hwmgr->backend = data;
  
-       hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
-       hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
-       hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+       hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
+       hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+       hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
  
        vega10_set_default_registry_data(hwmgr);
        data->disable_dpm_mask = 0xff;
@@@ -3266,10 -3266,8 +3266,10 @@@ static int vega10_find_dpm_states_clock
        }
  
        if (i >= sclk_table->count) {
 -              data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
 -              sclk_table->dpm_levels[i-1].value = sclk;
 +              if (sclk > sclk_table->dpm_levels[i-1].value) {
 +                      data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
 +                      sclk_table->dpm_levels[i-1].value = sclk;
 +              }
        }
  
        for (i = 0; i < mclk_table->count; i++) {
@@@ -3278,10 -3276,8 +3278,10 @@@
        }
  
        if (i >= mclk_table->count) {
 -              data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
 -              mclk_table->dpm_levels[i-1].value = mclk;
 +              if (mclk > mclk_table->dpm_levels[i-1].value) {
 +                      data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
 +                      mclk_table->dpm_levels[i-1].value = mclk;
 +              }
        }
  
        if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
@@@ -4668,13 -4664,15 +4668,15 @@@ static int vega10_get_power_profile_mod
  {
        struct vega10_hwmgr *data = hwmgr->backend;
        uint32_t i, size = 0;
-       static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
+       static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
+                                               {70, 60, 1, 3,},
                                                {90, 60, 0, 0,},
                                                {70, 60, 0, 0,},
                                                {70, 90, 0, 0,},
                                                {30, 60, 0, 6,},
                                                };
-       static const char *profile_name[6] = {"3D_FULL_SCREEN",
+       static const char *profile_name[7] = {"BOOTUP_DEFAULT",
+                                       "3D_FULL_SCREEN",
                                        "POWER_SAVING",
                                        "VIDEO",
                                        "VR",

diff --combined drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 26154f9,5824213..82935a3
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@@ -134,7 -134,7 +134,7 @@@ static void vega20_set_default_registry
        data->registry_data.disable_auto_wattman = 1;
        data->registry_data.auto_wattman_debug = 0;
        data->registry_data.auto_wattman_sample_period = 100;
 -      data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
 +      data->registry_data.fclk_gfxclk_ratio = 0;
        data->registry_data.auto_wattman_threshold = 50;
        data->registry_data.gfxoff_controlled_by_driver = 1;
        data->gfxoff_allowed = false;
@@@ -390,9 -390,9 +390,9 @@@ static int vega20_hwmgr_backend_init(st
  
        hwmgr->backend = data;
  
-       hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
-       hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
-       hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+       hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
+       hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+       hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
  
        vega20_set_default_registry_data(hwmgr);
  
@@@ -980,6 -980,9 +980,9 @@@ static int vega20_od8_set_feature_capab
            pp_table->FanZeroRpmEnable)
                od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
  
+       if (!od_settings->overdrive8_capabilities)
+               hwmgr->od_enabled = false;
+ 
        return 0;
  }
  
@@@ -1664,15 -1667,14 +1667,15 @@@ static uint32_t vega20_find_highest_dpm
        return i;
  }
  
 -static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
 +static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
  {
        struct vega20_hwmgr *data =
                        (struct vega20_hwmgr *)(hwmgr->backend);
        uint32_t min_freq;
        int ret = 0;
  
 -      if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 +      if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
 +         (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
                min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
                                        hwmgr, PPSMC_MSG_SetSoftMinByFreq,
@@@ -1681,25 -1683,16 +1684,18 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 +      if (data->smu_features[GNLD_DPM_UCLK].enabled &&
 +         (feature_mask & FEATURE_DPM_UCLK_MASK)) {
                min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
                                        hwmgr, PPSMC_MSG_SetSoftMinByFreq,
                                        (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
                                        "Failed to set soft min memclk !",
                                        return ret);
- 
-               min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
-               PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
-                                       hwmgr, PPSMC_MSG_SetHardMinByFreq,
-                                       (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
-                                       "Failed to set hard min memclk !",
-                                       return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_UVD].enabled) {
 +      if (data->smu_features[GNLD_DPM_UVD].enabled &&
 +         (feature_mask & FEATURE_DPM_UVD_MASK)) {
                min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1717,8 -1710,7 +1713,8 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_VCE].enabled) {
 +      if (data->smu_features[GNLD_DPM_VCE].enabled &&
 +         (feature_mask & FEATURE_DPM_VCE_MASK)) {
                min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1728,8 -1720,7 +1724,8 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 +      if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
 +         (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
                min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1742,15 -1733,14 +1738,15 @@@
        return ret;
  }
  
 -static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
 +static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
  {
        struct vega20_hwmgr *data =
                        (struct vega20_hwmgr *)(hwmgr->backend);
        uint32_t max_freq;
        int ret = 0;
  
 -      if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 +      if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
 +         (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
                max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1760,8 -1750,7 +1756,8 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 +      if (data->smu_features[GNLD_DPM_UCLK].enabled &&
 +         (feature_mask & FEATURE_DPM_UCLK_MASK)) {
                max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1771,8 -1760,7 +1767,8 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_UVD].enabled) {
 +      if (data->smu_features[GNLD_DPM_UVD].enabled &&
 +         (feature_mask & FEATURE_DPM_UVD_MASK)) {
                max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1789,8 -1777,7 +1785,8 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_VCE].enabled) {
 +      if (data->smu_features[GNLD_DPM_VCE].enabled &&
 +         (feature_mask & FEATURE_DPM_VCE_MASK)) {
                max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -1800,8 -1787,7 +1796,8 @@@
                                        return ret);
        }
  
 -      if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 +      if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
 +         (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
                max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
  
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@@ -2140,12 -2126,12 +2136,12 @@@ static int vega20_force_dpm_highest(str
                data->dpm_table.mem_table.dpm_state.soft_max_level =
                data->dpm_table.mem_table.dpm_levels[soft_level].value;
  
 -      ret = vega20_upload_dpm_min_level(hwmgr);
 +      ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
        PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload boot level to highest!",
                        return ret);
  
 -      ret = vega20_upload_dpm_max_level(hwmgr);
 +      ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
        PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload dpm max level to highest!",
                        return ret);
@@@ -2172,12 -2158,12 +2168,12 @@@ static int vega20_force_dpm_lowest(stru
                data->dpm_table.mem_table.dpm_state.soft_max_level =
                data->dpm_table.mem_table.dpm_levels[soft_level].value;
  
 -      ret = vega20_upload_dpm_min_level(hwmgr);
 +      ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
        PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload boot level to highest!",
                        return ret);
  
 -      ret = vega20_upload_dpm_max_level(hwmgr);
 +      ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
        PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload dpm max level to highest!",
                        return ret);
@@@ -2190,12 -2176,12 +2186,12 @@@ static int vega20_unforce_dpm_levels(st
  {
        int ret = 0;
  
 -      ret = vega20_upload_dpm_min_level(hwmgr);
 +      ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
        PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload DPM Bootup Levels!",
                        return ret);
  
 -      ret = vega20_upload_dpm_max_level(hwmgr);
 +      ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
        PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload DPM Max Levels!",
                        return ret);
@@@ -2248,17 -2234,24 +2244,24 @@@ static int vega20_force_clock_level(str
                soft_min_level = mask ? (ffs(mask) - 1) : 0;
                soft_max_level = mask ? (fls(mask) - 1) : 0;
  
+               if (soft_max_level >= data->dpm_table.gfx_table.count) {
+                       pr_err("Clock level specified %d is over max allowed %d\n",
+                                       soft_max_level,
+                                       data->dpm_table.gfx_table.count - 1);
+                       return -EINVAL;
+               }
+ 
                data->dpm_table.gfx_table.dpm_state.soft_min_level =
                        data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
                data->dpm_table.gfx_table.dpm_state.soft_max_level =
                        data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
  
 -              ret = vega20_upload_dpm_min_level(hwmgr);
 +              ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
                PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload boot level to lowest!",
                        return ret);
  
 -              ret = vega20_upload_dpm_max_level(hwmgr);
 +              ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
                PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload dpm max level to highest!",
                        return ret);
@@@ -2268,17 -2261,24 +2271,24 @@@
                soft_min_level = mask ? (ffs(mask) - 1) : 0;
                soft_max_level = mask ? (fls(mask) - 1) : 0;
  
+               if (soft_max_level >= data->dpm_table.mem_table.count) {
+                       pr_err("Clock level specified %d is over max allowed %d\n",
+                                       soft_max_level,
+                                       data->dpm_table.mem_table.count - 1);
+                       return -EINVAL;
+               }
+ 
                data->dpm_table.mem_table.dpm_state.soft_min_level =
                        data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
                data->dpm_table.mem_table.dpm_state.soft_max_level =
                        data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
  
 -              ret = vega20_upload_dpm_min_level(hwmgr);
 +              ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
                PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload boot level to lowest!",
                        return ret);
  
 -              ret = vega20_upload_dpm_max_level(hwmgr);
 +              ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
                PP_ASSERT_WITH_CODE(!ret,
                        "Failed to upload dpm max level to highest!",
                        return ret);
@@@ -3261,6 -3261,9 +3271,9 @@@ static int conv_power_profile_to_pplib_
        int pplib_workload = 0;
  
        switch (power_profile) {
+       case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
+               pplib_workload = WORKLOAD_DEFAULT_BIT;
+               break;
        case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
                pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
                break;
@@@ -3290,6 -3293,7 +3303,7 @@@ static int vega20_get_power_profile_mod
        uint32_t i, size = 0;
        uint16_t workload_type = 0;
        static const char *profile_name[] = {
+                                       "BOOTUP_DEFAULT",
                                        "3D_FULL_SCREEN",
                                        "POWER_SAVING",
                                        "VIDEO",