*/
#define RSND_SCU_USE_HPBIF (1 << 31) /* it needs RSND_SSI_DEPENDENT */
+#define RSND_SCU_SET(rate, _dma_id) \
+ { .flags = RSND_SCU_USE_HPBIF, .convert_rate = rate, .dma_id = _dma_id, }
+#define RSND_SCU_UNUSED \
+ { .flags = 0, .convert_rate = 0, .dma_id = 0, }
+
struct rsnd_scu_platform_info {
u32 flags;
u32 convert_rate; /* sampling rate convert */
+ int dma_id; /* for Gen2 SCU */
};
/*
i++, (pos) = adg->clk[i])
#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
+
+static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_mod *mod)
+{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
+ int id = rsnd_mod_id(mod);
+ int ws = id;
+
+ if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
+ switch (id) {
+ case 1:
+ case 2:
+ ws = 0;
+ break;
+ case 4:
+ ws = 3;
+ break;
+ case 8:
+ ws = 7;
+ break;
+ }
+ }
+
+ return (0x6 + ws) << 8;
+}
+
+static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai,
+ struct rsnd_mod *mod,
+ struct rsnd_dai_stream *io,
+ u32 timsel)
+{
+ int is_play = rsnd_dai_is_play(rdai, io);
+ int id = rsnd_mod_id(mod);
+ int shift = (id % 2) ? 16 : 0;
+ u32 mask, ws;
+ u32 in, out;
+
+ ws = rsnd_adg_ssi_ws_timing_gen2(mod);
+
+ in = (is_play) ? timsel : ws;
+ out = (is_play) ? ws : timsel;
+
+ in = in << shift;
+ out = out << shift;
+ mask = 0xffff << shift;
+
+ switch (id / 2) {
+ case 0:
+ rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in);
+ rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
+ break;
+ case 1:
+ rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in);
+ rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
+ break;
+ case 2:
+ rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in);
+ rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
+ break;
+ case 3:
+ rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in);
+ rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
+ break;
+ case 4:
+ rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in);
+ rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
+ break;
+ }
+
+ return 0;
+}
+
+int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io,
+ unsigned int src_rate,
+ unsigned int dst_rate)
+{
+ struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
+ struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
+ struct device *dev = rsnd_priv_to_dev(priv);
+ int idx, sel, div, step;
+ u32 val;
+ unsigned int min, diff;
+ unsigned int sel_rate [] = {
+ clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
+ clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
+ clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
+ adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
+ adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
+ };
+
+ min = ~0;
+ val = 0;
+ for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
+ idx = 0;
+ step = 2;
+
+ if (!sel_rate[sel])
+ continue;
+
+ for (div = 2; div <= 98304; div += step) {
+ diff = abs(src_rate - sel_rate[sel] / div);
+ if (min > diff) {
+ val = (sel << 8) | idx;
+ min = diff;
+ }
+
+ /*
+ * step of 0_0000 / 0_0001 / 0_1101
+ * are out of order
+ */
+ if ((idx > 2) && (idx % 2))
+ step *= 2;
+ if (idx == 0x1c) {
+ div += step;
+ step *= 2;
+ }
+ idx++;
+ }
+ }
+
+ if (min == ~0) {
+ dev_err(dev, "no Input clock\n");
+ return -EIO;
+ }
+
+ return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
+}
+
+int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io)
+{
+ u32 val = rsnd_adg_ssi_ws_timing_gen2(mod);
+
+ return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
+}
+
int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
struct rsnd_mod *mod,
unsigned int src_rate,
RSND_GEN2_S_REG(gen, SSIU, SSI_MODE0, 0x800),
RSND_GEN2_S_REG(gen, SSIU, SSI_MODE1, 0x804),
/* FIXME: it needs SSI_MODE2/3 in the future */
+ RSND_GEN2_S_REG(gen, SSIU, SSI_CONTROL, 0x810),
+ RSND_GEN2_M_REG(gen, SSIU, SSI_BUSIF_MODE, 0x0, 0x80),
+ RSND_GEN2_M_REG(gen, SSIU, SSI_BUSIF_ADINR,0x4, 0x80),
+ RSND_GEN2_M_REG(gen, SSIU, SSI_CTRL, 0x10, 0x80),
RSND_GEN2_M_REG(gen, SSIU, INT_ENABLE, 0x18, 0x80),
+ RSND_GEN2_M_REG(gen, SCU, SRC_BUSIF_MODE, 0x0, 0x20),
+ RSND_GEN2_M_REG(gen, SCU, SRC_ROUTE_MODE0,0xc, 0x20),
+ RSND_GEN2_M_REG(gen, SCU, SRC_CTRL, 0x10, 0x20),
+ RSND_GEN2_M_REG(gen, SCU, SRC_SWRSR, 0x200, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_SRCIR, 0x204, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_ADINR, 0x214, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_IFSCR, 0x21c, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_IFSVR, 0x220, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_SRCCR, 0x224, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_BSDSR, 0x22c, 0x40),
+ RSND_GEN2_M_REG(gen, SCU, SRC_BSISR, 0x238, 0x40),
+
RSND_GEN2_S_REG(gen, ADG, BRRA, 0x00),
RSND_GEN2_S_REG(gen, ADG, BRRB, 0x04),
RSND_GEN2_S_REG(gen, ADG, SSICKR, 0x08),
RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL0, 0x0c),
RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL1, 0x10),
RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL2, 0x14),
+ RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL0, 0x34),
+ RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL1, 0x38),
+ RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL2, 0x3c),
+ RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL3, 0x40),
+ RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL4, 0x44),
+ RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL0, 0x48),
+ RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL1, 0x4c),
+ RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL2, 0x50),
+ RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL3, 0x54),
+ RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL4, 0x58),
RSND_GEN2_M_REG(gen, SSI, SSICR, 0x00, 0x40),
RSND_GEN2_M_REG(gen, SSI, SSISR, 0x04, 0x40),
RSND_REG_SRC_TMG_SEL1, /* for Gen1 */
RSND_REG_SRC_TMG_SEL2, /* for Gen1 */
RSND_REG_SRC_ROUTE_CTRL, /* for Gen1 */
+ RSND_REG_SRC_CTRL, /* for Gen2 */
+ RSND_REG_SSI_CTRL, /* for Gen2 */
+ RSND_REG_SSI_CONTROL,
+ RSND_REG_SSI_BUSIF_MODE, /* for Gen2 */
+ RSND_REG_SSI_BUSIF_ADINR, /* for Gen2 */
RSND_REG_SSI_MODE0,
RSND_REG_SSI_MODE1,
RSND_REG_INT_ENABLE, /* for Gen2 */
RSND_REG_SRC_IFSVR,
RSND_REG_SRC_SRCCR,
RSND_REG_SRC_MNFSR, /* for Gen1 */
+ RSND_REG_SRC_BSDSR, /* for Gen2 */
+ RSND_REG_SRC_BSISR, /* for Gen2 */
/* ADG */
RSND_REG_BRRA,
RSND_REG_AUDIO_CLK_SEL3, /* for Gen1 */
RSND_REG_AUDIO_CLK_SEL4, /* for Gen1 */
RSND_REG_AUDIO_CLK_SEL5, /* for Gen1 */
+ RSND_REG_SRCIN_TIMSEL0, /* for Gen2 */
+ RSND_REG_SRCIN_TIMSEL1, /* for Gen2 */
+ RSND_REG_SRCIN_TIMSEL2, /* for Gen2 */
+ RSND_REG_SRCIN_TIMSEL3, /* for Gen2 */
+ RSND_REG_SRCIN_TIMSEL4, /* for Gen2 */
+ RSND_REG_SRCOUT_TIMSEL0, /* for Gen2 */
+ RSND_REG_SRCOUT_TIMSEL1, /* for Gen2 */
+ RSND_REG_SRCOUT_TIMSEL2, /* for Gen2 */
+ RSND_REG_SRCOUT_TIMSEL3, /* for Gen2 */
+ RSND_REG_SRCOUT_TIMSEL4, /* for Gen2 */
/* SSI */
RSND_REG_SSICR,
struct rsnd_mod *mod,
unsigned int src_rate,
unsigned int dst_rate);
+int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io,
+ unsigned int src_rate,
+ unsigned int dst_rate);
+int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io);
/*
* R-Car sound priv
container_of((_mod), struct rsnd_scu, mod)
#define rsnd_scu_hpbif_is_enable(scu) \
(rsnd_scu_mode_flags(scu) & RSND_SCU_USE_HPBIF)
+#define rsnd_scu_dma_available(scu) \
+ rsnd_dma_available(rsnd_mod_to_dma(&(scu)->mod))
#define for_each_rsnd_scu(pos, priv, i) \
for ((i) = 0; \
/*
* Gen2 functions
*/
+static int rsnd_scu_set_convert_rate_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io)
+{
+ int ret;
+
+ ret = rsnd_scu_set_convert_rate(mod, rdai, io);
+ if (ret < 0)
+ return ret;
+
+ rsnd_mod_write(mod, SSI_BUSIF_ADINR, rsnd_mod_read(mod, SRC_ADINR));
+ rsnd_mod_write(mod, SSI_BUSIF_MODE, rsnd_mod_read(mod, SRC_BUSIF_MODE));
+
+ rsnd_mod_write(mod, SRC_SRCCR, 0x00011110);
+
+ rsnd_mod_write(mod, SRC_BSDSR, 0x01800000);
+ rsnd_mod_write(mod, SRC_BSISR, 0x00100060);
+
+ return 0;
+}
+
+static int rsnd_scu_set_convert_timing_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io)
+{
+ struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
+ struct rsnd_scu *scu = rsnd_mod_to_scu(mod);
+ u32 convert_rate = rsnd_scu_convert_rate(scu);
+ int ret;
+
+ if (convert_rate)
+ ret = rsnd_adg_set_convert_clk_gen2(mod, rdai, io,
+ runtime->rate,
+ convert_rate);
+ else
+ ret = rsnd_adg_set_convert_timing_gen2(mod, rdai, io);
+
+ return ret;
+}
+
+static int rsnd_scu_init_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io)
+{
+ int ret;
+
+ ret = rsnd_scu_init(mod, rdai, io);
+ if (ret < 0)
+ return ret;
+
+ ret = rsnd_scu_set_convert_rate_gen2(mod, rdai, io);
+ if (ret < 0)
+ return ret;
+
+ ret = rsnd_scu_set_convert_timing_gen2(mod, rdai, io);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int rsnd_scu_start_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io)
+{
+ struct rsnd_scu *scu = rsnd_mod_to_scu(mod);
+
+ rsnd_dma_start(rsnd_mod_to_dma(&scu->mod));
+
+ rsnd_mod_write(mod, SSI_CTRL, 0x1);
+ rsnd_mod_write(mod, SRC_CTRL, 0x11);
+
+ return rsnd_scu_start(mod, rdai, io);
+}
+
+static int rsnd_scu_stop_gen2(struct rsnd_mod *mod,
+ struct rsnd_dai *rdai,
+ struct rsnd_dai_stream *io)
+{
+ struct rsnd_scu *scu = rsnd_mod_to_scu(mod);
+
+ rsnd_mod_write(mod, SSI_CTRL, 0);
+ rsnd_mod_write(mod, SRC_CTRL, 0);
+
+ rsnd_dma_stop(rsnd_mod_to_dma(&scu->mod));
+
+ return rsnd_scu_stop(mod, rdai, io);
+}
+
+static struct rsnd_mod_ops rsnd_scu_gen2_ops = {
+ .name = "scu (gen2)",
+ .init = rsnd_scu_init_gen2,
+ .quit = rsnd_scu_quit,
+ .start = rsnd_scu_start_gen2,
+ .stop = rsnd_scu_stop_gen2,
+};
+
static int rsnd_scu_start_non_gen2(struct rsnd_mod *mod,
struct rsnd_dai *rdai,
struct rsnd_dai_stream *io)
if (rsnd_scu_hpbif_is_enable(scu)) {
if (rsnd_is_gen1(priv))
ops = &rsnd_scu_gen1_ops;
+ if (rsnd_is_gen2(priv)) {
+ struct rsnd_mod *ssi = rsnd_ssi_mod_get(priv, i);
+ int ret = rsnd_dma_init(priv,
+ rsnd_mod_to_dma(&scu->mod),
+ rsnd_ssi_is_play(ssi),
+ scu->info->dma_id);
+ if (ret < 0)
+ return ret;
+
+ ops = &rsnd_scu_gen2_ops;
+ }
} else {
if (rsnd_is_gen1(priv))
ops = &rsnd_scu_non_gen1_ops;
void rsnd_scu_remove(struct platform_device *pdev,
struct rsnd_priv *priv)
{
+ struct rsnd_scu *scu;
+ int i;
+
+ for_each_rsnd_scu(scu, priv, i) {
+ if (rsnd_scu_dma_available(scu))
+ rsnd_dma_quit(priv, rsnd_mod_to_dma(&scu->mod));
+ }
}
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