[ ]*[a-f0-9]+: cf iretl
[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 0f 07 sysretl
+[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcxl %ecx,%edx
+[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adoxl %ecx,%edx
#pass
[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 48 89 e5 movq %rsp,%rbp
[ ]*[a-f0-9]+: 48 0f 07 sysretq
+[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcxl %ecx,%edx
+[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adoxl %ecx,%edx
+[ ]*[a-f0-9]+: 66 48 0f 38 f6 d1 adcxq %rcx,%rdx
+[ ]*[a-f0-9]+: f3 48 0f 38 f6 d1 adoxq %rcx,%rdx
#pass
'I' unused.
'J' unused.
'K' => print 'd' or 'q' if rex prefix is present.
- 'L' unused.
+ 'L' => print 'l' or 'q' if suffix_always is true
'M' => print 'r' if intel_mnemonic is false.
'N' => print 'n' if instruction has no wait "prefix"
'O' => print 'd' or 'o' (or 'q' in Intel mode)
/* PREFIX_0F38F6 */
{
{ "wrssK", { M, Gdq }, 0 },
- { "adoxS", { VexGdq, Gdq, Edq}, 0 },
- { "adcxS", { VexGdq, Gdq, Edq}, 0 },
+ { "adoxL", { VexGdq, Gdq, Edq }, 0 },
+ { "adcxL", { VexGdq, Gdq, Edq }, 0 },
{ Bad_Opcode },
},
*ins->obufp++ = 'd';
break;
case 'L':
- abort ();
+ if (ins->intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ {
+ if (ins->rex & REX_W)
+ *ins->obufp++ = 'q';
+ else
+ *ins->obufp++ = 'l';
+ }
+ break;
case 'M':
if (ins->intel_mnemonic != cond)
*ins->obufp++ = 'r';