MIPS: start.S: set sp register directly

The current code uses two instructions to load
the stack pointer into the 'sp' register.

This results in the following assembly code:

    468:   3c088040        lui     t0,0x8040
    46c:   251d0000        addiu   sp,t0,0

The first instuction loads the stack pointer into
the 't0' register then the value of the 'sp' register
is computed by adding zero to the value of the 't0'
register. The same issue present on the 64-bit version
as well:

    56c:   3c0c8040        lui     t0,0x8040
    570:   659d0000        daddiu  sp,t0,0

Change the code to load the stack pointer directly
into the 'sp' register. The generated code is functionally
equivalent to the previous version but it is simpler.

  32-bit:
    468:   3c1d8040        lui     sp,0x8040

  64-bit:
    56c:   3c1d8040        lui     sp,0x8040

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index a4fc1ec..88e8036 100644 (file)
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -258,8 +258,7 @@ reset:
 #endif
 
        /* Set up temporary stack */
-       li      t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       la      sp, 0(t0)
+       li      sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
        la      t9, board_init_f
        jr      t9

diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index aed82e1..d3c5cea 100644 (file)
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -137,8 +137,7 @@ reset:
 #endif
 
        /* Set up temporary stack */
-       dli     t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       dla     sp, 0(t0)
+       dli     sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
        dla     t9, board_init_f
        jr      t9