drm/msm/adreno: Allow SoC specific gpu device table entries

There are cases where there are differences due to SoC integration.
Such as cache-coherency support, and (in the next patch) e-fuse to
speedbin mappings.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549767/

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 3c531da..e62bc89 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -259,6 +259,32 @@ static const struct adreno_info gpulist[] = {
                .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
                .init = a6xx_gpu_init,
        }, {
+               .machine = "qcom,sm4350",
+               .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+               .revn = 619,
+               .fw = {
+                       [ADRENO_FW_SQE] = "a630_sqe.fw",
+                       [ADRENO_FW_GMU] = "a619_gmu.bin",
+               },
+               .gmem = SZ_512K,
+               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .init = a6xx_gpu_init,
+               .zapfw = "a615_zap.mdt",
+               .hwcg = a615_hwcg,
+       }, {
+               .machine = "qcom,sm6375",
+               .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+               .revn = 619,
+               .fw = {
+                       [ADRENO_FW_SQE] = "a630_sqe.fw",
+                       [ADRENO_FW_GMU] = "a619_gmu.bin",
+               },
+               .gmem = SZ_512K,
+               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .init = a6xx_gpu_init,
+               .zapfw = "a615_zap.mdt",
+               .hwcg = a615_hwcg,
+       }, {
                .rev = ADRENO_REV(6, 1, 9, ANY_ID),
                .revn = 619,
                .fw = {
@@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
        /* identify gpu: */
        for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
                const struct adreno_info *info = &gpulist[i];
+               if (info->machine && !of_machine_is_compatible(info->machine))
+                       continue;
                if (adreno_cmp_rev(info->rev, rev))
                        return info;
        }
@@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
                config.rev.minor, config.rev.patchid);
 
        priv->is_a2xx = config.rev.core == 2;
+       priv->has_cached_coherent =
+               !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
 
        gpu = info->init(drm);
        if (IS_ERR(gpu)) {
@@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
        if (ret)
                return ret;
 
-       priv->has_cached_coherent =
-               !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
-               !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
-
        return 0;
 }
 

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 059e35d..2abc43b 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
 extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
 
 struct adreno_info {
+       const char *machine;
        struct adreno_rev rev;
        uint32_t revn;
        const char *fw[ADRENO_FW_MAX];