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clk: sunxi-ng: a83t: Fix audio PLL divider offset
author
Chen-Yu Tsai
<wens@csie.org>
Mon, 22 May 2017 06:25:48 +0000
(14:25 +0800)
committer
Maxime Ripard
<maxime.ripard@free-electrons.com>
Wed, 7 Jun 2017 13:32:16 +0000
(15:32 +0200)
The divider of the audio PLL has an offset of 1.
Fix this in the driver.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
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diff --git
a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index
a9c5cc8
..
947f9f6
100644
(file)
--- a/
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@
-80,7
+80,7
@@
static struct ccu_nm pll_audio_clk = {
.enable = BIT(31),
.lock = BIT(2),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
- .m = _SUNXI_CCU_DIV
_OFFSET(0, 6, 0
),
+ .m = _SUNXI_CCU_DIV
(0, 6
),
.common = {
.reg = SUN8I_A83T_PLL_AUDIO_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,