drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in DCN2.1

[WHY]:
Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead
to a large number causing an assert to get hit. In VBA, this value is 0
when DCC is disabled.

[HOW]:
Set value to 0 to avoid hitting the assert.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index a38baa7..5430ced 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1500,9 +1500,12 @@ static void dml_rq_dlg_get_dlg_params(
                                < (unsigned int)dml_pow(2, 13));
        }
 
-       disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
+       if (src->dcc)
+               disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
                        (unsigned int) (dst_y_per_row_vblank * (double) htotal
                                        * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
+       else
+               disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 0;
        ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
 
        disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =