clk: samsung: exynos5433: Add clock flag to support suspend-to-ram

Add the CLK_IS_CRITICAL and CLK_IGNORE_UNUSED flag
to some clocks in order to avoid the hang-out in the suspend mode.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 7985352..38235b6 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -598,7 +598,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
                        CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
                        ENABLE_ACLK_TOP, 8,
-                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
                        ENABLE_ACLK_TOP, 7,
                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
@@ -654,7 +654,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
                        ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
                        "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
-                       3, CLK_SET_RATE_PARENT, 0),
+                       3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
        GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
                        "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
                        1, CLK_SET_RATE_PARENT, 0),
@@ -3009,7 +3009,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
        GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
                        ENABLE_SCLK_AUD1, 4, 0, 0),
        GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
-                       ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
+                       ENABLE_SCLK_AUD1, 3, CLK_IS_CRITICAL, 0),
        GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
                        ENABLE_SCLK_AUD1, 2, 0, 0),
        GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",