#ifndef __ARCH_ARM_SRC_S5J_CHIP_S5J_MEMORYMAP_H
#define __ARCH_ARM_SRC_S5J_CHIP_S5J_MEMORYMAP_H
+/* S5J Physical Memory Map */
+#define S5J_IROM_PADDR 0x00000000 /* 0x00000000-0x0000FFFF iROM */
+#define S5J_IRAM_PADDR 0x02020000 /* 0x02020000-0x0215FFFF iRAM */
+#define S5J_IRAM_SHARED_PADDR 0x02300000 /* 0x02300000-0x0231FFFF iRAM shared */
+#define S5J_FLASH_PADDR 0x04000000 /* 0x04000000-0x04FFFFFF NOR flash */
+#define S5J_FLASH_MIRROR_PADDR 0x60000000 /* 0x60000000-0x60FFFFFF NOR flash (mirror of 0x04000000-0x04FFFFFF) */
+#define S5J_PERIPHERAL_PADDR 0x80000000 /* 0x80000000-0x8FFFFFFF SFR region */
+#define S5J_IRAM_MIRROR_PADDR 0xFFFF0000 /* 0xFFFF0000-0xFFFFFFFF iRAM (mirror of 0x02020000-0x0202FFFF) */
+
+/* Size of memory regions in bytes */
+#define S5J_IROM_SIZE (64 * 1024)
+#define S5J_IRAM_SIZE (1280 * 1024)
+#define S5J_IRAM_SHARED_SIZE (128 * 1024)
+#define S5J_FLASH_SIZE (16 * 1024 * 1024)
+#define S5J_FLASH_MIRROR_SIZE S5J_FLASH_SIZE
+#define S5J_PERIPHERAL_SIZE (256 * 1024 * 1024)
+#define S5J_IRAM_MIRROR_SIZE (64 * 1024)
+
#define VECTOR_BASE 0xFFFF0000
+/* S5J Internal Peripherals at 0x80000000 */
#define EFUSE_WRITER 0x80000000
#define CHIPID_BASE EFUSE_WRITER
#define MCT0_BASE 0x80010000