Builder.defineMacro("__riscv_compressed");
}
- if (HasB) {
- Builder.defineMacro("__riscv_b", "93000");
- Builder.defineMacro("__riscv_bitmanip");
- }
-
if (HasV) {
Builder.defineMacro("__riscv_v", "10000");
Builder.defineMacro("__riscv_vector");
.Case("f", HasF)
.Case("d", HasD)
.Case("c", HasC)
- .Case("experimental-b", HasB)
.Case("experimental-v", HasV)
.Case("experimental-zba", HasZba)
.Case("experimental-zbb", HasZbb)
HasD = true;
else if (Feature == "+c")
HasC = true;
- else if (Feature == "+experimental-b")
- HasB = true;
else if (Feature == "+experimental-v")
HasV = true;
else if (Feature == "+experimental-zba")
bool HasF = false;
bool HasD = false;
bool HasC = false;
- bool HasB = false;
bool HasV = false;
bool HasZba = false;
bool HasZbb = false;
// extension that the compiler currently supports.
static Optional<RISCVExtensionVersion>
isExperimentalExtension(StringRef Ext) {
- if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
- Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
- Ext == "zbr" || Ext == "zbs" || Ext == "zbt")
+ if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" ||
+ Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
+ Ext == "zbs" || Ext == "zbt")
return RISCVExtensionVersion{"0", "93"};
if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
return RISCVExtensionVersion{"0", "10"};
case 'c':
Features.push_back("+c");
break;
- case 'b':
- Features.push_back("+experimental-b");
- Features.push_back("+experimental-zba");
- Features.push_back("+experimental-zbb");
- Features.push_back("+experimental-zbc");
- Features.push_back("+experimental-zbe");
- Features.push_back("+experimental-zbf");
- Features.push_back("+experimental-zbm");
- Features.push_back("+experimental-zbp");
- Features.push_back("+experimental-zbr");
- Features.push_back("+experimental-zbs");
- Features.push_back("+experimental-zbt");
- break;
case 'v':
Features.push_back("+experimental-v");
Features.push_back("+experimental-zvlsseg");
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32ib'
-// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib -menable-experimental-extensions -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32ib'
-// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p1 -menable-experimental-extensions -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32ib0p1'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ib0p93 -menable-experimental-extensions -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-b"
-
// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-NOFLAG %s
// RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb'
// CHECK-C-EXT: __riscv_c 2000000
// CHECK-C-EXT: __riscv_compressed 1
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv64ib0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
-// CHECK-B-EXT: __riscv_b 93000
-// CHECK-B-EXT: __riscv_bitmanip 1
-// CHECK-B-EXT: __riscv_zba 93000
-// CHECK-B-EXT: __riscv_zbb 93000
-// CHECK-B-EXT: __riscv_zbc 93000
-// CHECK-B-EXT: __riscv_zbe 93000
-// CHECK-B-EXT: __riscv_zbf 93000
-// CHECK-B-EXT: __riscv_zbm 93000
-// CHECK-B-EXT: __riscv_zbp 93000
-// CHECK-B-EXT: __riscv_zbr 93000
-// CHECK-B-EXT: __riscv_zbs 93000
-// CHECK-B-EXT: __riscv_zbt 93000
-
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32izba0p93 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
clearFeatureBits(RISCV::FeatureStdExtF, "f");
clearFeatureBits(RISCV::FeatureStdExtD, "d");
clearFeatureBits(RISCV::FeatureStdExtC, "c");
- clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
setFeatureBits(RISCV::FeatureStdExtD, "d");
} else if (Arch[0] == 'c') {
setFeatureBits(RISCV::FeatureStdExtC, "c");
- } else if (Arch[0] == 'b') {
- setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
} else if (Arch[0] == 'v') {
setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
} else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
if (getFeatureBits(RISCV::FeatureStdExtC))
formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
- if (getFeatureBits(RISCV::FeatureStdExtB))
- formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtV))
formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
if (getFeatureBits(RISCV::FeatureStdExtZfh))
Arch += "_d2p0";
if (STI.hasFeature(RISCV::FeatureStdExtC))
Arch += "_c2p0";
- if (STI.hasFeature(RISCV::FeatureStdExtB))
- Arch += "_b0p93";
if (STI.hasFeature(RISCV::FeatureStdExtV))
Arch += "_v0p10";
if (STI.hasFeature(RISCV::FeatureStdExtZfh))
"'Zbb' (Base 'B' Instructions) or "
"'Zbp' (Permutation 'B' Instructions)">;
-def FeatureStdExtB
- : SubtargetFeature<"experimental-b", "HasStdExtB", "true",
- "'B' (Bit Manipulation Instructions)",
- [FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbc,
- FeatureStdExtZbe,
- FeatureStdExtZbf,
- FeatureStdExtZbm,
- FeatureStdExtZbp,
- FeatureStdExtZbr,
- FeatureStdExtZbs,
- FeatureStdExtZbt]>;
-def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
- AssemblerPredicate<(all_of FeatureStdExtB),
- "'B' (Bit Manipulation Instructions)">;
-
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">;
include "RISCVInstrInfoF.td"
include "RISCVInstrInfoD.td"
include "RISCVInstrInfoC.td"
-include "RISCVInstrInfoB.td"
+include "RISCVInstrInfoZb.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
+++ /dev/null
-//===-- RISCVInstrInfoB.td - RISC-V 'B' instructions -------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the RISC-V instructions from the standard 'B' Bitmanip
-// extension, version 0.93.
-// This version is still experimental as the 'B' extension hasn't been
-// ratified yet.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Operand and SDNode transformation definitions.
-//===----------------------------------------------------------------------===//
-
-def riscv_clzw : SDNode<"RISCVISD::CLZW", SDT_RISCVIntUnaryOpW>;
-def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDT_RISCVIntUnaryOpW>;
-def riscv_rolw : SDNode<"RISCVISD::ROLW", SDT_RISCVIntBinOpW>;
-def riscv_rorw : SDNode<"RISCVISD::RORW", SDT_RISCVIntBinOpW>;
-def riscv_fslw : SDNode<"RISCVISD::FSLW", SDT_RISCVIntShiftDOpW>;
-def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>;
-def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>;
-def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
-def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;
-def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;
-def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;
-def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;
-def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
-def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;
-def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
-def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
-def riscv_bcompress : SDNode<"RISCVISD::BCOMPRESS", SDTIntBinOp>;
-def riscv_bcompressw : SDNode<"RISCVISD::BCOMPRESSW", SDT_RISCVIntBinOpW>;
-def riscv_bdecompress : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
-def riscv_bdecompressw : SDNode<"RISCVISD::BDECOMPRESSW",SDT_RISCVIntBinOpW>;
-
-def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
- let Name = "UImmLog2XLenHalf";
- let RenderMethod = "addImmOperands";
- let DiagnosticType = "InvalidUImmLog2XLenHalf";
-}
-
-def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
- if (Subtarget->is64Bit())
- return isUInt<5>(Imm);
- return isUInt<4>(Imm);
-}]> {
- let ParserMatchClass = UImmLog2XLenHalfAsmOperand;
- let DecoderMethod = "decodeUImmOperand<5>";
- let MCOperandPredicate = [{
- int64_t Imm;
- if (!MCOp.evaluateAsConstantImm(Imm))
- return false;
- if (STI.getTargetTriple().isArch64Bit())
- return isUInt<5>(Imm);
- return isUInt<4>(Imm);
- }];
-}
-
-def BCLRXForm : SDNodeXForm<imm, [{
- // Find the lowest 0.
- return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
- SDLoc(N), N->getValueType(0));
-}]>;
-
-def BSETINVXForm : SDNodeXForm<imm, [{
- // Find the lowest 1.
- return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
- SDLoc(N), N->getValueType(0));
-}]>;
-
-// Checks if this mask has a single 0 bit and cannot be used with ANDI.
-def BCLRMask : ImmLeaf<XLenVT, [{
- if (Subtarget->is64Bit())
- return !isInt<12>(Imm) && isPowerOf2_64(~Imm);
- return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
-}], BCLRXForm>;
-
-// Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.
-def BSETINVMask : ImmLeaf<XLenVT, [{
- if (Subtarget->is64Bit())
- return !isInt<12>(Imm) && isPowerOf2_64(Imm);
- return !isInt<12>(Imm) && isPowerOf2_32(Imm);
-}], BSETINVXForm>;
-
-// Check if (or r, i) can be optimized to (BSETI (BSETI r, i0), i1),
-// in which i = (1 << i0) | (1 << i1).
-def BSETINVTwoBitsMask : PatLeaf<(imm), [{
- if (!N->hasOneUse())
- return false;
- // The immediate should not be a simm12.
- if (isInt<12>(N->getSExtValue()))
- return false;
- // The immediate must have exactly two bits set.
- return countPopulation(N->getZExtValue()) == 2;
-}]>;
-
-def TrailingZerosXForm : SDNodeXForm<imm, [{
- uint64_t I = N->getZExtValue();
- return CurDAG->getTargetConstant(countTrailingZeros(I), SDLoc(N),
- N->getValueType(0));
-}]>;
-
-def BSETINVTwoBitsMaskHigh : SDNodeXForm<imm, [{
- uint64_t I = N->getZExtValue();
- return CurDAG->getTargetConstant(63 - countLeadingZeros(I), SDLoc(N),
- N->getValueType(0));
-}]>;
-
-// Check if (or r, imm) can be optimized to (BSETI (ORI r, i0), i1),
-// in which imm = i0 | (1 << i1).
-def BSETINVORIMask : PatLeaf<(imm), [{
- if (!N->hasOneUse())
- return false;
- // The immediate should not be a simm12.
- if (isInt<12>(N->getSExtValue()))
- return false;
- // There should be only one set bit from bit 11 to the top.
- return isPowerOf2_64(N->getZExtValue() & ~0x7ff);
-}]>;
-
-def BSETINVORIMaskLow : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 0x7ff,
- SDLoc(N), N->getValueType(0));
-}]>;
-
-// Check if (and r, i) can be optimized to (BCLRI (BCLRI r, i0), i1),
-// in which i = ~((1<<i0) | (1<<i1)).
-def BCLRITwoBitsMask : PatLeaf<(imm), [{
- if (!N->hasOneUse())
- return false;
- // The immediate should not be a simm12.
- if (isInt<12>(N->getSExtValue()))
- return false;
- // The immediate must have exactly two bits clear.
- return countPopulation(N->getZExtValue()) == Subtarget->getXLen() - 2;
-}]>;
-
-def BCLRITwoBitsMaskLow : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(countTrailingZeros(~N->getZExtValue()),
- SDLoc(N), N->getValueType(0));
-}]>;
-
-def BCLRITwoBitsMaskHigh : SDNodeXForm<imm, [{
- uint64_t I = N->getSExtValue();
- if (!Subtarget->is64Bit())
- I |= 0xffffffffull << 32;
- return CurDAG->getTargetConstant(63 - countLeadingZeros(~I), SDLoc(N),
- N->getValueType(0));
-}]>;
-
-// Check if (and r, i) can be optimized to (BCLRI (ANDI r, i0), i1),
-// in which i = i0 & ~(1<<i1).
-def BCLRIANDIMask : PatLeaf<(imm), [{
- if (!N->hasOneUse())
- return false;
- // The immediate should not be a simm12.
- if (isInt<12>(N->getSExtValue()))
- return false;
- // There should be only one clear bit from bit 11 to the top.
- uint64_t I = N->getZExtValue() | 0x7ff;
- return Subtarget->is64Bit() ? isPowerOf2_64(~I) : isPowerOf2_32(~I);
-}]>;
-
-def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
- SDLoc(N), N->getValueType(0));
-}]>;
-
-def C3LeftShift : PatLeaf<(imm), [{
- uint64_t C = N->getZExtValue();
- return C > 3 && ((C % 3) == 0) && isPowerOf2_64(C / 3);
-}]>;
-
-def C5LeftShift : PatLeaf<(imm), [{
- uint64_t C = N->getZExtValue();
- return C > 5 && ((C % 5) == 0) && isPowerOf2_64(C / 5);
-}]>;
-
-def C9LeftShift : PatLeaf<(imm), [{
- uint64_t C = N->getZExtValue();
- return C > 9 && ((C % 9) == 0) && isPowerOf2_64(C / 9);
-}]>;
-
-def CSImm12MulBy4 : PatLeaf<(imm), [{
- if (!N->hasOneUse())
- return false;
- int64_t C = N->getSExtValue();
- // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
- return !isInt<13>(C) && isInt<14>(C) && (C & 3) == 0;
-}]>;
-
-def CSImm12MulBy8 : PatLeaf<(imm), [{
- if (!N->hasOneUse())
- return false;
- int64_t C = N->getSExtValue();
- // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
- return !isInt<13>(C) && isInt<15>(C) && (C & 7) == 0;
-}]>;
-
-def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
- N->getValueType(0));
-}]>;
-
-def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
- N->getValueType(0));
-}]>;
-
-//===----------------------------------------------------------------------===//
-// Instruction class templates
-//===----------------------------------------------------------------------===//
-
-// Some of these templates should be moved to RISCVInstrFormats.td once the B
-// extension has been ratified.
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3,
- RISCVOpcode opcode, string opcodestr>
- : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
- opcodestr, "$rd, $rs1"> {
- let rs2 = funct5;
-}
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBShift_ri<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
- string opcodestr>
- : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
- (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
- "$rd, $rs1, $shamt">;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBShiftW_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
- string opcodestr>
- : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
- (ins GPR:$rs1, uimm5:$shamt), opcodestr,
- "$rd, $rs1, $shamt">;
-
-// Using RVInstIShiftW since it allocates 5 bits instead of 6 to shamt.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBShfl_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
- string opcodestr>
- : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
- (ins GPR:$rs1, shfl_uimm:$shamt), opcodestr,
- "$rd, $rs1, $shamt">;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBTernaryR<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
- string opcodestr, string argstr>
- : RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),
- (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr>;
-
-// Currently used by FSRI only
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBTernaryImm6<bits<3> funct3, RISCVOpcode opcode,
- string opcodestr, string argstr>
- : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt),
- opcodestr, argstr, [], InstFormatR4> {
- bits<5> rs3;
- bits<6> shamt;
- bits<5> rs1;
- bits<5> rd;
-
- let Inst{31-27} = rs3;
- let Inst{26} = 1;
- let Inst{25-20} = shamt;
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Opcode = opcode.Value;
-}
-
-// Currently used by FSRIW only
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
- string opcodestr, string argstr>
- : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$shamt),
- opcodestr, argstr, [], InstFormatR4> {
- bits<5> rs3;
- bits<5> shamt;
- bits<5> rs1;
- bits<5> rd;
-
- let Inst{31-27} = rs3;
- let Inst{26-25} = funct2;
- let Inst{24-20} = shamt;
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Opcode = opcode.Value;
-}
-
-//===----------------------------------------------------------------------===//
-// Instructions
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasStdExtZbbOrZbp] in {
-def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def ORN : ALU_rr<0b0100000, 0b110, "orn">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-} // Predicates = [HasStdExtZbbOrZbp]
-
-let Predicates = [HasStdExtZba] in {
-def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
- Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
-def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">,
- Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
-def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
- Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
-} // Predicates = [HasStdExtZba]
-
-let Predicates = [HasStdExtZbbOrZbp] in {
-def ROL : ALU_rr<0b0110000, 0b001, "rol">,
- Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
-def ROR : ALU_rr<0b0110000, 0b101, "ror">,
- Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
-} // Predicates = [HasStdExtZbbOrZbp]
-
-let Predicates = [HasStdExtZbs] in {
-def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, Sched<[]>;
-def BSET : ALU_rr<0b0010100, 0b001, "bset">, Sched<[]>;
-def BINV : ALU_rr<0b0110100, 0b001, "binv">, Sched<[]>;
-def BEXT : ALU_rr<0b0100100, 0b101, "bext">, Sched<[]>;
-} // Predicates = [HasStdExtZbs]
-
-let Predicates = [HasStdExtZbp] in {
-def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
-def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbp] in {
-def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>;
-def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
-def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbbOrZbp] in
-def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
- Sched<[WriteRotateImm, ReadRotateImm]>;
-
-let Predicates = [HasStdExtZbs] in {
-def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">, Sched<[]>;
-def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">, Sched<[]>;
-def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">, Sched<[]>;
-def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, Sched<[]>;
-} // Predicates = [HasStdExtZbs]
-
-let Predicates = [HasStdExtZbp] in {
-def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
-def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbt] in {
-def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
- Sched<[]>;
-def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
- Sched<[]>;
-def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
- Sched<[]>;
-def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
- Sched<[]>;
-def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
- "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
-} // Predicates = [HasStdExtZbt]
-
-let Predicates = [HasStdExtZbb] in {
-def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0010011>, "clz">,
- Sched<[WriteCLZ, ReadCLZ]>;
-def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0010011>, "ctz">,
- Sched<[WriteCTZ, ReadCTZ]>;
-def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "cpop">,
- Sched<[WriteCPOP, ReadCPOP]>;
-} // Predicates = [HasStdExtZbb]
-
-let Predicates = [HasStdExtZbm, IsRV64] in
-def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, RISCVOpcode<0b0010011>,
- "bmatflip">, Sched<[]>;
-
-let Predicates = [HasStdExtZbb] in {
-def SEXTB : RVBUnary<0b0110000, 0b00100, 0b001, RISCVOpcode<0b0010011>,
- "sext.b">, Sched<[WriteIALU, ReadIALU]>;
-def SEXTH : RVBUnary<0b0110000, 0b00101, 0b001, RISCVOpcode<0b0010011>,
- "sext.h">, Sched<[WriteIALU, ReadIALU]>;
-} // Predicates = [HasStdExtZbb]
-
-let Predicates = [HasStdExtZbr] in {
-def CRC32B : RVBUnary<0b0110000, 0b10000, 0b001, RISCVOpcode<0b0010011>,
- "crc32.b">, Sched<[]>;
-def CRC32H : RVBUnary<0b0110000, 0b10001, 0b001, RISCVOpcode<0b0010011>,
- "crc32.h">, Sched<[]>;
-def CRC32W : RVBUnary<0b0110000, 0b10010, 0b001, RISCVOpcode<0b0010011>,
- "crc32.w">, Sched<[]>;
-} // Predicates = [HasStdExtZbr]
-
-let Predicates = [HasStdExtZbr, IsRV64] in
-def CRC32D : RVBUnary<0b0110000, 0b10011, 0b001, RISCVOpcode<0b0010011>,
- "crc32.d">, Sched<[]>;
-
-let Predicates = [HasStdExtZbr] in {
-def CRC32CB : RVBUnary<0b0110000, 0b11000, 0b001, RISCVOpcode<0b0010011>,
- "crc32c.b">, Sched<[]>;
-def CRC32CH : RVBUnary<0b0110000, 0b11001, 0b001, RISCVOpcode<0b0010011>,
- "crc32c.h">, Sched<[]>;
-def CRC32CW : RVBUnary<0b0110000, 0b11010, 0b001, RISCVOpcode<0b0010011>,
- "crc32c.w">, Sched<[]>;
-} // Predicates = [HasStdExtZbr]
-
-let Predicates = [HasStdExtZbr, IsRV64] in
-def CRC32CD : RVBUnary<0b0110000, 0b11011, 0b001, RISCVOpcode<0b0010011>,
- "crc32c.d">, Sched<[]>;
-
-let Predicates = [HasStdExtZbc] in {
-def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>;
-def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>;
-def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>;
-} // Predicates = [HasStdExtZbc]
-
-let Predicates = [HasStdExtZbb] in {
-def MIN : ALU_rr<0b0000101, 0b100, "min">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def MINU : ALU_rr<0b0000101, 0b101, "minu">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def MAX : ALU_rr<0b0000101, 0b110, "max">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def MAXU : ALU_rr<0b0000101, 0b111, "maxu">,
- Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-} // Predicates = [HasStdExtZbb]
-
-let Predicates = [HasStdExtZbp] in {
-def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
-def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbe] in {
-// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
-// bext in the 0.93 spec.
-def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
-def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
-} // Predicates = [HasStdExtZbe]
-
-let Predicates = [HasStdExtZbp] in {
-def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
-def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
-def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbm, IsRV64] in {
-def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
-def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
-} // Predicates = [HasStdExtZbm, IsRV64]
-
-let Predicates = [HasStdExtZbf] in
-def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
-
-let Predicates = [HasStdExtZbp] in {
-def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
-def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZba, IsRV64] in {
-def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
- Sched<[WriteShiftImm32, ReadShiftImm32]>;
-def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">,
- Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
-def SH1ADDUW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">,
- Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
-def SH2ADDUW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
- Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
-def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
- Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
-} // Predicates = [HasStdExtZbb, IsRV64]
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
- Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
-def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
- Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
-
-let Predicates = [HasStdExtZbs, IsRV64] in {
-// NOTE: These instructions have been removed from the 0.94 spec. As a result
-// we have no isel patterns for them.
-def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>;
-def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>;
-def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>;
-def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>;
-} // Predicates = [HasStdExtZbs, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
-def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
-def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
- Sched<[WriteRotateImm32, ReadRotateImm32]>;
-
-let Predicates = [HasStdExtZbs, IsRV64] in {
-// NOTE: These instructions have been removed from the 0.94 spec. As a result
-// we have no isel patterns for them.
-def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">,
- Sched<[]>;
-def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">,
- Sched<[]>;
-def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">,
- Sched<[]>;
-} // Predicates = [HasStdExtZbs, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
-def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbt, IsRV64] in {
-def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32,
- "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
-def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
- "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
-def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
- "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
-} // Predicates = [HasStdExtZbt, IsRV64]
-
-let Predicates = [HasStdExtZbb, IsRV64] in {
-def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
- "clzw">, Sched<[WriteCLZ32, ReadCLZ32]>;
-def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>,
- "ctzw">, Sched<[WriteCTZ32, ReadCTZ32]>;
-def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
- "cpopw">, Sched<[WriteCPOP32, ReadCPOP32]>;
-} // Predicates = [HasStdExtZbb, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
-def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbe, IsRV64] in {
-// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
-// bextw in the 0.93 spec.
-def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
-def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
-} // Predicates = [HasStdExtZbe, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
-def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbf, IsRV64] in
-def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def ZEXTH_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
- (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
- Sched<[WriteIALU, ReadIALU]> {
- let rs2 = 0b00000;
-}
-} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
- (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
- Sched<[WriteIALU, ReadIALU]> {
- let rs2 = 0b00000;
-}
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
-
-// We treat rev8 and orc.b as standalone instructions even though they use a
-// portion of the encodings for grevi and gorci. This allows us to support only
-// those encodings when only Zbb is enabled. We do this even when grevi and
-// gorci are available with Zbp. Trying to use 'HasStdExtZbb, NotHasStdExtZbp'
-// causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
-// or gorci. Since Zbb is closer to being finalized than Zbp this will be
-// misleading to users.
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
- "rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
- let imm12 = { 0b01101, 0b0011000 };
-}
-} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
- "rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
- let imm12 = { 0b01101, 0b0111000 };
-}
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
-
-let Predicates = [HasStdExtZbbOrZbp] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
- "orc.b", "$rd, $rs1">, Sched<[WriteORCB, ReadORCB]> {
- let imm12 = { 0b00101, 0b0000111 };
-}
-} // Predicates = [HasStdExtZbbOrZbp]
-
-//===----------------------------------------------------------------------===//
-// Pseudo Instructions
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasStdExtZba, IsRV64] in {
-// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been
-// changed to add.uw in a draft after 0.94.
-def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
-}
-
-let Predicates = [HasStdExtZbp] in {
-def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>;
-def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
-def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
-def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
-def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
-def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
-def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
-def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
-def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
-def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
-
-def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
-def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
-def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>;
-def : InstAlias<"unzip2.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0010)>;
-def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>;
-def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>;
-def : InstAlias<"zip4.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0100)>;
-def : InstAlias<"unzip4.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0100)>;
-def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>;
-def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>;
-def : InstAlias<"zip.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0111)>;
-def : InstAlias<"unzip.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0111)>;
-
-def : InstAlias<"orc.p $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00001)>;
-def : InstAlias<"orc2.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00010)>;
-def : InstAlias<"orc.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00011)>;
-def : InstAlias<"orc4.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00100)>;
-def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>;
-// orc.b is considered an instruction rather than an alias.
-def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>;
-def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>;
-def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>;
-def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbp, IsRV32] in {
-def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
-// rev8 is considered an instruction rather than an alias.
-def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
-def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
-def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
-
-def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>;
-def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>;
-def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
-def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
-def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
-def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
-def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
-def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
-
-def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
-def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
-def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>;
-def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>;
-def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>;
-} // Predicates = [HasStdExtZbp, IsRV32]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>;
-def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>;
-def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>;
-def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>;
-def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>;
-def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>;
-def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>;
-// rev8 is considered an instruction rather than an alias.
-def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111100)>;
-def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111110)>;
-def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>;
-
-def : InstAlias<"zip8.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01000)>;
-def : InstAlias<"unzip8.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01000)>;
-def : InstAlias<"zip4.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01100)>;
-def : InstAlias<"unzip4.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01100)>;
-def : InstAlias<"zip2.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01110)>;
-def : InstAlias<"unzip2.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01110)>;
-def : InstAlias<"zip.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01111)>;
-def : InstAlias<"unzip.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01111)>;
-def : InstAlias<"zip16 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b10000)>;
-def : InstAlias<"unzip16 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b10000)>;
-def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11000)>;
-def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11000)>;
-def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11100)>;
-def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11100)>;
-def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11110)>;
-def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11110)>;
-def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11111)>;
-def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11111)>;
-
-def : InstAlias<"orc16.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b010000)>;
-def : InstAlias<"orc8.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011000)>;
-def : InstAlias<"orc4.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011100)>;
-def : InstAlias<"orc2.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011110)>;
-def : InstAlias<"orc.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011111)>;
-def : InstAlias<"orc32 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b100000)>;
-def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b110000)>;
-def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111000)>;
-def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111100)>;
-def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111110)>;
-def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111111)>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbbOrZbp] in {
-def : InstAlias<"ror $rd, $rs1, $shamt",
- (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-} // Predicates = [HasStdExtZbbOrZbp]
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-def : InstAlias<"rorw $rd, $rs1, $shamt",
- (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
-
-let Predicates = [HasStdExtZbp] in {
-def : InstAlias<"grev $rd, $rs1, $shamt",
- (GREVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-def : InstAlias<"gorc $rd, $rs1, $shamt",
- (GORCI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-def : InstAlias<"shfl $rd, $rs1, $shamt",
- (SHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
-def : InstAlias<"unshfl $rd, $rs1, $shamt",
- (UNSHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : InstAlias<"grevw $rd, $rs1, $shamt",
- (GREVIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
-def : InstAlias<"gorcw $rd, $rs1, $shamt",
- (GORCIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbs] in {
-def : InstAlias<"bset $rd, $rs1, $shamt",
- (BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-def : InstAlias<"bclr $rd, $rs1, $shamt",
- (BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-def : InstAlias<"binv $rd, $rs1, $shamt",
- (BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-def : InstAlias<"bext $rd, $rs1, $shamt",
- (BEXTI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
-} // Predicates = [HasStdExtZbs]
-
-//===----------------------------------------------------------------------===//
-// Codegen patterns
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasStdExtZbbOrZbp] in {
-def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>;
-def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
-} // Predicates = [HasStdExtZbbOrZbp]
-
-let Predicates = [HasStdExtZbbOrZbp] in {
-def : PatGprGpr<rotl, ROL>;
-def : PatGprGpr<rotr, ROR>;
-} // Predicates = [HasStdExtZbbOrZbp]
-
-let Predicates = [HasStdExtZbs] in {
-def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
- (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
- (BSET GPR:$rs1, GPR:$rs2)>;
-def : Pat<(xor (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
- (BINV GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (shiftop<srl> GPR:$rs1, GPR:$rs2), 1),
- (BEXT GPR:$rs1, GPR:$rs2)>;
-
-def : Pat<(shiftop<shl> 1, GPR:$rs2),
- (BSET X0, GPR:$rs2)>;
-
-def : Pat<(and GPR:$rs1, BCLRMask:$mask),
- (BCLRI GPR:$rs1, BCLRMask:$mask)>;
-def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
- (BSETI GPR:$rs1, BSETINVMask:$mask)>;
-def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
- (BINVI GPR:$rs1, BSETINVMask:$mask)>;
-
-def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
- (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
-
-def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i),
- (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
- (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
-def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
- (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
- (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
-def : Pat<(or GPR:$r, BSETINVORIMask:$i),
- (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
- (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
-def : Pat<(xor GPR:$r, BSETINVORIMask:$i),
- (BINVI (XORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
- (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
-def : Pat<(and GPR:$r, BCLRITwoBitsMask:$i),
- (BCLRI (BCLRI GPR:$r, (BCLRITwoBitsMaskLow BCLRITwoBitsMask:$i)),
- (BCLRITwoBitsMaskHigh BCLRITwoBitsMask:$i))>;
-def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
- (BCLRI (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i)),
- (BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>;
-}
-
-// There's no encoding for roli in the the 'B' extension as it can be
-// implemented with rori by negating the immediate.
-let Predicates = [HasStdExtZbbOrZbp] in {
-def : PatGprImm<rotr, RORI, uimmlog2xlen>;
-def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
- (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
-
-// We treat orc.b as a separate instruction, so match it directly. We also
-// lower the Zbb orc.b intrinsic to this.
-def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
-}
-
-let Predicates = [HasStdExtZbp] in {
-def : PatGprGpr<riscv_grev, GREV>;
-def : PatGprGpr<riscv_gorc, GORC>;
-def : PatGprGpr<riscv_shfl, SHFL>;
-def : PatGprGpr<riscv_unshfl, UNSHFL>;
-def : PatGprGpr<int_riscv_xperm_n, XPERMN>;
-def : PatGprGpr<int_riscv_xperm_b, XPERMB>;
-def : PatGprGpr<int_riscv_xperm_h, XPERMH>;
-def : PatGprGpr<int_riscv_xperm_w, XPERMW>;
-def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
-def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
-def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
-def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
-} // Predicates = [HasStdExtZbp]
-
-let Predicates = [HasStdExtZbp, IsRV32] in {
-def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
-def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
-
-// We treat rev8 as a separate instruction, so match it directly.
-def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
-} // Predicates = [HasStdExtZbp, IsRV32]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-// We treat rev8 as a separate instruction, so match it directly.
-def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbt] in {
-def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
- (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-
-def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
- (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
- (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
-def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
- (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
- (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
- (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-} // Predicates = [HasStdExtZbt]
-
-// fshl and fshr concatenate their operands in the same order. fsr and fsl
-// instruction use different orders. fshl will return its first operand for
-// shift of zero, fshr will return its second operand. fsl and fsr both return
-// $rs1 so the patterns need to have different operand orders.
-let Predicates = [HasStdExtZbt] in {
-def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
- (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(riscv_fsr GPR:$rs3, GPR:$rs1, GPR:$rs2),
- (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-
-def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
- (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
-// We can use FSRI for fshl by immediate if we subtract the immediate from
-// XLen and swap the operands.
-def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
- (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
-} // Predicates = [HasStdExtZbt]
-
-let Predicates = [HasStdExtZbb] in {
-def : PatGpr<ctlz, CLZ>;
-def : PatGpr<cttz, CTZ>;
-def : PatGpr<ctpop, CPOP>;
-} // Predicates = [HasStdExtZbb]
-
-let Predicates = [HasStdExtZbb] in {
-def : Pat<(sext_inreg GPR:$rs1, i8), (SEXTB GPR:$rs1)>;
-def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>;
-}
-
-let Predicates = [HasStdExtZbb] in {
-def : PatGprGpr<smin, MIN>;
-def : PatGprGpr<smax, MAX>;
-def : PatGprGpr<umin, MINU>;
-def : PatGprGpr<umax, MAXU>;
-} // Predicates = [HasStdExtZbb]
-
-let Predicates = [HasStdExtZbb, IsRV32] in {
-def : Pat<(i32 (bswap GPR:$rs1)), (REV8_RV32 GPR:$rs1)>;
-} // Predicates = [HasStdExtZbb, IsRV32]
-
-let Predicates = [HasStdExtZbb, IsRV64] in {
-def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>;
-} // Predicates = [HasStdExtZbb, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV32] in {
-def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))),
- (PACK GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))),
- (PACKU GPR:$rs1, GPR:$rs2)>;
-
-}
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
- (PACK GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))),
- (PACKU GPR:$rs1, GPR:$rs2)>;
-}
-let Predicates = [HasStdExtZbp] in
-def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
- (and GPR:$rs1, 0x00FF)),
- (PACKH GPR:$rs1, GPR:$rs2)>;
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
-def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV32 GPR:$rs)>;
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
-def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV64 GPR:$rs)>;
-
-// Pattern to exclude simm12 immediates from matching.
-def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
- auto *C = dyn_cast<ConstantSDNode>(N);
- return !C || !isInt<12>(C->getSExtValue());
-}]>;
-
-let Predicates = [HasStdExtZba] in {
-def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2),
- (SH1ADD GPR:$rs1, GPR:$rs2)>;
-def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), non_imm12:$rs2),
- (SH2ADD GPR:$rs1, GPR:$rs2)>;
-def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), non_imm12:$rs2),
- (SH3ADD GPR:$rs1, GPR:$rs2)>;
-
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
- (SH1ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
- (SH1ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2),
- (SH1ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2),
- (SH2ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2),
- (SH2ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
- (SH2ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
- (SH3ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
- (SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
- (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
-
-def : Pat<(add GPR:$r, CSImm12MulBy4:$i),
- (SH2ADD (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)),
- GPR:$r)>;
-def : Pat<(add GPR:$r, CSImm12MulBy8:$i),
- (SH3ADD (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)),
- GPR:$r)>;
-
-def : Pat<(mul GPR:$r, C3LeftShift:$i),
- (SLLI (SH1ADD GPR:$r, GPR:$r),
- (TrailingZerosXForm C3LeftShift:$i))>;
-def : Pat<(mul GPR:$r, C5LeftShift:$i),
- (SLLI (SH2ADD GPR:$r, GPR:$r),
- (TrailingZerosXForm C5LeftShift:$i))>;
-def : Pat<(mul GPR:$r, C9LeftShift:$i),
- (SLLI (SH3ADD GPR:$r, GPR:$r),
- (TrailingZerosXForm C9LeftShift:$i))>;
-
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 11)),
- (SH1ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 19)),
- (SH1ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 13)),
- (SH2ADD (SH1ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 21)),
- (SH2ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 37)),
- (SH2ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 25)),
- (SH3ADD (SH1ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 41)),
- (SH3ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 73)),
- (SH3ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 27)),
- (SH1ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 45)),
- (SH2ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
- (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-} // Predicates = [HasStdExtZba]
-
-let Predicates = [HasStdExtZba, IsRV64] in {
-def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
- (SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)),
- (ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, X0)>;
-
-def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), non_imm12:$rs2)),
- (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 2)), non_imm12:$rs2)),
- (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 3)), non_imm12:$rs2)),
- (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
-
-def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 1)), 0x1FFFFFFFF), non_imm12:$rs2)),
- (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 2)), 0x3FFFFFFFF), non_imm12:$rs2)),
- (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2)),
- (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
-} // Predicates = [HasStdExtZba, IsRV64]
-
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-def : PatGprGpr<riscv_rolw, ROLW>;
-def : PatGprGpr<riscv_rorw, RORW>;
-def : PatGprImm<riscv_rorw, RORIW, uimm5>;
-def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
- (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
-def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
-def : PatGprGpr<riscv_grevw, GREVW>;
-def : PatGprGpr<riscv_gorcw, GORCW>;
-def : PatGprGpr<riscv_shflw, SHFLW>;
-def : PatGprGpr<riscv_unshflw, UNSHFLW>;
-def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
-def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbt, IsRV64] in {
-def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
- (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),
- (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
- (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
-def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
- (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
-} // Predicates = [HasStdExtZbt, IsRV64]
-
-let Predicates = [HasStdExtZbb, IsRV64] in {
-def : PatGpr<riscv_clzw, CLZW>;
-def : PatGpr<riscv_ctzw, CTZW>;
-def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
-} // Predicates = [HasStdExtZbb, IsRV64]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
- (and GPR:$rs1, 0x000000000000FFFF)),
- i32)),
- (PACKW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
- (and GPR:$rs1, 0x000000000000FFFF))),
- (PACKW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
- (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
- (PACKUW GPR:$rs1, GPR:$rs2)>;
-} // Predicates = [HasStdExtZbp, IsRV64]
-
-let Predicates = [HasStdExtZbc] in {
-def : PatGprGpr<int_riscv_clmul, CLMUL>;
-def : PatGprGpr<int_riscv_clmulh, CLMULH>;
-def : PatGprGpr<int_riscv_clmulr, CLMULR>;
-} // Predicates = [HasStdExtZbc]
-
-let Predicates = [HasStdExtZbe] in {
-def : PatGprGpr<riscv_bcompress, BCOMPRESS>;
-def : PatGprGpr<riscv_bdecompress, BDECOMPRESS>;
-} // Predicates = [HasStdExtZbe]
-
-let Predicates = [HasStdExtZbe, IsRV64] in {
-def : PatGprGpr<riscv_bcompressw, BCOMPRESSW>;
-def : PatGprGpr<riscv_bdecompressw, BDECOMPRESSW>;
-} // Predicates = [HasStdExtZbe, IsRV64]
-
-let Predicates = [HasStdExtZbr] in {
-def : PatGpr<int_riscv_crc32_b, CRC32B>;
-def : PatGpr<int_riscv_crc32_h, CRC32H>;
-def : PatGpr<int_riscv_crc32_w, CRC32W>;
-def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
-def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
-def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
-} // Predicates = [HasStdExtZbr]
-
-let Predicates = [HasStdExtZbr, IsRV64] in {
-def : PatGpr<int_riscv_crc32_d, CRC32D>;
-def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
-} // Predicates = [HasStdExtZbr, IsRV64]
--- /dev/null
+//===-- RISCVInstrInfoZb.td - RISC-V Bitmanip instructions -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard Bitmanip
+// extensions, version 0.93.
+// This version is still experimental as the Bitmanip extensions haven't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def riscv_clzw : SDNode<"RISCVISD::CLZW", SDT_RISCVIntUnaryOpW>;
+def riscv_ctzw : SDNode<"RISCVISD::CTZW", SDT_RISCVIntUnaryOpW>;
+def riscv_rolw : SDNode<"RISCVISD::ROLW", SDT_RISCVIntBinOpW>;
+def riscv_rorw : SDNode<"RISCVISD::RORW", SDT_RISCVIntBinOpW>;
+def riscv_fslw : SDNode<"RISCVISD::FSLW", SDT_RISCVIntShiftDOpW>;
+def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>;
+def riscv_fsl : SDNode<"RISCVISD::FSL", SDTIntShiftDOp>;
+def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
+def riscv_grev : SDNode<"RISCVISD::GREV", SDTIntBinOp>;
+def riscv_grevw : SDNode<"RISCVISD::GREVW", SDT_RISCVIntBinOpW>;
+def riscv_gorc : SDNode<"RISCVISD::GORC", SDTIntBinOp>;
+def riscv_gorcw : SDNode<"RISCVISD::GORCW", SDT_RISCVIntBinOpW>;
+def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
+def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;
+def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
+def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_bcompress : SDNode<"RISCVISD::BCOMPRESS", SDTIntBinOp>;
+def riscv_bcompressw : SDNode<"RISCVISD::BCOMPRESSW", SDT_RISCVIntBinOpW>;
+def riscv_bdecompress : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
+def riscv_bdecompressw : SDNode<"RISCVISD::BDECOMPRESSW",SDT_RISCVIntBinOpW>;
+
+def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
+ let Name = "UImmLog2XLenHalf";
+ let RenderMethod = "addImmOperands";
+ let DiagnosticType = "InvalidUImmLog2XLenHalf";
+}
+
+def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
+ if (Subtarget->is64Bit())
+ return isUInt<5>(Imm);
+ return isUInt<4>(Imm);
+}]> {
+ let ParserMatchClass = UImmLog2XLenHalfAsmOperand;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ if (STI.getTargetTriple().isArch64Bit())
+ return isUInt<5>(Imm);
+ return isUInt<4>(Imm);
+ }];
+}
+
+def BCLRXForm : SDNodeXForm<imm, [{
+ // Find the lowest 0.
+ return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
+ SDLoc(N), N->getValueType(0));
+}]>;
+
+def BSETINVXForm : SDNodeXForm<imm, [{
+ // Find the lowest 1.
+ return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
+ SDLoc(N), N->getValueType(0));
+}]>;
+
+// Checks if this mask has a single 0 bit and cannot be used with ANDI.
+def BCLRMask : ImmLeaf<XLenVT, [{
+ if (Subtarget->is64Bit())
+ return !isInt<12>(Imm) && isPowerOf2_64(~Imm);
+ return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
+}], BCLRXForm>;
+
+// Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.
+def BSETINVMask : ImmLeaf<XLenVT, [{
+ if (Subtarget->is64Bit())
+ return !isInt<12>(Imm) && isPowerOf2_64(Imm);
+ return !isInt<12>(Imm) && isPowerOf2_32(Imm);
+}], BSETINVXForm>;
+
+// Check if (or r, i) can be optimized to (BSETI (BSETI r, i0), i1),
+// in which i = (1 << i0) | (1 << i1).
+def BSETINVTwoBitsMask : PatLeaf<(imm), [{
+ if (!N->hasOneUse())
+ return false;
+ // The immediate should not be a simm12.
+ if (isInt<12>(N->getSExtValue()))
+ return false;
+ // The immediate must have exactly two bits set.
+ return countPopulation(N->getZExtValue()) == 2;
+}]>;
+
+def TrailingZerosXForm : SDNodeXForm<imm, [{
+ uint64_t I = N->getZExtValue();
+ return CurDAG->getTargetConstant(countTrailingZeros(I), SDLoc(N),
+ N->getValueType(0));
+}]>;
+
+def BSETINVTwoBitsMaskHigh : SDNodeXForm<imm, [{
+ uint64_t I = N->getZExtValue();
+ return CurDAG->getTargetConstant(63 - countLeadingZeros(I), SDLoc(N),
+ N->getValueType(0));
+}]>;
+
+// Check if (or r, imm) can be optimized to (BSETI (ORI r, i0), i1),
+// in which imm = i0 | (1 << i1).
+def BSETINVORIMask : PatLeaf<(imm), [{
+ if (!N->hasOneUse())
+ return false;
+ // The immediate should not be a simm12.
+ if (isInt<12>(N->getSExtValue()))
+ return false;
+ // There should be only one set bit from bit 11 to the top.
+ return isPowerOf2_64(N->getZExtValue() & ~0x7ff);
+}]>;
+
+def BSETINVORIMaskLow : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() & 0x7ff,
+ SDLoc(N), N->getValueType(0));
+}]>;
+
+// Check if (and r, i) can be optimized to (BCLRI (BCLRI r, i0), i1),
+// in which i = ~((1<<i0) | (1<<i1)).
+def BCLRITwoBitsMask : PatLeaf<(imm), [{
+ if (!N->hasOneUse())
+ return false;
+ // The immediate should not be a simm12.
+ if (isInt<12>(N->getSExtValue()))
+ return false;
+ // The immediate must have exactly two bits clear.
+ return countPopulation(N->getZExtValue()) == Subtarget->getXLen() - 2;
+}]>;
+
+def BCLRITwoBitsMaskLow : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(countTrailingZeros(~N->getZExtValue()),
+ SDLoc(N), N->getValueType(0));
+}]>;
+
+def BCLRITwoBitsMaskHigh : SDNodeXForm<imm, [{
+ uint64_t I = N->getSExtValue();
+ if (!Subtarget->is64Bit())
+ I |= 0xffffffffull << 32;
+ return CurDAG->getTargetConstant(63 - countLeadingZeros(~I), SDLoc(N),
+ N->getValueType(0));
+}]>;
+
+// Check if (and r, i) can be optimized to (BCLRI (ANDI r, i0), i1),
+// in which i = i0 & ~(1<<i1).
+def BCLRIANDIMask : PatLeaf<(imm), [{
+ if (!N->hasOneUse())
+ return false;
+ // The immediate should not be a simm12.
+ if (isInt<12>(N->getSExtValue()))
+ return false;
+ // There should be only one clear bit from bit 11 to the top.
+ uint64_t I = N->getZExtValue() | 0x7ff;
+ return Subtarget->is64Bit() ? isPowerOf2_64(~I) : isPowerOf2_32(~I);
+}]>;
+
+def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
+ SDLoc(N), N->getValueType(0));
+}]>;
+
+def C3LeftShift : PatLeaf<(imm), [{
+ uint64_t C = N->getZExtValue();
+ return C > 3 && ((C % 3) == 0) && isPowerOf2_64(C / 3);
+}]>;
+
+def C5LeftShift : PatLeaf<(imm), [{
+ uint64_t C = N->getZExtValue();
+ return C > 5 && ((C % 5) == 0) && isPowerOf2_64(C / 5);
+}]>;
+
+def C9LeftShift : PatLeaf<(imm), [{
+ uint64_t C = N->getZExtValue();
+ return C > 9 && ((C % 9) == 0) && isPowerOf2_64(C / 9);
+}]>;
+
+def CSImm12MulBy4 : PatLeaf<(imm), [{
+ if (!N->hasOneUse())
+ return false;
+ int64_t C = N->getSExtValue();
+ // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
+ return !isInt<13>(C) && isInt<14>(C) && (C & 3) == 0;
+}]>;
+
+def CSImm12MulBy8 : PatLeaf<(imm), [{
+ if (!N->hasOneUse())
+ return false;
+ int64_t C = N->getSExtValue();
+ // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
+ return !isInt<13>(C) && isInt<15>(C) && (C & 7) == 0;
+}]>;
+
+def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
+ N->getValueType(0));
+}]>;
+
+def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
+ N->getValueType(0));
+}]>;
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+// Some of these templates should be moved to RISCVInstrFormats.td once the B
+// extension has been ratified.
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3,
+ RISCVOpcode opcode, string opcodestr>
+ : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = funct5;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBShift_ri<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr>
+ : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
+ (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
+ "$rd, $rs1, $shamt">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBShiftW_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr>
+ : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
+ (ins GPR:$rs1, uimm5:$shamt), opcodestr,
+ "$rd, $rs1, $shamt">;
+
+// Using RVInstIShiftW since it allocates 5 bits instead of 6 to shamt.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBShfl_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr>
+ : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
+ (ins GPR:$rs1, shfl_uimm:$shamt), opcodestr,
+ "$rd, $rs1, $shamt">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBTernaryR<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr, string argstr>
+ : RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr>;
+
+// Currently used by FSRI only
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBTernaryImm6<bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr, string argstr>
+ : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt),
+ opcodestr, argstr, [], InstFormatR4> {
+ bits<5> rs3;
+ bits<6> shamt;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-27} = rs3;
+ let Inst{26} = 1;
+ let Inst{25-20} = shamt;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Opcode = opcode.Value;
+}
+
+// Currently used by FSRIW only
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr, string argstr>
+ : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$shamt),
+ opcodestr, argstr, [], InstFormatR4> {
+ bits<5> rs3;
+ bits<5> shamt;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = funct2;
+ let Inst{24-20} = shamt;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Opcode = opcode.Value;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def ORN : ALU_rr<0b0100000, 0b110, "orn">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+} // Predicates = [HasStdExtZbbOrZbp]
+
+let Predicates = [HasStdExtZba] in {
+def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
+ Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
+def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">,
+ Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
+def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
+ Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
+} // Predicates = [HasStdExtZba]
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+def ROL : ALU_rr<0b0110000, 0b001, "rol">,
+ Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
+def ROR : ALU_rr<0b0110000, 0b101, "ror">,
+ Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
+} // Predicates = [HasStdExtZbbOrZbp]
+
+let Predicates = [HasStdExtZbs] in {
+def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, Sched<[]>;
+def BSET : ALU_rr<0b0010100, 0b001, "bset">, Sched<[]>;
+def BINV : ALU_rr<0b0110100, 0b001, "binv">, Sched<[]>;
+def BEXT : ALU_rr<0b0100100, 0b101, "bext">, Sched<[]>;
+} // Predicates = [HasStdExtZbs]
+
+let Predicates = [HasStdExtZbp] in {
+def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
+def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbp] in {
+def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>;
+def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
+def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbbOrZbp] in
+def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
+ Sched<[WriteRotateImm, ReadRotateImm]>;
+
+let Predicates = [HasStdExtZbs] in {
+def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">, Sched<[]>;
+def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">, Sched<[]>;
+def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">, Sched<[]>;
+def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, Sched<[]>;
+} // Predicates = [HasStdExtZbs]
+
+let Predicates = [HasStdExtZbp] in {
+def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
+def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbt] in {
+def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
+ Sched<[]>;
+def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
+ Sched<[]>;
+def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
+ "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
+} // Predicates = [HasStdExtZbt]
+
+let Predicates = [HasStdExtZbb] in {
+def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0010011>, "clz">,
+ Sched<[WriteCLZ, ReadCLZ]>;
+def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0010011>, "ctz">,
+ Sched<[WriteCTZ, ReadCTZ]>;
+def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "cpop">,
+ Sched<[WriteCPOP, ReadCPOP]>;
+} // Predicates = [HasStdExtZbb]
+
+let Predicates = [HasStdExtZbm, IsRV64] in
+def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, RISCVOpcode<0b0010011>,
+ "bmatflip">, Sched<[]>;
+
+let Predicates = [HasStdExtZbb] in {
+def SEXTB : RVBUnary<0b0110000, 0b00100, 0b001, RISCVOpcode<0b0010011>,
+ "sext.b">, Sched<[WriteIALU, ReadIALU]>;
+def SEXTH : RVBUnary<0b0110000, 0b00101, 0b001, RISCVOpcode<0b0010011>,
+ "sext.h">, Sched<[WriteIALU, ReadIALU]>;
+} // Predicates = [HasStdExtZbb]
+
+let Predicates = [HasStdExtZbr] in {
+def CRC32B : RVBUnary<0b0110000, 0b10000, 0b001, RISCVOpcode<0b0010011>,
+ "crc32.b">, Sched<[]>;
+def CRC32H : RVBUnary<0b0110000, 0b10001, 0b001, RISCVOpcode<0b0010011>,
+ "crc32.h">, Sched<[]>;
+def CRC32W : RVBUnary<0b0110000, 0b10010, 0b001, RISCVOpcode<0b0010011>,
+ "crc32.w">, Sched<[]>;
+} // Predicates = [HasStdExtZbr]
+
+let Predicates = [HasStdExtZbr, IsRV64] in
+def CRC32D : RVBUnary<0b0110000, 0b10011, 0b001, RISCVOpcode<0b0010011>,
+ "crc32.d">, Sched<[]>;
+
+let Predicates = [HasStdExtZbr] in {
+def CRC32CB : RVBUnary<0b0110000, 0b11000, 0b001, RISCVOpcode<0b0010011>,
+ "crc32c.b">, Sched<[]>;
+def CRC32CH : RVBUnary<0b0110000, 0b11001, 0b001, RISCVOpcode<0b0010011>,
+ "crc32c.h">, Sched<[]>;
+def CRC32CW : RVBUnary<0b0110000, 0b11010, 0b001, RISCVOpcode<0b0010011>,
+ "crc32c.w">, Sched<[]>;
+} // Predicates = [HasStdExtZbr]
+
+let Predicates = [HasStdExtZbr, IsRV64] in
+def CRC32CD : RVBUnary<0b0110000, 0b11011, 0b001, RISCVOpcode<0b0010011>,
+ "crc32c.d">, Sched<[]>;
+
+let Predicates = [HasStdExtZbc] in {
+def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>;
+def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>;
+def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>;
+} // Predicates = [HasStdExtZbc]
+
+let Predicates = [HasStdExtZbb] in {
+def MIN : ALU_rr<0b0000101, 0b100, "min">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def MINU : ALU_rr<0b0000101, 0b101, "minu">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def MAX : ALU_rr<0b0000101, 0b110, "max">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def MAXU : ALU_rr<0b0000101, 0b111, "maxu">,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+} // Predicates = [HasStdExtZbb]
+
+let Predicates = [HasStdExtZbp] in {
+def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
+def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbe] in {
+// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
+// bext in the 0.93 spec.
+def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
+def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
+} // Predicates = [HasStdExtZbe]
+
+let Predicates = [HasStdExtZbp] in {
+def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
+def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
+def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbm, IsRV64] in {
+def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
+def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
+} // Predicates = [HasStdExtZbm, IsRV64]
+
+let Predicates = [HasStdExtZbf] in
+def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
+
+let Predicates = [HasStdExtZbp] in {
+def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
+def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZba, IsRV64] in {
+def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
+ Sched<[WriteShiftImm32, ReadShiftImm32]>;
+def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">,
+ Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
+def SH1ADDUW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">,
+ Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
+def SH2ADDUW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
+ Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
+def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
+ Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
+} // Predicates = [HasStdExtZbb, IsRV64]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
+ Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
+def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
+ Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
+let Predicates = [HasStdExtZbs, IsRV64] in {
+// NOTE: These instructions have been removed from the 0.94 spec. As a result
+// we have no isel patterns for them.
+def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>;
+def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>;
+def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>;
+def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>;
+} // Predicates = [HasStdExtZbs, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
+def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
+def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
+ Sched<[WriteRotateImm32, ReadRotateImm32]>;
+
+let Predicates = [HasStdExtZbs, IsRV64] in {
+// NOTE: These instructions have been removed from the 0.94 spec. As a result
+// we have no isel patterns for them.
+def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">,
+ Sched<[]>;
+def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">,
+ Sched<[]>;
+def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">,
+ Sched<[]>;
+} // Predicates = [HasStdExtZbs, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
+def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbt, IsRV64] in {
+def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32,
+ "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
+def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
+ "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
+def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
+ "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
+} // Predicates = [HasStdExtZbt, IsRV64]
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
+def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
+ "clzw">, Sched<[WriteCLZ32, ReadCLZ32]>;
+def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>,
+ "ctzw">, Sched<[WriteCTZ32, ReadCTZ32]>;
+def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
+ "cpopw">, Sched<[WriteCPOP32, ReadCPOP32]>;
+} // Predicates = [HasStdExtZbb, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
+def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbe, IsRV64] in {
+// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
+// bextw in the 0.93 spec.
+def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
+def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
+} // Predicates = [HasStdExtZbe, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
+def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbf, IsRV64] in
+def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def ZEXTH_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
+ (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
+ Sched<[WriteIALU, ReadIALU]> {
+ let rs2 = 0b00000;
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
+ (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
+ Sched<[WriteIALU, ReadIALU]> {
+ let rs2 = 0b00000;
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
+// We treat rev8 and orc.b as standalone instructions even though they use a
+// portion of the encodings for grevi and gorci. This allows us to support only
+// those encodings when only Zbb is enabled. We do this even when grevi and
+// gorci are available with Zbp. Trying to use 'HasStdExtZbb, NotHasStdExtZbp'
+// causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
+// or gorci. Since Zbb is closer to being finalized than Zbp this will be
+// misleading to users.
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+ "rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
+ let imm12 = { 0b01101, 0b0011000 };
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+ "rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
+ let imm12 = { 0b01101, 0b0111000 };
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+ "orc.b", "$rd, $rs1">, Sched<[WriteORCB, ReadORCB]> {
+ let imm12 = { 0b00101, 0b0000111 };
+}
+} // Predicates = [HasStdExtZbbOrZbp]
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZba, IsRV64] in {
+// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been
+// changed to add.uw in a draft after 0.94.
+def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
+}
+
+let Predicates = [HasStdExtZbp] in {
+def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>;
+def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
+def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
+def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
+def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
+def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
+def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
+def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
+def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
+def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
+
+def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
+def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
+def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>;
+def : InstAlias<"unzip2.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0010)>;
+def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>;
+def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>;
+def : InstAlias<"zip4.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0100)>;
+def : InstAlias<"unzip4.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0100)>;
+def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>;
+def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>;
+def : InstAlias<"zip.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0111)>;
+def : InstAlias<"unzip.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0111)>;
+
+def : InstAlias<"orc.p $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00001)>;
+def : InstAlias<"orc2.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00010)>;
+def : InstAlias<"orc.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00011)>;
+def : InstAlias<"orc4.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00100)>;
+def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>;
+// orc.b is considered an instruction rather than an alias.
+def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>;
+def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>;
+def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>;
+def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbp, IsRV32] in {
+def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
+// rev8 is considered an instruction rather than an alias.
+def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
+def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
+def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
+
+def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>;
+def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>;
+def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
+def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
+def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
+def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
+def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
+def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
+
+def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
+def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
+def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>;
+def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>;
+def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>;
+} // Predicates = [HasStdExtZbp, IsRV32]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>;
+def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>;
+def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>;
+def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>;
+def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>;
+def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>;
+def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>;
+// rev8 is considered an instruction rather than an alias.
+def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111100)>;
+def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111110)>;
+def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>;
+
+def : InstAlias<"zip8.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01000)>;
+def : InstAlias<"unzip8.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01000)>;
+def : InstAlias<"zip4.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01100)>;
+def : InstAlias<"unzip4.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01100)>;
+def : InstAlias<"zip2.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01110)>;
+def : InstAlias<"unzip2.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01110)>;
+def : InstAlias<"zip.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01111)>;
+def : InstAlias<"unzip.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01111)>;
+def : InstAlias<"zip16 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b10000)>;
+def : InstAlias<"unzip16 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b10000)>;
+def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11000)>;
+def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11000)>;
+def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11100)>;
+def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11100)>;
+def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11110)>;
+def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11110)>;
+def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11111)>;
+def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11111)>;
+
+def : InstAlias<"orc16.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b010000)>;
+def : InstAlias<"orc8.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011000)>;
+def : InstAlias<"orc4.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011100)>;
+def : InstAlias<"orc2.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011110)>;
+def : InstAlias<"orc.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011111)>;
+def : InstAlias<"orc32 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b100000)>;
+def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b110000)>;
+def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111000)>;
+def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111100)>;
+def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111110)>;
+def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111111)>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+def : InstAlias<"ror $rd, $rs1, $shamt",
+ (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+} // Predicates = [HasStdExtZbbOrZbp]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+def : InstAlias<"rorw $rd, $rs1, $shamt",
+ (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
+let Predicates = [HasStdExtZbp] in {
+def : InstAlias<"grev $rd, $rs1, $shamt",
+ (GREVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"gorc $rd, $rs1, $shamt",
+ (GORCI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"shfl $rd, $rs1, $shamt",
+ (SHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
+def : InstAlias<"unshfl $rd, $rs1, $shamt",
+ (UNSHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def : InstAlias<"grevw $rd, $rs1, $shamt",
+ (GREVIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
+def : InstAlias<"gorcw $rd, $rs1, $shamt",
+ (GORCIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbs] in {
+def : InstAlias<"bset $rd, $rs1, $shamt",
+ (BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"bclr $rd, $rs1, $shamt",
+ (BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"binv $rd, $rs1, $shamt",
+ (BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+def : InstAlias<"bext $rd, $rs1, $shamt",
+ (BEXTI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
+} // Predicates = [HasStdExtZbs]
+
+//===----------------------------------------------------------------------===//
+// Codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
+def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>;
+def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtZbbOrZbp]
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+def : PatGprGpr<rotl, ROL>;
+def : PatGprGpr<rotr, ROR>;
+} // Predicates = [HasStdExtZbbOrZbp]
+
+let Predicates = [HasStdExtZbs] in {
+def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
+ (BCLR GPR:$rs1, GPR:$rs2)>;
+def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>;
+def : Pat<(or (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
+ (BSET GPR:$rs1, GPR:$rs2)>;
+def : Pat<(xor (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
+ (BINV GPR:$rs1, GPR:$rs2)>;
+def : Pat<(and (shiftop<srl> GPR:$rs1, GPR:$rs2), 1),
+ (BEXT GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(shiftop<shl> 1, GPR:$rs2),
+ (BSET X0, GPR:$rs2)>;
+
+def : Pat<(and GPR:$rs1, BCLRMask:$mask),
+ (BCLRI GPR:$rs1, BCLRMask:$mask)>;
+def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
+ (BSETI GPR:$rs1, BSETINVMask:$mask)>;
+def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
+ (BINVI GPR:$rs1, BSETINVMask:$mask)>;
+
+def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
+ (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
+
+def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i),
+ (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
+ (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
+def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
+ (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
+ (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
+def : Pat<(or GPR:$r, BSETINVORIMask:$i),
+ (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
+ (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
+def : Pat<(xor GPR:$r, BSETINVORIMask:$i),
+ (BINVI (XORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
+ (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
+def : Pat<(and GPR:$r, BCLRITwoBitsMask:$i),
+ (BCLRI (BCLRI GPR:$r, (BCLRITwoBitsMaskLow BCLRITwoBitsMask:$i)),
+ (BCLRITwoBitsMaskHigh BCLRITwoBitsMask:$i))>;
+def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
+ (BCLRI (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i)),
+ (BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>;
+}
+
+// There's no encoding for roli in the the 'B' extension as it can be
+// implemented with rori by negating the immediate.
+let Predicates = [HasStdExtZbbOrZbp] in {
+def : PatGprImm<rotr, RORI, uimmlog2xlen>;
+def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
+ (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
+
+// We treat orc.b as a separate instruction, so match it directly. We also
+// lower the Zbb orc.b intrinsic to this.
+def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
+}
+
+let Predicates = [HasStdExtZbp] in {
+def : PatGprGpr<riscv_grev, GREV>;
+def : PatGprGpr<riscv_gorc, GORC>;
+def : PatGprGpr<riscv_shfl, SHFL>;
+def : PatGprGpr<riscv_unshfl, UNSHFL>;
+def : PatGprGpr<int_riscv_xperm_n, XPERMN>;
+def : PatGprGpr<int_riscv_xperm_b, XPERMB>;
+def : PatGprGpr<int_riscv_xperm_h, XPERMH>;
+def : PatGprGpr<int_riscv_xperm_w, XPERMW>;
+def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
+def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
+def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
+def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
+} // Predicates = [HasStdExtZbp]
+
+let Predicates = [HasStdExtZbp, IsRV32] in {
+def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
+def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
+
+// We treat rev8 as a separate instruction, so match it directly.
+def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
+} // Predicates = [HasStdExtZbp, IsRV32]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+// We treat rev8 as a separate instruction, so match it directly.
+def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbt] in {
+def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
+ (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+
+def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
+ (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
+ (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
+ (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
+ (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
+ (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+} // Predicates = [HasStdExtZbt]
+
+// fshl and fshr concatenate their operands in the same order. fsr and fsl
+// instruction use different orders. fshl will return its first operand for
+// shift of zero, fshr will return its second operand. fsl and fsr both return
+// $rs1 so the patterns need to have different operand orders.
+let Predicates = [HasStdExtZbt] in {
+def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
+ (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(riscv_fsr GPR:$rs3, GPR:$rs1, GPR:$rs2),
+ (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+
+def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
+ (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
+// We can use FSRI for fshl by immediate if we subtract the immediate from
+// XLen and swap the operands.
+def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
+ (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
+} // Predicates = [HasStdExtZbt]
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr<ctlz, CLZ>;
+def : PatGpr<cttz, CTZ>;
+def : PatGpr<ctpop, CPOP>;
+} // Predicates = [HasStdExtZbb]
+
+let Predicates = [HasStdExtZbb] in {
+def : Pat<(sext_inreg GPR:$rs1, i8), (SEXTB GPR:$rs1)>;
+def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>;
+}
+
+let Predicates = [HasStdExtZbb] in {
+def : PatGprGpr<smin, MIN>;
+def : PatGprGpr<smax, MAX>;
+def : PatGprGpr<umin, MINU>;
+def : PatGprGpr<umax, MAXU>;
+} // Predicates = [HasStdExtZbb]
+
+let Predicates = [HasStdExtZbb, IsRV32] in {
+def : Pat<(i32 (bswap GPR:$rs1)), (REV8_RV32 GPR:$rs1)>;
+} // Predicates = [HasStdExtZbb, IsRV32]
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
+def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>;
+} // Predicates = [HasStdExtZbb, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV32] in {
+def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))),
+ (PACK GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))),
+ (PACKU GPR:$rs1, GPR:$rs2)>;
+
+}
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
+ (PACK GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))),
+ (PACKU GPR:$rs1, GPR:$rs2)>;
+}
+let Predicates = [HasStdExtZbp] in
+def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
+ (and GPR:$rs1, 0x00FF)),
+ (PACKH GPR:$rs1, GPR:$rs2)>;
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
+def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV32 GPR:$rs)>;
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
+def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV64 GPR:$rs)>;
+
+// Pattern to exclude simm12 immediates from matching.
+def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
+ auto *C = dyn_cast<ConstantSDNode>(N);
+ return !C || !isInt<12>(C->getSExtValue());
+}]>;
+
+let Predicates = [HasStdExtZba] in {
+def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2),
+ (SH1ADD GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), non_imm12:$rs2),
+ (SH2ADD GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), non_imm12:$rs2),
+ (SH3ADD GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
+ (SH1ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
+ (SH1ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2),
+ (SH1ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2),
+ (SH2ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2),
+ (SH2ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
+ (SH2ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
+ (SH3ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
+ (SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
+ (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+
+def : Pat<(add GPR:$r, CSImm12MulBy4:$i),
+ (SH2ADD (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)),
+ GPR:$r)>;
+def : Pat<(add GPR:$r, CSImm12MulBy8:$i),
+ (SH3ADD (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)),
+ GPR:$r)>;
+
+def : Pat<(mul GPR:$r, C3LeftShift:$i),
+ (SLLI (SH1ADD GPR:$r, GPR:$r),
+ (TrailingZerosXForm C3LeftShift:$i))>;
+def : Pat<(mul GPR:$r, C5LeftShift:$i),
+ (SLLI (SH2ADD GPR:$r, GPR:$r),
+ (TrailingZerosXForm C5LeftShift:$i))>;
+def : Pat<(mul GPR:$r, C9LeftShift:$i),
+ (SLLI (SH3ADD GPR:$r, GPR:$r),
+ (TrailingZerosXForm C9LeftShift:$i))>;
+
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 11)),
+ (SH1ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 19)),
+ (SH1ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 13)),
+ (SH2ADD (SH1ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 21)),
+ (SH2ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 37)),
+ (SH2ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 25)),
+ (SH3ADD (SH1ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 41)),
+ (SH3ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 73)),
+ (SH3ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 27)),
+ (SH1ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 45)),
+ (SH2ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
+ (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
+} // Predicates = [HasStdExtZba]
+
+let Predicates = [HasStdExtZba, IsRV64] in {
+def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
+ (SLLIUW GPR:$rs1, uimm5:$shamt)>;
+def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)),
+ (ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, X0)>;
+
+def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), non_imm12:$rs2)),
+ (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 2)), non_imm12:$rs2)),
+ (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 3)), non_imm12:$rs2)),
+ (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 1)), 0x1FFFFFFFF), non_imm12:$rs2)),
+ (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 2)), 0x3FFFFFFFF), non_imm12:$rs2)),
+ (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2)),
+ (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtZba, IsRV64]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+def : PatGprGpr<riscv_rolw, ROLW>;
+def : PatGprGpr<riscv_rorw, RORW>;
+def : PatGprImm<riscv_rorw, RORIW, uimm5>;
+def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
+ (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
+def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
+def : PatGprGpr<riscv_grevw, GREVW>;
+def : PatGprGpr<riscv_gorcw, GORCW>;
+def : PatGprGpr<riscv_shflw, SHFLW>;
+def : PatGprGpr<riscv_unshflw, UNSHFLW>;
+def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
+def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbt, IsRV64] in {
+def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
+ (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),
+ (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
+ (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
+def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
+ (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
+} // Predicates = [HasStdExtZbt, IsRV64]
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
+def : PatGpr<riscv_clzw, CLZW>;
+def : PatGpr<riscv_ctzw, CTZW>;
+def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
+} // Predicates = [HasStdExtZbb, IsRV64]
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
+ (and GPR:$rs1, 0x000000000000FFFF)),
+ i32)),
+ (PACKW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
+ (and GPR:$rs1, 0x000000000000FFFF))),
+ (PACKW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
+ (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
+ (PACKUW GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbc] in {
+def : PatGprGpr<int_riscv_clmul, CLMUL>;
+def : PatGprGpr<int_riscv_clmulh, CLMULH>;
+def : PatGprGpr<int_riscv_clmulr, CLMULR>;
+} // Predicates = [HasStdExtZbc]
+
+let Predicates = [HasStdExtZbe] in {
+def : PatGprGpr<riscv_bcompress, BCOMPRESS>;
+def : PatGprGpr<riscv_bdecompress, BDECOMPRESS>;
+} // Predicates = [HasStdExtZbe]
+
+let Predicates = [HasStdExtZbe, IsRV64] in {
+def : PatGprGpr<riscv_bcompressw, BCOMPRESSW>;
+def : PatGprGpr<riscv_bdecompressw, BDECOMPRESSW>;
+} // Predicates = [HasStdExtZbe, IsRV64]
+
+let Predicates = [HasStdExtZbr] in {
+def : PatGpr<int_riscv_crc32_b, CRC32B>;
+def : PatGpr<int_riscv_crc32_h, CRC32H>;
+def : PatGpr<int_riscv_crc32_w, CRC32W>;
+def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
+def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
+def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
+} // Predicates = [HasStdExtZbr]
+
+let Predicates = [HasStdExtZbr, IsRV64] in {
+def : PatGpr<int_riscv_crc32_d, CRC32D>;
+def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
+} // Predicates = [HasStdExtZbr, IsRV64]
bool HasStdExtF = false;
bool HasStdExtD = false;
bool HasStdExtC = false;
- bool HasStdExtB = false;
bool HasStdExtZba = false;
bool HasStdExtZbb = false;
bool HasStdExtZbc = false;
bool hasStdExtF() const { return HasStdExtF; }
bool hasStdExtD() const { return HasStdExtD; }
bool hasStdExtC() const { return HasStdExtC; }
- bool hasStdExtB() const { return HasStdExtB; }
bool hasStdExtZba() const { return HasStdExtZba; }
bool hasStdExtZbb() const { return HasStdExtZbb; }
bool hasStdExtZbc() const { return HasStdExtZbc; }
; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
; RV32F: .attribute 5, "rv32i2p0_f2p0"
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
; RV64F: .attribute 5, "rv64i2p0_f2p0"
; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
; RV64C: .attribute 5, "rv64i2p0_c2p0"
-; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBA
; RV32I-NEXT: lh a0, 0(a0)
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sh1add:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a0, a0, a2
-; RV32B-NEXT: lh a0, 0(a0)
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: sh1add:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a2
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sh2add:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a0, a0, a2
-; RV32B-NEXT: lw a0, 0(a0)
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: sh2add:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a2
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sh3add:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a1, a0, a2
-; RV32B-NEXT: lw a0, 0(a1)
-; RV32B-NEXT: lw a1, 4(a1)
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: sh3add:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul6:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a0, a0, a0
-; RV32B-NEXT: sh1add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul6:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul10:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a0, a0, a0
-; RV32B-NEXT: sh1add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul10:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul12:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a0, a0, a0
-; RV32B-NEXT: sh2add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul12:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul18:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: sh1add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul18:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul20:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a0, a0, a0
-; RV32B-NEXT: sh2add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul20:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul24:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a0, a0, a0
-; RV32B-NEXT: sh3add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul24:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul36:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: sh2add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul36:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul40:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a0, a0, a0
-; RV32B-NEXT: sh3add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul40:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addmul72:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: sh3add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addmul72:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul96:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a0, a0, a0
-; RV32B-NEXT: slli a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul96:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul160:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a0, a0, a0
-; RV32B-NEXT: slli a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul160:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul288:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: slli a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul288:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul258:
-; RV32B: # %bb.0:
-; RV32B-NEXT: addi a1, zero, 258
-; RV32B-NEXT: mul a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul258:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 258
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul260:
-; RV32B: # %bb.0:
-; RV32B-NEXT: addi a1, zero, 260
-; RV32B-NEXT: mul a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul260:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 260
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul264:
-; RV32B: # %bb.0:
-; RV32B-NEXT: addi a1, zero, 264
-; RV32B-NEXT: mul a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul264:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 264
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul11:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a1, a0, a0
-; RV32B-NEXT: sh1add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul11:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul19:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a1, a0, a0
-; RV32B-NEXT: sh1add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul19:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul13:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a1, a0, a0
-; RV32B-NEXT: sh2add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul13:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul21:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a1, a0, a0
-; RV32B-NEXT: sh2add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul21:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul37:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a1, a0, a0
-; RV32B-NEXT: sh2add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul37:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul25:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a1, a0, a0
-; RV32B-NEXT: sh3add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul25:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul41:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a1, a0, a0
-; RV32B-NEXT: sh3add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul41:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul73:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a1, a0, a0
-; RV32B-NEXT: sh3add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul73:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a1, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul27:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: sh1add a0, a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul27:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul45:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: sh2add a0, a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul45:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul81:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: sh3add a0, a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul81:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a0, a0
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul4098:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slli a1, a0, 12
-; RV32B-NEXT: sh1add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul4098:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a1, a0, 12
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul4100:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slli a1, a0, 12
-; RV32B-NEXT: sh2add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul4100:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a1, a0, 12
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: mul4104:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slli a1, a0, 12
-; RV32B-NEXT: sh3add a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: mul4104:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a1, a0, 12
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: add4104:
-; RV32B: # %bb.0:
-; RV32B-NEXT: addi a1, zero, 1026
-; RV32B-NEXT: sh2add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: add4104:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: add8208:
-; RV32B: # %bb.0:
-; RV32B-NEXT: addi a1, zero, 1026
-; RV32B-NEXT: sh3add a0, a1, a0
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: add8208:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addshl_5_6:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh1add a0, a1, a0
-; RV32B-NEXT: slli a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addshl_5_6:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh1add a0, a1, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addshl_5_7:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh2add a0, a1, a0
-; RV32B-NEXT: slli a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addshl_5_7:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: addshl_5_8:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sh3add a0, a1, a0
-; RV32B-NEXT: slli a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBA-LABEL: addshl_5_8:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: sh3add a0, a1, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBB
declare i32 @llvm.riscv.orc.b.i32(i32)
define i32 @orcb(i32 %a) nounwind {
-; RV32B-LABEL: orcb:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: orcb:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: orc.b a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBB
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: andn_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andn a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: andn_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andn a0, a0, a1
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: andn_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andn a0, a0, a2
-; RV32B-NEXT: andn a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: andn_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andn a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: orn_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orn a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: orn_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: orn a0, a0, a1
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: orn_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orn a0, a0, a2
-; RV32B-NEXT: orn a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: orn_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: orn a0, a0, a2
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: xnor_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xnor a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: xnor_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: xnor a0, a0, a1
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: xnor_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xnor a0, a0, a2
-; RV32B-NEXT: xnor a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: xnor_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: xnor a0, a0, a2
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: rol_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rol a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: rol_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rol a0, a0, a1
ret i32 %or
}
-; As we are not matching directly i64 code patterns on RV32 some i64 patterns
-; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern.
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: ret
;
-; RV32B-LABEL: rol_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sll a7, a1, a2
-; RV32B-NEXT: andi a4, a2, 63
-; RV32B-NEXT: addi a6, zero, 31
-; RV32B-NEXT: sub a5, a6, a4
-; RV32B-NEXT: srli a3, a0, 1
-; RV32B-NEXT: srl a3, a3, a5
-; RV32B-NEXT: or a7, a7, a3
-; RV32B-NEXT: addi t1, a4, -32
-; RV32B-NEXT: sll a5, a0, t1
-; RV32B-NEXT: slti a3, t1, 0
-; RV32B-NEXT: cmov a7, a3, a7, a5
-; RV32B-NEXT: neg a5, a2
-; RV32B-NEXT: srl t0, a1, a5
-; RV32B-NEXT: andi t2, a5, 63
-; RV32B-NEXT: addi a4, t2, -32
-; RV32B-NEXT: srai a3, a4, 31
-; RV32B-NEXT: and a3, a3, t0
-; RV32B-NEXT: or a7, a7, a3
-; RV32B-NEXT: srl t0, a0, a5
-; RV32B-NEXT: sub a5, a6, t2
-; RV32B-NEXT: slli a3, a1, 1
-; RV32B-NEXT: sll a3, a3, a5
-; RV32B-NEXT: or a3, t0, a3
-; RV32B-NEXT: srl a1, a1, a4
-; RV32B-NEXT: slti a4, a4, 0
-; RV32B-NEXT: cmov a1, a4, a3, a1
-; RV32B-NEXT: sll a0, a0, a2
-; RV32B-NEXT: srai a2, t1, 31
-; RV32B-NEXT: and a0, a2, a0
-; RV32B-NEXT: or a0, a0, a1
-; RV32B-NEXT: mv a1, a7
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: rol_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a7, a1
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: ror_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ror a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: ror_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ror a0, a0, a1
ret i32 %or
}
-; As we are not matching directly i64 code patterns on RV32 some i64 patterns
-; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern.
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
;
-; RV32B-LABEL: ror_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: srl a7, a0, a2
-; RV32B-NEXT: andi a4, a2, 63
-; RV32B-NEXT: addi a6, zero, 31
-; RV32B-NEXT: sub a5, a6, a4
-; RV32B-NEXT: slli a3, a1, 1
-; RV32B-NEXT: sll a3, a3, a5
-; RV32B-NEXT: or a7, a7, a3
-; RV32B-NEXT: addi t1, a4, -32
-; RV32B-NEXT: srl a5, a1, t1
-; RV32B-NEXT: slti a3, t1, 0
-; RV32B-NEXT: cmov a7, a3, a7, a5
-; RV32B-NEXT: neg a5, a2
-; RV32B-NEXT: sll t0, a0, a5
-; RV32B-NEXT: andi t2, a5, 63
-; RV32B-NEXT: addi a4, t2, -32
-; RV32B-NEXT: srai a3, a4, 31
-; RV32B-NEXT: and a3, a3, t0
-; RV32B-NEXT: or a7, a7, a3
-; RV32B-NEXT: sll t0, a1, a5
-; RV32B-NEXT: sub a5, a6, t2
-; RV32B-NEXT: srli a3, a0, 1
-; RV32B-NEXT: srl a3, a3, a5
-; RV32B-NEXT: or a3, t0, a3
-; RV32B-NEXT: sll a0, a0, a4
-; RV32B-NEXT: slti a4, a4, 0
-; RV32B-NEXT: cmov a0, a4, a3, a0
-; RV32B-NEXT: srl a1, a1, a2
-; RV32B-NEXT: srai a2, t1, 31
-; RV32B-NEXT: and a1, a2, a1
-; RV32B-NEXT: or a1, a1, a0
-; RV32B-NEXT: mv a0, a7
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: ror_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv t0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: rori_i32_fshl:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rori a0, a0, 1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: rori_i32_fshl:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rori a0, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: rori_i32_fshr:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rori a0, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: rori_i32_fshr:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rori a0, a0, 31
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: rori_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: fsri a2, a0, a1, 1
-; RV32B-NEXT: fsri a1, a1, a0, 1
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: rori_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: slli a2, a1, 31
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: rori_i64_fshr:
-; RV32B: # %bb.0:
-; RV32B-NEXT: fsri a2, a1, a0, 31
-; RV32B-NEXT: fsri a1, a0, a1, 31
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: rori_i64_fshr:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: slli a2, a0, 1
; RV32I-NEXT: srli a0, a0, 6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: srli_i8:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andi a0, a0, 192
-; RV32B-NEXT: srli a0, a0, 6
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: srli_i8:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: andi a0, a0, 192
; RV32I-NEXT: srai a0, a0, 29
; RV32I-NEXT: ret
;
-; RV32B-LABEL: srai_i8:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sext.b a0, a0
-; RV32B-NEXT: srai a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: srai_i8:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.b a0, a0
; RV32I-NEXT: srli a0, a0, 22
; RV32I-NEXT: ret
;
-; RV32B-LABEL: srli_i16:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zext.h a0, a0
-; RV32B-NEXT: srli a0, a0, 6
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: srli_i16:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0
; RV32I-NEXT: srai a0, a0, 25
; RV32I-NEXT: ret
;
-; RV32B-LABEL: srai_i16:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sext.h a0, a0
-; RV32B-NEXT: srai a0, a0, 9
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: srai_i16:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.h a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBB
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: ret
;
-; RV32B-LABEL: ctlz_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: clz a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: ctlz_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: clz a0, a0
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV32B-LABEL: ctlz_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: clz a2, a1
-; RV32B-NEXT: clz a0, a0
-; RV32B-NEXT: addi a0, a0, 32
-; RV32B-NEXT: cmov a0, a1, a2, a0
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: ctlz_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a1, .LBB1_2
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cttz_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ctz a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: cttz_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ctz a0, a0
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cttz_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ctz a2, a0
-; RV32B-NEXT: ctz a1, a1
-; RV32B-NEXT: addi a1, a1, 32
-; RV32B-NEXT: cmov a0, a0, a2, a1
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: cttz_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a0, .LBB3_2
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32B-LABEL: ctpop_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: cpop a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: ctpop_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: cpop a0, a0
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV32B-LABEL: ctpop_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: cpop a1, a1
-; RV32B-NEXT: cpop a0, a0
-; RV32B-NEXT: add a0, a0, a1
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: ctpop_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: cpop a1, a1
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sextb_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sext.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: sextb_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.b a0, a0
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sextb_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sext.b a0, a0
-; RV32B-NEXT: srai a1, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: sextb_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.b a0, a0
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sexth_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sext.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: sexth_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.h a0, a0
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sexth_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sext.h a0, a0
-; RV32B-NEXT: srai a1, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: sexth_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: sext.h a0, a0
; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: min_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: min a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: min_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: min a0, a0, a1
; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: min_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slt a4, a1, a3
-; RV32B-NEXT: cmov a4, a4, a0, a2
-; RV32B-NEXT: minu a0, a0, a2
-; RV32B-NEXT: xor a2, a1, a3
-; RV32B-NEXT: cmov a0, a2, a4, a0
-; RV32B-NEXT: min a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: min_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0
; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: max_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: max a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: max_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: max a0, a0, a1
; RV32I-NEXT: .LBB13_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: max_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slt a4, a3, a1
-; RV32B-NEXT: cmov a4, a4, a0, a2
-; RV32B-NEXT: maxu a0, a0, a2
-; RV32B-NEXT: xor a2, a1, a3
-; RV32B-NEXT: cmov a0, a2, a4, a0
-; RV32B-NEXT: max a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: max_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0
; RV32I-NEXT: .LBB14_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: minu_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: minu a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: minu_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: minu a0, a0, a1
; RV32I-NEXT: .LBB15_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: minu_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sltu a4, a1, a3
-; RV32B-NEXT: cmov a4, a4, a0, a2
-; RV32B-NEXT: minu a0, a0, a2
-; RV32B-NEXT: xor a2, a1, a3
-; RV32B-NEXT: cmov a0, a2, a4, a0
-; RV32B-NEXT: minu a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: minu_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0
; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: maxu_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: maxu a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: maxu_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: maxu a0, a0, a1
; RV32I-NEXT: .LBB17_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: maxu_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sltu a4, a3, a1
-; RV32B-NEXT: cmov a4, a4, a0, a2
-; RV32B-NEXT: maxu a0, a0, a2
-; RV32B-NEXT: xor a2, a1, a3
-; RV32B-NEXT: cmov a0, a2, a4, a0
-; RV32B-NEXT: maxu a1, a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: maxu_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a4, a0
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: abs_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: neg a1, a0
-; RV32B-NEXT: max a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: abs_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: neg a1, a0
; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: abs_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: neg a2, a0
-; RV32B-NEXT: slti a3, a1, 0
-; RV32B-NEXT: cmov a2, a3, a2, a0
-; RV32B-NEXT: snez a0, a0
-; RV32B-NEXT: add a0, a1, a0
-; RV32B-NEXT: neg a0, a0
-; RV32B-NEXT: cmov a1, a3, a0, a1
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: abs_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bgez a1, .LBB19_2
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: zexth_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zext.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: zexth_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
-; RV32B-LABEL: zexth_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zext.h a0, a0
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: zexth_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8 a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: bswap_i32:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8 a2, a1
-; RV32B-NEXT: rev8 a1, a0
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBB-LABEL: bswap_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a2, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBC
declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
define i32 @clmul32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: clmul32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: clmul a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBC-LABEL: clmul32:
; RV32ZBC: # %bb.0:
; RV32ZBC-NEXT: clmul a0, a0, a1
declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
define i32 @clmul32h(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: clmul32h:
-; RV32B: # %bb.0:
-; RV32B-NEXT: clmulh a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBC-LABEL: clmul32h:
; RV32ZBC: # %bb.0:
; RV32ZBC-NEXT: clmulh a0, a0, a1
declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
define i32 @clmul32r(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: clmul32r:
-; RV32B: # %bb.0:
-; RV32B-NEXT: clmulr a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBC-LABEL: clmul32r:
; RV32ZBC: # %bb.0:
; RV32ZBC-NEXT: clmulr a0, a0, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBE
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
define i32 @bcompress32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: bcompress32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bcompress a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBE-LABEL: bcompress32:
; RV32ZBE: # %bb.0:
; RV32ZBE-NEXT: bcompress a0, a0, a1
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
define i32 @bdecompress32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: bdecompress32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bdecompress a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBE-LABEL: bdecompress32:
; RV32ZBE: # %bb.0:
; RV32ZBE-NEXT: bdecompress a0, a0, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBP
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
define i32 @grev32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: grev32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: grev a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grev a0, a0, a1
}
define i32 @grev32_demandedbits(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: grev32_demandedbits:
-; RV32B: # %bb.0:
-; RV32B-NEXT: grev a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev32_demandedbits:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grev a0, a0, a1
}
define i32 @grevi32(i32 %a) nounwind {
-; RV32B-LABEL: grevi32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: grevi a0, a0, 13
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grevi32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 13
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define i32 @gorc32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: gorc32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: gorc a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorc a0, a0, a1
}
define i32 @gorc32_demandedbits(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: gorc32_demandedbits:
-; RV32B: # %bb.0:
-; RV32B-NEXT: gorc a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc32_demandedbits:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorc a0, a0, a1
}
define i32 @gorci32(i32 %a) nounwind {
-; RV32B-LABEL: gorci32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: gorci a0, a0, 13
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorci32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 13
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define i32 @shfl32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: shfl32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: shfl a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfl a0, a0, a1
}
define i32 @shfl32_demandedbits(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: shfl32_demandedbits:
-; RV32B: # %bb.0:
-; RV32B-NEXT: shfl a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl32_demandedbits:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfl a0, a0, a1
}
define i32 @shfli32(i32 %a) nounwind {
-; RV32B-LABEL: shfli32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: shfli a0, a0, 13
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfli32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: shfli a0, a0, 13
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define i32 @unshfl32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: unshfl32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: unshfl a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: unshfl32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: unshfl a0, a0, a1
}
define i32 @unshfl32_demandedbits(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: unshfl32_demandedbits:
-; RV32B: # %bb.0:
-; RV32B-NEXT: unshfl a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: unshfl32_demandedbits:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: unshfl a0, a0, a1
}
define i32 @unshfli32(i32 %a) nounwind {
-; RV32B-LABEL: unshfli32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: unshfli a0, a0, 13
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: unshfli32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: unshfli a0, a0, 13
declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
define i32 @xpermn32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: xpermn32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xperm.n a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: xpermn32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xperm.n a0, a0, a1
declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
define i32 @xpermb32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: xpermb32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xperm.b a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: xpermb32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xperm.b a0, a0, a1
declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
define i32 @xpermh32(i32 %a, i32 %b) nounwind {
-; RV32B-LABEL: xpermh32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xperm.h a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: xpermh32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: xperm.h a0, a0, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBP
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc1_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.p a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc1_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.p a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc1_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.p a0, a0
-; RV32B-NEXT: orc.p a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc1_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.p a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc2_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc2.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc2_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc2_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc2.n a0, a0
-; RV32B-NEXT: orc2.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc2_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc3_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc3_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc3_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.n a0, a0
-; RV32B-NEXT: orc.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc3_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc4_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc4.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc4_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.b a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc4_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc4.b a0, a0
-; RV32B-NEXT: orc4.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc4_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.b a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc5_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: gorci a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc5_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 5
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc5_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: gorci a0, a0, 5
-; RV32B-NEXT: gorci a1, a1, 5
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc5_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 5
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc6_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc2.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc6_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.b a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc6_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc2.b a0, a0
-; RV32B-NEXT: orc2.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc6_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.b a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc7_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc7_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.b a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc7_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.b a0, a0
-; RV32B-NEXT: orc.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc7_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.b a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc8_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc8.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc8_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc8.h a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc8_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc8.h a0, a0
-; RV32B-NEXT: orc8.h a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc8_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc8.h a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc16_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc16 a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc16_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc16_rotl_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc16 a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc16_rotl_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc16_rotr_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc16 a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc16_rotr_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc16_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc16 a0, a0
-; RV32B-NEXT: orc16 a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc16_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc16 a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc2b_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc2.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc2b_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc2b_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc2.n a0, a0
-; RV32B-NEXT: orc2.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc2b_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc3b_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc3b_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: gorc3b_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: orc.n a0, a0
-; RV32B-NEXT: orc.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: gorc3b_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev1_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.p a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev1_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.p a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev1_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.p a0, a0
-; RV32B-NEXT: rev.p a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev1_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.p a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev2_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev2.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev2_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev2_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev2.n a0, a0
-; RV32B-NEXT: rev2.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev2_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev3_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev3_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev3_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.n a0, a0
-; RV32B-NEXT: rev.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev3_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev4_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev4.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev4_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev4.b a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev4_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev4.b a0, a0
-; RV32B-NEXT: rev4.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev4_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev4.b a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev5_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: grevi a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev5_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 5
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev5_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: grevi a0, a0, 5
-; RV32B-NEXT: grevi a1, a1, 5
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev5_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: grevi a0, a0, 5
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev6_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev2.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev6_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.b a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev6_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev2.b a0, a0
-; RV32B-NEXT: rev2.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev6_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.b a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev7_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev7_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev7_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.b a0, a0
-; RV32B-NEXT: rev.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev7_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev8_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev8_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev8_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8.h a0, a0
-; RV32B-NEXT: rev8.h a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev8_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev16_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rori a0, a0, 16
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev16_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev3b_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev3b_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev3b_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.n a0, a0
-; RV32B-NEXT: rev.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev3b_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.n a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev2b_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev2.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev2b_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev2b_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev2.n a0, a0
-; RV32B-NEXT: rev2.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev2b_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev2.n a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev0_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev0_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: ret
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev0_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev0_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: ret
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev16_i32_fshl:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rori a0, a0, 16
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev16_i32_fshl:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev16_i32_fshr:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rori a0, a0, 16
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev16_i32_fshr:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: grev16_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rori a0, a0, 16
-; RV32B-NEXT: rori a1, a1, 16
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: grev16_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rori a0, a0, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_i16:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bswap_i16:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8 a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bswap_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8 a0, a0
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8 a2, a1
-; RV32B-NEXT: rev8 a1, a0
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bswap_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8 a2, a1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bitreverse_i8:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bitreverse_i8:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bitreverse_i16:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bitreverse_i16:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.h a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bitreverse_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bitreverse_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev a0, a0
; RV32I-NEXT: mv a0, t0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bitreverse_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev a2, a1
-; RV32B-NEXT: rev a1, a0
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bitreverse_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev a2, a1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_rotr_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bswap_rotr_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bswap_rotl_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev8.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bswap_rotl_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev8.h a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bitreverse_bswap_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bitreverse_bswap_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: bitreverse_bswap_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: rev.b a0, a0
-; RV32B-NEXT: rev.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: bitreverse_bswap_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl1_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip.n a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl1_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip.n a0, a0
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl1_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip.n a0, a0
-; RV32B-NEXT: zip.n a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl1_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip.n a0, a0
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl2_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip2.b a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl2_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip2.b a0, a0
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl2_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip2.b a0, a0
-; RV32B-NEXT: zip2.b a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl2_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip2.b a0, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl4_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip4.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl4_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip4.h a0, a0
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl4_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip4.h a0, a0
-; RV32B-NEXT: zip4.h a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl4_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip4.h a0, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl8_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip8 a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl8_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip8 a0, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: shfl8_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zip8 a0, a0
-; RV32B-NEXT: zip8 a1, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: shfl8_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip8 a0, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: pack_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: pack a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: pack_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: pack a0, a0, a1
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: pack_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: mv a1, a2
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: pack_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: mv a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: packu_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: packu a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: packu_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packu a0, a0, a1
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
;
-; RV32B-LABEL: packu_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: mv a0, a1
-; RV32B-NEXT: mv a1, a3
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: packu_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: mv a0, a1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: packh_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: packh a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: packh_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packh a0, a0, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
-; RV32B-LABEL: packh_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: packh a0, a0, a2
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: packh_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packh a0, a0, a2
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: zexth_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zext.h a0, a0
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: zexth_i32:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zext.h a0, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
-; RV32B-LABEL: zexth_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: zext.h a0, a0
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBP-LABEL: zexth_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zext.h a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBS
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclr_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclr a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclr_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclr a0, a0, a1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclr_i32_no_mask:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclr a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclr_i32_no_mask:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclr a0, a0, a1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclr_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bset a3, zero, a2
-; RV32B-NEXT: andi a2, a2, 63
-; RV32B-NEXT: addi a2, a2, -32
-; RV32B-NEXT: srai a4, a2, 31
-; RV32B-NEXT: and a3, a4, a3
-; RV32B-NEXT: slti a4, a2, 0
-; RV32B-NEXT: bclr a2, a1, a2
-; RV32B-NEXT: cmov a1, a4, a1, a2
-; RV32B-NEXT: andn a0, a0, a3
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclr_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a3, a2, 63
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbset_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bset a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbset_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a0, a0, a1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbset_i32_no_mask:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bset a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbset_i32_no_mask:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a0, a0, a1
; RV32I-NEXT: sll a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbset_i32_zero:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bset a0, zero, a0
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbset_i32_zero:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a0, zero, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbset_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bset a3, zero, a2
-; RV32B-NEXT: srai a3, a3, 31
-; RV32B-NEXT: bset a0, a0, a2
-; RV32B-NEXT: or a1, a3, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbset_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a3, zero, a2
; RV32I-NEXT: sll a0, a2, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbset_i64_zero:
-; RV32B: # %bb.0:
-; RV32B-NEXT: addi a2, a0, -32
-; RV32B-NEXT: bset a1, zero, a2
-; RV32B-NEXT: slti a3, a2, 0
-; RV32B-NEXT: cmov a1, a3, zero, a1
-; RV32B-NEXT: bset a0, zero, a0
-; RV32B-NEXT: srai a2, a2, 31
-; RV32B-NEXT: and a0, a2, a0
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbset_i64_zero:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: addi a1, a0, -32
; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbinv_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: binv a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbinv_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binv a0, a0, a1
; RV32I-NEXT: xor a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbinv_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bset a3, zero, a2
-; RV32B-NEXT: srai a3, a3, 31
-; RV32B-NEXT: binv a0, a0, a2
-; RV32B-NEXT: xor a1, a3, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbinv_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bset a3, zero, a2
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbext_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bext a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbext_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbext_i32_no_mask:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bext a0, a0, a1
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbext_i32_no_mask:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbext_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: srl a0, a0, a2
-; RV32B-NEXT: andi a2, a2, 63
-; RV32B-NEXT: addi a3, zero, 31
-; RV32B-NEXT: sub a3, a3, a2
-; RV32B-NEXT: slli a4, a1, 1
-; RV32B-NEXT: sll a3, a4, a3
-; RV32B-NEXT: or a0, a0, a3
-; RV32B-NEXT: addi a2, a2, -32
-; RV32B-NEXT: srl a1, a1, a2
-; RV32B-NEXT: slti a2, a2, 0
-; RV32B-NEXT: cmov a0, a2, a0, a1
-; RV32B-NEXT: andi a0, a0, 1
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbext_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a3, a2, 63
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbexti_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bexti a0, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbexti_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bexti a0, a0, 5
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbexti_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bexti a0, a0, 5
-; RV32B-NEXT: mv a1, zero
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbexti_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bexti a0, a0, 5
; RV32I-NEXT: andi a0, a0, -1025
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_10:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andi a0, a0, -1025
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_10:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a0, a0, -1025
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_11:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclri a0, a0, 11
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_11:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 11
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_30:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclri a0, a0, 30
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_30:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 30
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_31:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclri a0, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_31:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 31
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_large0:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andi a0, a0, -256
-; RV32B-NEXT: bclri a0, a0, 24
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_large0:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a0, a0, -256
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_large1:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclri a0, a0, 16
-; RV32B-NEXT: bclri a0, a0, 24
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_large1:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_large2:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bclri a0, a0, 2
-; RV32B-NEXT: bclri a0, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_large2:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bclri a0, a0, 2
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbclri_i32_large3:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andi a0, a0, -6
-; RV32B-NEXT: bclri a0, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbclri_i32_large3:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: andi a0, a0, -6
; RV32I-NEXT: ori a0, a0, 1024
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbseti_i32_10:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ori a0, a0, 1024
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbseti_i32_10:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 1024
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbseti_i32_11:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bseti a0, a0, 11
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbseti_i32_11:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 11
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbseti_i32_30:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bseti a0, a0, 30
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbseti_i32_30:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 30
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbseti_i32_31:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bseti a0, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbseti_i32_31:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 31
; RV32I-NEXT: xori a0, a0, 1024
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbinvi_i32_10:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xori a0, a0, 1024
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbinvi_i32_10:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 1024
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbinvi_i32_11:
-; RV32B: # %bb.0:
-; RV32B-NEXT: binvi a0, a0, 11
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbinvi_i32_11:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 11
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbinvi_i32_30:
-; RV32B: # %bb.0:
-; RV32B-NEXT: binvi a0, a0, 30
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbinvi_i32_30:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 30
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: sbinvi_i32_31:
-; RV32B: # %bb.0:
-; RV32B-NEXT: binvi a0, a0, 31
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: sbinvi_i32_31:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 31
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: xor_i32_4098:
-; RV32B: # %bb.0:
-; RV32B-NEXT: binvi a0, a0, 1
-; RV32B-NEXT: binvi a0, a0, 12
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: xor_i32_4098:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: binvi a0, a0, 1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: xor_i32_4099:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xori a0, a0, 3
-; RV32B-NEXT: binvi a0, a0, 12
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: xor_i32_4099:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 3
; RV32I-NEXT: xori a0, a0, 96
; RV32I-NEXT: ret
;
-; RV32B-LABEL: xor_i32_96:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xori a0, a0, 96
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: xor_i32_96:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 96
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: xor_i32_66901:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xori a0, a0, 1365
-; RV32B-NEXT: binvi a0, a0, 16
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: xor_i32_66901:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: xori a0, a0, 1365
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: or_i32_4098:
-; RV32B: # %bb.0:
-; RV32B-NEXT: bseti a0, a0, 1
-; RV32B-NEXT: bseti a0, a0, 12
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: or_i32_4098:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bseti a0, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: or_i32_4099:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ori a0, a0, 3
-; RV32B-NEXT: bseti a0, a0, 12
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: or_i32_4099:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 3
; RV32I-NEXT: ori a0, a0, 96
; RV32I-NEXT: ret
;
-; RV32B-LABEL: or_i32_96:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ori a0, a0, 96
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: or_i32_96:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 96
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: or_i32_66901:
-; RV32B: # %bb.0:
-; RV32B-NEXT: ori a0, a0, 1365
-; RV32B-NEXT: bseti a0, a0, 16
-; RV32B-NEXT: ret
-;
; RV32ZBS-LABEL: or_i32_66901:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: ori a0, a0, 1365
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV32B
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBT
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmix_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: cmix a0, a1, a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmix_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmix a0, a1, a0, a2
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmix_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: cmix a0, a2, a0, a4
-; RV32B-NEXT: cmix a1, a3, a1, a5
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmix_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmix a0, a2, a0, a4
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: cmov a0, a1, a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: cmov a0, a1, a0, a2
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_sle_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slt a1, a2, a1
-; RV32B-NEXT: cmov a0, a1, a3, a0
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_sle_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a2, a1
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_sge_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: slt a1, a1, a2
-; RV32B-NEXT: cmov a0, a1, a3, a0
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_sge_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: slt a1, a1, a2
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_ule_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sltu a1, a2, a1
-; RV32B-NEXT: cmov a0, a1, a3, a0
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_ule_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a2, a1
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_uge_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sltu a1, a1, a2
-; RV32B-NEXT: cmov a0, a1, a3, a0
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_uge_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sltu a1, a1, a2
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: or a2, a2, a3
-; RV32B-NEXT: cmov a0, a2, a0, a4
-; RV32B-NEXT: cmov a1, a2, a1, a5
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: or a2, a2, a3
; RV32I-NEXT: .LBB8_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_sle_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xor t0, a3, a5
-; RV32B-NEXT: sltu a2, a4, a2
-; RV32B-NEXT: xori a2, a2, 1
-; RV32B-NEXT: slt a3, a5, a3
-; RV32B-NEXT: xori a3, a3, 1
-; RV32B-NEXT: cmov a2, t0, a3, a2
-; RV32B-NEXT: cmov a0, a2, a0, a6
-; RV32B-NEXT: cmov a1, a2, a1, a7
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_sle_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5
; RV32I-NEXT: .LBB9_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_sge_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xor t0, a3, a5
-; RV32B-NEXT: sltu a2, a2, a4
-; RV32B-NEXT: xori a2, a2, 1
-; RV32B-NEXT: slt a3, a3, a5
-; RV32B-NEXT: xori a3, a3, 1
-; RV32B-NEXT: cmov a2, t0, a3, a2
-; RV32B-NEXT: cmov a0, a2, a0, a6
-; RV32B-NEXT: cmov a1, a2, a1, a7
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_sge_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5
; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_ule_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xor t0, a3, a5
-; RV32B-NEXT: sltu a2, a4, a2
-; RV32B-NEXT: xori a2, a2, 1
-; RV32B-NEXT: sltu a3, a5, a3
-; RV32B-NEXT: xori a3, a3, 1
-; RV32B-NEXT: cmov a2, t0, a3, a2
-; RV32B-NEXT: cmov a0, a2, a0, a6
-; RV32B-NEXT: cmov a1, a2, a1, a7
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_ule_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5
; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: cmov_uge_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: xor t0, a3, a5
-; RV32B-NEXT: sltu a2, a2, a4
-; RV32B-NEXT: xori a2, a2, 1
-; RV32B-NEXT: sltu a3, a3, a5
-; RV32B-NEXT: xori a3, a3, 1
-; RV32B-NEXT: cmov a2, t0, a3, a2
-; RV32B-NEXT: cmov a0, a2, a0, a6
-; RV32B-NEXT: cmov a1, a2, a1, a7
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: cmov_uge_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: xor t0, a3, a5
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshl_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andi a2, a2, 31
-; RV32B-NEXT: fsl a0, a0, a1, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshl_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: andi a2, a2, 31
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshl_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: sll a7, a1, a4
-; RV32B-NEXT: andi a5, a4, 63
-; RV32B-NEXT: addi a6, zero, 31
-; RV32B-NEXT: sub t0, a6, a5
-; RV32B-NEXT: srli a1, a0, 1
-; RV32B-NEXT: srl a1, a1, t0
-; RV32B-NEXT: or a7, a7, a1
-; RV32B-NEXT: addi t1, a5, -32
-; RV32B-NEXT: sll t0, a0, t1
-; RV32B-NEXT: slti a1, t1, 0
-; RV32B-NEXT: cmov t0, a1, a7, t0
-; RV32B-NEXT: not a7, a4
-; RV32B-NEXT: srli t4, a3, 1
-; RV32B-NEXT: srl t2, t4, a7
-; RV32B-NEXT: addi a1, zero, 63
-; RV32B-NEXT: andn t3, a1, a4
-; RV32B-NEXT: addi a5, t3, -32
-; RV32B-NEXT: srai a1, a5, 31
-; RV32B-NEXT: and a1, a1, t2
-; RV32B-NEXT: or a1, t0, a1
-; RV32B-NEXT: fsri a2, a2, a3, 1
-; RV32B-NEXT: srl a7, a2, a7
-; RV32B-NEXT: sub a3, a6, t3
-; RV32B-NEXT: slli a2, t4, 1
-; RV32B-NEXT: sll a2, a2, a3
-; RV32B-NEXT: or a2, a7, a2
-; RV32B-NEXT: srl a3, t4, a5
-; RV32B-NEXT: slti a5, a5, 0
-; RV32B-NEXT: cmov a2, a5, a2, a3
-; RV32B-NEXT: sll a0, a0, a4
-; RV32B-NEXT: srai a3, t1, 31
-; RV32B-NEXT: and a0, a3, a0
-; RV32B-NEXT: or a0, a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshl_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: sll a7, a1, a4
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshr_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: andi a2, a2, 31
-; RV32B-NEXT: fsr a0, a1, a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshr_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: andi a2, a2, 31
; RV32I-NEXT: .LBB15_7:
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshr_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: srl a7, a2, a4
-; RV32B-NEXT: andi a5, a4, 63
-; RV32B-NEXT: addi a6, zero, 31
-; RV32B-NEXT: sub t0, a6, a5
-; RV32B-NEXT: slli a2, a3, 1
-; RV32B-NEXT: sll a2, a2, t0
-; RV32B-NEXT: or a7, a7, a2
-; RV32B-NEXT: addi t2, a5, -32
-; RV32B-NEXT: srl t0, a3, t2
-; RV32B-NEXT: slti a2, t2, 0
-; RV32B-NEXT: cmov a7, a2, a7, t0
-; RV32B-NEXT: not t3, a4
-; RV32B-NEXT: slli t0, a0, 1
-; RV32B-NEXT: sll t1, t0, t3
-; RV32B-NEXT: addi a5, zero, 63
-; RV32B-NEXT: andn t4, a5, a4
-; RV32B-NEXT: addi a2, t4, -32
-; RV32B-NEXT: srai a5, a2, 31
-; RV32B-NEXT: and a5, a5, t1
-; RV32B-NEXT: or a7, a5, a7
-; RV32B-NEXT: fsri a1, a0, a1, 31
-; RV32B-NEXT: sll a1, a1, t3
-; RV32B-NEXT: sub a5, a6, t4
-; RV32B-NEXT: bclri a0, a0, 31
-; RV32B-NEXT: srl a0, a0, a5
-; RV32B-NEXT: or a0, a1, a0
-; RV32B-NEXT: sll a1, t0, a2
-; RV32B-NEXT: slti a2, a2, 0
-; RV32B-NEXT: cmov a0, a2, a0, a1
-; RV32B-NEXT: srl a1, a3, a4
-; RV32B-NEXT: srai a2, t2, 31
-; RV32B-NEXT: and a1, a2, a1
-; RV32B-NEXT: or a1, a0, a1
-; RV32B-NEXT: mv a0, a7
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshr_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: srl a7, a2, a4
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshri_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: fsri a0, a1, a0, 5
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshri_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a0, a1, a0, 5
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshri_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: fsri a2, a2, a3, 5
-; RV32B-NEXT: fsri a1, a3, a0, 5
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshri_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a2, a2, a3, 5
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshli_i32:
-; RV32B: # %bb.0:
-; RV32B-NEXT: fsri a0, a1, a0, 27
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshli_i32:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a0, a1, a0, 27
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
-; RV32B-LABEL: fshli_i64:
-; RV32B: # %bb.0:
-; RV32B-NEXT: fsri a2, a3, a0, 27
-; RV32B-NEXT: fsri a1, a0, a1, 27
-; RV32B-NEXT: mv a0, a2
-; RV32B-NEXT: ret
-;
; RV32ZBT-LABEL: fshli_i64:
; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: fsri a2, a3, a0, 27
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBA
; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: ret
;
-; RV64B-LABEL: slliuw:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli.uw a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: slliuw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 1
; RV64I-NEXT: ld a1, 8(a1)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: slliuw_2:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli.uw a0, a0, 4
-; RV64B-NEXT: add a1, a1, a0
-; RV64B-NEXT: ld a0, 0(a1)
-; RV64B-NEXT: ld a1, 8(a1)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: slliuw_2:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 4
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: adduw:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add.uw a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: adduw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: add.uw a0, a1, a0
; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: adduw_2:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add.uw a0, a0, a1
-; RV64B-NEXT: lb a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: adduw_2:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: add.uw a0, a0, a1
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
-; RV64B-LABEL: zextw_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: zextw_i64:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: zext.w a0, a0
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
-; RV64B-LABEL: zextw_demandedbits_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ori a0, a0, 1
-; RV64B-NEXT: zext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: zextw_demandedbits_i64:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: ori a0, a0, 1
; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh1add:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a0, a1
-; RV64B-NEXT: lh a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh1add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a1
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh2add:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a1
-; RV64B-NEXT: lw a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh2add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh3add:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a1
-; RV64B-NEXT: ld a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh3add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh1adduw:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add.uw a0, a0, a1
-; RV64B-NEXT: lh a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh1adduw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add.uw a0, a0, a1
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh1adduw_2:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add.uw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh1adduw_2:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add.uw a0, a0, a1
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh2adduw:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add.uw a0, a0, a1
-; RV64B-NEXT: lw a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh2adduw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add.uw a0, a0, a1
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh2adduw_2:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add.uw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh2adduw_2:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add.uw a0, a0, a1
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh3adduw:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add.uw a0, a0, a1
-; RV64B-NEXT: ld a0, 0(a0)
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh3adduw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add.uw a0, a0, a1
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh3adduw_2:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add.uw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh3adduw_2:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add.uw a0, a0, a1
; RV64I-NEXT: mul a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh2add_extra_sext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a1
-; RV64B-NEXT: sllw a1, a2, a0
-; RV64B-NEXT: sraiw a0, a0, 2
-; RV64B-NEXT: mul a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh2add_extra_sext:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a1
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul6:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a0, a0
-; RV64B-NEXT: sh1add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul6:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a0
-; RV64B-NEXT: sh1add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul10:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul12:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a0, a0
-; RV64B-NEXT: sh2add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul12:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul18:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: sh1add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul18:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul20:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a0
-; RV64B-NEXT: sh2add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul20:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul24:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a0, a0
-; RV64B-NEXT: sh3add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul24:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul36:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: sh2add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul36:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul40:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a0
-; RV64B-NEXT: sh3add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul40:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addmul72:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: sh3add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addmul72:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul96:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a0, a0
-; RV64B-NEXT: slli a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul96:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul160:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a0
-; RV64B-NEXT: slli a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul160:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul288:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: slli a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul288:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: addi a0, a0, 5
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh1add_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a0, a0, 1
-; RV64B-NEXT: addi a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh1add_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 1
; RV64I-NEXT: addi a0, a0, -6
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh2add_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a0, a0, 2
-; RV64B-NEXT: addi a0, a0, -6
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh2add_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 2
; RV64I-NEXT: ori a0, a0, 7
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh3add_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a0, a0, 3
-; RV64B-NEXT: ori a0, a0, 7
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh3add_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 3
; RV64I-NEXT: addi a0, a0, 11
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh1adduw_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli.uw a0, a0, 1
-; RV64B-NEXT: addi a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh1adduw_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 1
; RV64I-NEXT: addi a0, a0, -12
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh2adduw_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli.uw a0, a0, 2
-; RV64B-NEXT: addi a0, a0, -12
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh2adduw_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 2
; RV64I-NEXT: addi a0, a0, 13
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sh3adduw_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli.uw a0, a0, 3
-; RV64B-NEXT: addi a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: sh3adduw_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli.uw a0, a0, 3
; RV64I-NEXT: addi a0, a0, 5
; RV64I-NEXT: ret
;
-; RV64B-LABEL: adduw_imm:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.w a0, a0
-; RV64B-NEXT: addi a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: adduw_imm:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: zext.w a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul258:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, 258
-; RV64B-NEXT: mul a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul258:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 258
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul260:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, 260
-; RV64B-NEXT: mul a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul260:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 260
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul264:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, 264
-; RV64B-NEXT: mul a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul264:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 264
; RV64I-NEXT: addi a0, a0, -2
; RV64I-NEXT: ret
;
-; RV64B-LABEL: imm_zextw:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a0, zero, -2
-; RV64B-NEXT: zext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: imm_zextw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a0, zero, -2
; RV64I-NEXT: addi a0, a0, -1366
; RV64I-NEXT: ret
;
-; RV64B-LABEL: imm_zextw2:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lui a0, 699051
-; RV64B-NEXT: addiw a0, a0, -1366
-; RV64B-NEXT: zext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: imm_zextw2:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: lui a0, 699051
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a1, a0, a0
-; RV64B-NEXT: sh1add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul11:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul19:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a1, a0, a0
-; RV64B-NEXT: sh1add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul19:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul13:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a1, a0, a0
-; RV64B-NEXT: sh2add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul13:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul21:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a1, a0, a0
-; RV64B-NEXT: sh2add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul21:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul37:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a1, a0, a0
-; RV64B-NEXT: sh2add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul37:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul25:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a1, a0, a0
-; RV64B-NEXT: sh3add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul25:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul41:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a1, a0, a0
-; RV64B-NEXT: sh3add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul41:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul73:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a1, a0, a0
-; RV64B-NEXT: sh3add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul73:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a1, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul27:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: sh1add a0, a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul27:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul45:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: sh2add a0, a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul45:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul81:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul81:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul4098:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a1, a0, 12
-; RV64B-NEXT: sh1add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul4098:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a1, a0, 12
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul4100:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a1, a0, 12
-; RV64B-NEXT: sh2add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul4100:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a1, a0, 12
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mul4104:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a1, a0, 12
-; RV64B-NEXT: sh3add a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mul4104:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a1, a0, 12
; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mulw192:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a0, a0
-; RV64B-NEXT: slliw a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mulw192:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mulw320:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a0, a0
-; RV64B-NEXT: slliw a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mulw320:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: mulw576:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a0, a0
-; RV64B-NEXT: slliw a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: mulw576:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: add4104:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, 1026
-; RV64B-NEXT: sh2add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: add4104:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: add8208:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, 1026
-; RV64B-NEXT: sh3add a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: add8208:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addshl32_5_6:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a1, a0
-; RV64B-NEXT: slliw a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addshl32_5_6:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addshl64_5_6:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh1add a0, a1, a0
-; RV64B-NEXT: slli a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addshl64_5_6:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addshl32_5_7:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a1, a0
-; RV64B-NEXT: slliw a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addshl32_5_7:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addshl64_5_7:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh2add a0, a1, a0
-; RV64B-NEXT: slli a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addshl64_5_7:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addshl32_5_8:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a1, a0
-; RV64B-NEXT: slliw a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addshl32_5_8:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: addshl64_5_8:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sh3add a0, a1, a0
-; RV64B-NEXT: slli a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBA-LABEL: addshl64_5_8:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: sh3add a0, a1, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBB
declare i32 @llvm.riscv.orc.b.i32(i32)
define signext i32 @orcb32(i32 signext %a) nounwind {
-; RV64B-LABEL: orcb32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 7
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: orcb32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orc.b a0, a0
declare i64 @llvm.riscv.orc.b.i64(i64)
define i64 @orcb64(i64 %a) nounwind {
-; RV64B-LABEL: orcb64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: orcb64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orc.b a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBB
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: andn_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andn a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: andn_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andn a0, a0, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: andn_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andn a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: andn_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andn a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: orn_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orn a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: orn_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orn a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: orn_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orn a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: orn_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: orn a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: xnor_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xnor a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: xnor_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: xnor a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: xnor_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xnor a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: xnor_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: xnor a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rol_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rolw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rol_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rolw a0, a0, a1
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rol_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rolw a0, a0, a1
-; RV64B-NEXT: sw a0, 0(a2)
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rol_i32_nosext:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rolw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rol_i32_neg_constant_rhs:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, -2
-; RV64B-NEXT: rolw a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rol_i32_neg_constant_rhs:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi a1, zero, -2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rol_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rol a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rol_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rol a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ror_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rorw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ror_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rorw a0, a0, a1
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ror_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rorw a0, a0, a1
-; RV64B-NEXT: sw a0, 0(a2)
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ror_i32_nosext:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rorw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ror_i32_neg_constant_rhs:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, -2
-; RV64B-NEXT: rorw a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ror_i32_neg_constant_rhs:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi a1, zero, -2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ror_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ror a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ror_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ror a0, a0, a1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rori_i32_fshl:
-; RV64B: # %bb.0:
-; RV64B-NEXT: roriw a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rori_i32_fshl:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 1
; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rori_i32_fshl_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: roriw a0, a0, 1
-; RV64B-NEXT: sw a0, 0(a1)
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rori_i32_fshl_nosext:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rori_i32_fshr:
-; RV64B: # %bb.0:
-; RV64B-NEXT: roriw a0, a0, 31
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rori_i32_fshr:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 31
; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rori_i32_fshr_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: roriw a0, a0, 31
-; RV64B-NEXT: sw a0, 0(a1)
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rori_i32_fshr_nosext:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: roriw a0, a0, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: not_rori_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slliw a0, a0, 31
-; RV64B-NEXT: srliw a1, a1, 1
-; RV64B-NEXT: or a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: not_rori_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slliw a0, a0, 31
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: roriw_bug:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slli a1, a0, 31
-; RV64B-NEXT: andi a0, a0, -2
-; RV64B-NEXT: srli a2, a0, 1
-; RV64B-NEXT: or a1, a1, a2
-; RV64B-NEXT: sext.w a1, a1
-; RV64B-NEXT: xor a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: roriw_bug:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a1, a0, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rori_i64_fshl:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rori a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rori_i64_fshl:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rori a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: rori_i64_fshr:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rori a0, a0, 63
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: rori_i64_fshr:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rori a0, a0, 63
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
;
-; RV64B-LABEL: srli_i8:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a0, a0, 192
-; RV64B-NEXT: srli a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: srli_i8:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: andi a0, a0, 192
; RV64I-NEXT: srai a0, a0, 61
; RV64I-NEXT: ret
;
-; RV64B-LABEL: srai_i8:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.b a0, a0
-; RV64B-NEXT: srai a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: srai_i8:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.b a0, a0
; RV64I-NEXT: srli a0, a0, 54
; RV64I-NEXT: ret
;
-; RV64B-LABEL: srli_i16:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.h a0, a0
-; RV64B-NEXT: srli a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: srli_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a0, a0
; RV64I-NEXT: srai a0, a0, 57
; RV64I-NEXT: ret
;
-; RV64B-LABEL: srai_i16:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.h a0, a0
-; RV64B-NEXT: srai a0, a0, 9
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: srai_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.h a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBB
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ctlz_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clzw a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ctlz_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clzw a0, a0
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: log2_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clzw a0, a0
-; RV64B-NEXT: addi a1, zero, 31
-; RV64B-NEXT: sub a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: log2_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clzw a0, a0
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: log2_ceil_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addiw a0, a0, -1
-; RV64B-NEXT: clzw a0, a0
-; RV64B-NEXT: addi a1, zero, 32
-; RV64B-NEXT: sub a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: log2_ceil_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: findLastSet_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clzw a1, a0
-; RV64B-NEXT: xori a1, a1, 31
-; RV64B-NEXT: addi a2, zero, -1
-; RV64B-NEXT: cmov a0, a0, a1, a2
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: findLastSet_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ctlz_lshr_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: srliw a0, a0, 1
-; RV64B-NEXT: clzw a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ctlz_lshr_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srliw a0, a0, 1
; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ctlz_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clz a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ctlz_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clz a0, a0
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cttz_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ctzw a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: cttz_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cttz_zero_undef_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ctzw a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: cttz_zero_undef_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctzw a0, a0
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: findFirstSet_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ctzw a1, a0
-; RV64B-NEXT: addi a2, zero, -1
-; RV64B-NEXT: cmov a0, a0, a1, a2
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: findFirstSet_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ffs_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ctzw a1, a0
-; RV64B-NEXT: addi a1, a1, 1
-; RV64B-NEXT: cmov a0, a0, a1, zero
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ffs_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cttz_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ctz a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: cttz_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ctz a0, a0
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ctpop_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: cpopw a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ctpop_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: cpopw a0, a0
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ctpop_i32_load:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lwu a0, 0(a0)
-; RV64B-NEXT: cpopw a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ctpop_i32_load:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lwu a0, 0(a0)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64B-LABEL: ctpop_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: cpop a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: ctpop_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: cpop a0, a0
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sextb_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: sextb_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.b a0, a0
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sextb_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: sextb_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.b a0, a0
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sexth_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: sexth_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.h a0, a0
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sexth_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: sexth_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.h a0, a0
; RV64I-NEXT: .LBB18_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: min_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: min a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: min_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: min a0, a0, a1
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: min_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: min a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: min_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: min a0, a0, a1
; RV64I-NEXT: .LBB20_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: max_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: max a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: max_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: max a0, a0, a1
; RV64I-NEXT: .LBB21_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: max_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: max a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: max_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: max a0, a0, a1
; RV64I-NEXT: .LBB22_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: minu_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: minu a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: minu_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: minu a0, a0, a1
; RV64I-NEXT: .LBB23_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: minu_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: minu a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: minu_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: minu a0, a0, a1
; RV64I-NEXT: .LBB24_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: maxu_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: maxu a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: maxu_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: maxu a0, a0, a1
; RV64I-NEXT: .LBB25_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: maxu_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: maxu a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: maxu_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: maxu a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: abs_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sext.w a0, a0
-; RV64B-NEXT: neg a1, a0
-; RV64B-NEXT: max a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: abs_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: sext.w a0, a0
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: abs_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: neg a1, a0
-; RV64B-NEXT: max a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: abs_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: zexth_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: zexth_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: zexth_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: zexth_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 24
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: bswap_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 24
-; RV64B-NEXT: sw a0, 0(a1)
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: bswap_i32_nosext:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev8 a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBB-LABEL: bswap_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBC
declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
define i64 @clmul64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: clmul64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clmul a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBC-LABEL: clmul64:
; RV64ZBC: # %bb.0:
; RV64ZBC-NEXT: clmul a0, a0, a1
declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
define i64 @clmul64h(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: clmul64h:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clmulh a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBC-LABEL: clmul64h:
; RV64ZBC: # %bb.0:
; RV64ZBC-NEXT: clmulh a0, a0, a1
declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
define i64 @clmul64r(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: clmul64r:
-; RV64B: # %bb.0:
-; RV64B-NEXT: clmulr a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBC-LABEL: clmul64r:
; RV64ZBC: # %bb.0:
; RV64ZBC-NEXT: clmulr a0, a0, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBE
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
-; RV64B-LABEL: bcompress32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bcompressw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBE-LABEL: bcompress32:
; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bcompressw a0, a0, a1
}
define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
-; RV64B-LABEL: bcompress32_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add a0, a0, a1
-; RV64B-NEXT: add a1, a2, a3
-; RV64B-NEXT: bcompressw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBE-LABEL: bcompress32_demandedbits:
; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: add a0, a0, a1
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
-; RV64B-LABEL: bdecompress32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bdecompressw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBE-LABEL: bdecompress32:
; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bdecompressw a0, a0, a1
}
define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
-; RV64B-LABEL: bdecompress32_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add a0, a0, a1
-; RV64B-NEXT: add a1, a2, a3
-; RV64B-NEXT: bdecompressw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBE-LABEL: bdecompress32_demandedbits:
; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: add a0, a0, a1
declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
define i64 @bcompress64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: bcompress64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bcompress a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBE-LABEL: bcompress64:
; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bcompress a0, a0, a1
declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: bdecompress64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bdecompress a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBE-LABEL: bdecompress64:
; RV64ZBE: # %bb.0:
; RV64ZBE-NEXT: bdecompress a0, a0, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBP
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
define signext i32 @grev32(i32 signext %a, i32 signext %b) nounwind {
-; RV64B-LABEL: grev32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: grevw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevw a0, a0, a1
}
define signext i32 @grev32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
-; RV64B-LABEL: grev32_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add a0, a0, a1
-; RV64B-NEXT: grevw a0, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev32_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1
declare i32 @llvm.riscv.grevi.i32(i32 %a)
define signext i32 @grevi32(i32 signext %a) nounwind {
-; RV64B-LABEL: grevi32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grevi32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 13
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define signext i32 @gorc32(i32 signext %a, i32 signext %b) nounwind {
-; RV64B-LABEL: gorc32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorcw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorcw a0, a0, a1
}
define signext i32 @gorc32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
-; RV64B-LABEL: gorc32_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add a0, a0, a1
-; RV64B-NEXT: gorcw a0, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc32_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1
}
define signext i32 @gorci32(i32 signext %a) nounwind {
-; RV64B-LABEL: gorci32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorci32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 13
declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
define signext i32 @shfl32(i32 signext %a, i32 signext %b) nounwind {
-; RV64B-LABEL: shfl32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: shflw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shflw a0, a0, a1
}
define signext i32 @shfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
-; RV64B-LABEL: shfl32_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add a0, a0, a1
-; RV64B-NEXT: shflw a0, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl32_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1
}
define signext i32 @shfli32(i32 signext %a) nounwind {
-; RV64B-LABEL: shfli32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: shfli a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfli32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfli a0, a0, 13
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
-; RV64B-LABEL: unshfl32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: unshflw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: unshfl32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshflw a0, a0, a1
}
define signext i32 @unshfl32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
-; RV64B-LABEL: unshfl32_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: add a0, a0, a1
-; RV64B-NEXT: unshflw a0, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: unshfl32_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: add a0, a0, a1
}
define signext i32 @unshfli32(i32 signext %a) nounwind {
-; RV64B-LABEL: unshfli32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: unshfli a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: unshfli32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfli a0, a0, 13
declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
define i64 @grev64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: grev64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: grev a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grev a0, a0, a1
}
define i64 @grev64_demandedbits(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: grev64_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: grev a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev64_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grev a0, a0, a1
}
define i64 @grevi64(i64 %a) nounwind {
-; RV64B-LABEL: grevi64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: grevi a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grevi64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevi a0, a0, 13
declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
define i64 @gorc64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: gorc64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorc a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorc a0, a0, a1
}
define i64 @gorc64_demandedbits(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: gorc64_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorc a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc64_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorc a0, a0, a1
declare i64 @llvm.riscv.gorci.i64(i64 %a)
define i64 @gorci64(i64 %a) nounwind {
-; RV64B-LABEL: gorci64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorci a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorci64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorci a0, a0, 13
declare i64 @llvm.riscv.shfl.i64(i64 %a, i64 %b)
define i64 @shfl64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: shfl64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: shfl a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfl a0, a0, a1
}
define i64 @shfl64_demandedbits(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: shfl64_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: shfl a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl64_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfl a0, a0, a1
}
define i64 @shfli64(i64 %a) nounwind {
-; RV64B-LABEL: shfli64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: shfli a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfli64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: shfli a0, a0, 13
declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
define i64 @unshfl64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: unshfl64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: unshfl a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: unshfl64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfl a0, a0, a1
}
define i64 @unshfl64_demandedbits(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: unshfl64_demandedbits:
-; RV64B: # %bb.0:
-; RV64B-NEXT: unshfl a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: unshfl64_demandedbits:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfl a0, a0, a1
}
define i64 @unshfli64(i64 %a) nounwind {
-; RV64B-LABEL: unshfli64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: unshfli a0, a0, 13
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: unshfli64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unshfli a0, a0, 13
declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
define i64 @xpermn64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: xpermn64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xperm.n a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: xpermn64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.n a0, a0, a1
declare i64 @llvm.riscv.xperm.b.i64(i64 %a, i64 %b)
define i64 @xpermb64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: xpermb64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xperm.b a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: xpermb64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.b a0, a0, a1
declare i64 @llvm.riscv.xperm.h.i64(i64 %a, i64 %b)
define i64 @xpermh64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: xpermh64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xperm.h a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: xpermh64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.h a0, a0, a1
declare i64 @llvm.riscv.xperm.w.i64(i64 %a, i64 %b)
define i64 @xpermw64(i64 %a, i64 %b) nounwind {
-; RV64B-LABEL: xpermw64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xperm.w a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: xpermw64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: xperm.w a0, a0, a1
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBP
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc1_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc1_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc1_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc.p a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc1_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.p a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc2_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc2_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc2_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc2.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc2_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.n a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc3_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 3
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc3_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc3_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc3_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.n a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc4_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 4
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc4_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc4_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc4.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc4_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc4.b a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc5_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc5_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 5
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc5_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorci a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc5_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorci a0, a0, 5
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc6_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc6_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 6
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc6_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc2.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc6_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.b a0, a0
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc7_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 7
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc7_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 7
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc7_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc7_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.b a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc8_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 8
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc8_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc8_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc8.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc8_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc8.h a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc16_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc16_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 16
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc16_rotl_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc16_rotl_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 16
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc16_rotr_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc16_rotr_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc16_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc16.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc16_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc16.w a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc32 a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc2b_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc2b_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc2b_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc2.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc2b_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc2.n a0, a0
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc3b_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: gorciw a0, a0, 3
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc3b_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: gorciw a0, a0, 3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc3b_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc3b_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc.n a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc32_rotl:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc32 a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc32_rotl:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: gorc32_rotr:
-; RV64B: # %bb.0:
-; RV64B-NEXT: orc32 a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: gorc32_rotr:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: orc32 a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev1_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev1_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev1_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev.p a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev1_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.p a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev2_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev2_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev2_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev2.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev2_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.n a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev3_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 3
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev3_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev3_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev3_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.n a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev4_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 4
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev4_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev4_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev4.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev4_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev4.b a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev5_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev5_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 5
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev5_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: grevi a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev5_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: grevi a0, a0, 5
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev6_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 6
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev6_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 6
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev6_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev2.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev6_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.b a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev7_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 7
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev7_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev7_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev7_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.b a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev8_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 8
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev8_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev8_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev8.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev8_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev8.h a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev16_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev16_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev16_i32_fshl:
-; RV64B: # %bb.0:
-; RV64B-NEXT: roriw a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev16_i32_fshl:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev16_i32_fshr:
-; RV64B: # %bb.0:
-; RV64B-NEXT: roriw a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev16_i32_fshr:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: roriw a0, a0, 16
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev16_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev16.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev16_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev16.w a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rori a0, a0, 32
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 32
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev3b_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 3
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev3b_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev3b_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev3b_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.n a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev2b_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 2
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev2b_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev2b_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev2.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev2b_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev2.n a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev0_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev0_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: ret
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev0_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev0_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: ret
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev32_fshl:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rori a0, a0, 32
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev32_fshl:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: grev32_fshr:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rori a0, a0, 32
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: grev32_fshr:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rori a0, a0, 32
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i16:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 8
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bswap_i16:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 24
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bswap_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 24
; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 24
-; RV64B-NEXT: sw a0, 0(a1)
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bswap_i32_nosext:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 24
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev8 a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bswap_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev8 a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_i8:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 7
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_i8:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_i16:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 15
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_i16:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 15
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 31
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 31
; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 31
-; RV64B-NEXT: sw a0, 0(a1)
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_i32_nosext:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 31
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_rotr_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 8
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bswap_rotr_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bswap_rotl_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 8
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bswap_rotl_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_bswap_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: greviw a0, a0, 7
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_bswap_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: greviw a0, a0, 7
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret
;
-; RV64B-LABEL: bitreverse_bswap_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: rev.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: bitreverse_bswap_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: rev.b a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl1_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl1_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip.n a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl1_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip.n a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl1_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip.n a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl2_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip2.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl2_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip2.b a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl2_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip2.b a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl2_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip2.b a0, a0
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl4_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip4.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl4_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip4.h a0, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl4_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip4.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl4_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip4.h a0, a0
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl8_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip8.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl8_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip8.w a0, a0
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl8_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip8.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl8_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip8.w a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: shfl16:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zip16 a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: shfl16:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip16 a0, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: pack_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: packw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: pack_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packw a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: pack_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: pack a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: pack_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: pack a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: packu_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: packuw a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: packu_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packuw a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: packu_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: packu a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: packu_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packu a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: packh_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: packh a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: packh_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packh a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: packh_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: packh a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: packh_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: packh a0, a0, a1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: zexth_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: zexth_i32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zext.h a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: zexth_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: zext.h a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBP-LABEL: zexth_i64:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zext.h a0, a0
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBS
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclr_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: andn a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclr_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclr_i32_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: andn a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclr_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclr_i32_load:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lw a0, 0(a0)
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: andn a0, a0, a1
-; RV64B-NEXT: sext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclr_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclr_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclr a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclr_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclr_i64_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclr a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclr_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: or a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i32_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: or a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i32_load:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lw a0, 0(a0)
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: or a0, a1, a0
-; RV64B-NEXT: sext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i32_zero:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a1, zero, 1
-; RV64B-NEXT: sllw a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i32_zero:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a1, zero, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bset a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i64_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bset a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbset_i64_zero:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bset a0, zero, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbset_i64_zero:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinv_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: xor a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinv_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinv_i32_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: xor a0, a1, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinv_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi a2, zero, 1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinv_i32_load:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lw a0, 0(a0)
-; RV64B-NEXT: addi a2, zero, 1
-; RV64B-NEXT: sllw a1, a2, a1
-; RV64B-NEXT: xor a0, a1, a0
-; RV64B-NEXT: sext.w a0, a0
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinv_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinv_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binv a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinv_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinv_i64_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binv a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinv_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbext_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: srlw a0, a0, a1
-; RV64B-NEXT: andi a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbext_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbext_i32_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: srlw a0, a0, a1
-; RV64B-NEXT: andi a0, a0, 1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbext_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbext_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bext a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbext_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbext_i64_no_mask:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bext a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbext_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbexti_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bexti a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbexti_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbexti_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bexti a0, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbexti_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64I-NEXT: andi a0, a0, -1025
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i32_10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a0, a0, -1025
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i32_10:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -1025
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i32_11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i32_30:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 30
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i32_31:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lui a1, 524288
-; RV64B-NEXT: addiw a1, a1, -1
-; RV64B-NEXT: and a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i32_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 524288
; RV64I-NEXT: andi a0, a0, -1025
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a0, a0, -1025
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_10:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -1025
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_30:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 30
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_31:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 31
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 31
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_62:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 62
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 62
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_63:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 63
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 63
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_large0:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a0, a0, -256
-; RV64B-NEXT: bclri a0, a0, 24
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_large0:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -256
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbclri_i64_large1:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bclri a0, a0, 16
-; RV64B-NEXT: bclri a0, a0, 24
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbclri_i64_large1:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 16
; RV64I-NEXT: ori a0, a0, 1024
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i32_10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ori a0, a0, 1024
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i32_10:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1024
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i32_11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i32_30:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 30
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i32_31:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lui a1, 524288
-; RV64B-NEXT: or a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i32_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 524288
; RV64I-NEXT: ori a0, a0, 1024
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i64_10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ori a0, a0, 1024
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i64_10:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1024
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i64_11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i64_30:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 30
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i64_31:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 31
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i64_62:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 62
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 62
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbseti_i64_63:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 63
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbseti_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 63
; RV64I-NEXT: xori a0, a0, 1024
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i32_10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xori a0, a0, 1024
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i32_10:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1024
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i32_11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i32_30:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 30
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i32_31:
-; RV64B: # %bb.0:
-; RV64B-NEXT: lui a1, 524288
-; RV64B-NEXT: xor a0, a0, a1
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i32_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 524288
; RV64I-NEXT: xori a0, a0, 1024
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i64_10:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xori a0, a0, 1024
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i64_10:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1024
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i64_11:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 11
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i64_30:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 30
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i64_31:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 31
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 31
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i64_62:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 62
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 62
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: sbinvi_i64_63:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 63
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: sbinvi_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: xor_i64_large:
-; RV64B: # %bb.0:
-; RV64B-NEXT: binvi a0, a0, 0
-; RV64B-NEXT: binvi a0, a0, 32
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: xor_i64_large:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 0
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: xor_i64_4099:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xori a0, a0, 3
-; RV64B-NEXT: binvi a0, a0, 12
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: xor_i64_4099:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 3
; RV64I-NEXT: xori a0, a0, 96
; RV64I-NEXT: ret
;
-; RV64B-LABEL: xor_i64_96:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xori a0, a0, 96
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: xor_i64_96:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 96
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: or_i64_large:
-; RV64B: # %bb.0:
-; RV64B-NEXT: bseti a0, a0, 0
-; RV64B-NEXT: bseti a0, a0, 32
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: or_i64_large:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 0
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: xor_i64_66901:
-; RV64B: # %bb.0:
-; RV64B-NEXT: xori a0, a0, 1365
-; RV64B-NEXT: binvi a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: xor_i64_66901:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1365
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: or_i64_4099:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ori a0, a0, 3
-; RV64B-NEXT: bseti a0, a0, 12
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: or_i64_4099:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 3
; RV64I-NEXT: ori a0, a0, 96
; RV64I-NEXT: ret
;
-; RV64B-LABEL: or_i64_96:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ori a0, a0, 96
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: or_i64_96:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 96
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: or_i64_66901:
-; RV64B: # %bb.0:
-; RV64B-NEXT: ori a0, a0, 1365
-; RV64B-NEXT: bseti a0, a0, 16
-; RV64B-NEXT: ret
-;
; RV64ZBS-LABEL: or_i64_66901:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1365
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64B
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBT
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmix_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: cmix a0, a1, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmix_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmix_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: cmix a0, a1, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmix_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmix a0, a1, a0, a2
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: cmov a0, a1, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_sle_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slt a1, a2, a1
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_sle_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_sge_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slt a1, a1, a2
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_sge_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_ule_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sltu a1, a2, a1
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_ule_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_uge_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sltu a1, a1, a2
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_uge_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: cmov a0, a1, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: cmov a0, a1, a0, a2
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_sle_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slt a1, a2, a1
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_sle_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a2, a1
; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_sge_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: slt a1, a1, a2
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_sge_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: slt a1, a1, a2
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_ule_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sltu a1, a2, a1
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_ule_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a2, a1
; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: ret
;
-; RV64B-LABEL: cmov_uge_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: sltu a1, a1, a2
-; RV64B-NEXT: cmov a0, a1, a3, a0
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: cmov_uge_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: sltu a1, a1, a2
; RV64I-NEXT: srai a0, a0, 32
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshl_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a2, a2, 31
-; RV64B-NEXT: fslw a0, a0, a1, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshl_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31
; RV64I-NEXT: sw a0, 0(a3)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshl_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a2, a2, 31
-; RV64B-NEXT: fslw a0, a0, a1, a2
-; RV64B-NEXT: sw a0, 0(a3)
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshl_i32_nosext:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshl_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a2, a2, 63
-; RV64B-NEXT: fsl a0, a0, a1, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshl_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 63
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshr_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a2, a2, 31
-; RV64B-NEXT: fsrw a0, a1, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshr_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31
; RV64I-NEXT: sw a0, 0(a3)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshr_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a2, a2, 31
-; RV64B-NEXT: fsrw a0, a1, a0, a2
-; RV64B-NEXT: sw a0, 0(a3)
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshr_i32_nosext:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshr_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: andi a2, a2, 63
-; RV64B-NEXT: fsr a0, a1, a0, a2
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshr_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: andi a2, a2, 63
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshri_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: fsriw a0, a1, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshri_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 5
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshri_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: fsriw a0, a1, a0, 5
-; RV64B-NEXT: sw a0, 0(a2)
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshri_i32_nosext:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 5
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshri_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: fsri a0, a1, a0, 5
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshri_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsri a0, a1, a0, 5
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshli_i32:
-; RV64B: # %bb.0:
-; RV64B-NEXT: fsriw a0, a1, a0, 27
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshli_i32:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshli_i32_nosext:
-; RV64B: # %bb.0:
-; RV64B-NEXT: fsriw a0, a1, a0, 27
-; RV64B-NEXT: sw a0, 0(a2)
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshli_i32_nosext:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsriw a0, a1, a0, 27
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV64B-LABEL: fshli_i64:
-; RV64B: # %bb.0:
-; RV64B-NEXT: fsri a0, a1, a0, 59
-; RV64B-NEXT: ret
-;
; RV64ZBT-LABEL: fshli_i64:
; RV64ZBT: # %bb.0:
; RV64ZBT-NEXT: fsri a0, a1, a0, 59
.attribute arch, "rv32ima2p_fdc"
# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
-.attribute arch, "rv32ib"
-# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-
.attribute arch, "rv32iv"
# CHECK: attribute 5, "rv32i2p0_v0p10"
+++ /dev/null
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -riscv-no-aliases \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-b - \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
-
-# The following check prefixes are used in this test:
-# CHECK-S-OBJ Match both the .s and objdumped object output with
-# aliases enabled
-# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
-# aliases disabled
-
-# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
-# CHECK-S-OBJ: andi t0, t1, 255
-zext.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
-# CHECK-S-OBJ: zext.h t0, t1
-zext.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
-# CHECK-S-OBJ: rev.p t0, t1
-rev.p x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
-# CHECK-S-OBJ: rev2.n t0, t1
-rev2.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
-# CHECK-S-OBJ: rev.n t0, t1
-rev.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
-# CHECK-S-OBJ: rev4.b t0, t1
-rev4.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
-# CHECK-S-OBJ: rev2.b t0, t1
-rev2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
-# CHECK-S-OBJ: rev.b t0, t1
-rev.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
-# CHECK-S-OBJ: rev8.h t0, t1
-rev8.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
-# CHECK-S-OBJ: rev4.h t0, t1
-rev4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
-# CHECK-S-OBJ: rev2.h t0, t1
-rev2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
-# CHECK-S-OBJ: rev.h t0, t1
-rev.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
-# CHECK-S-OBJ: rev16 t0, t1
-rev16 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
-# CHECK-S-OBJ: rev8 t0, t1
-rev8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
-# CHECK-S-OBJ: rev4 t0, t1
-rev4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
-# CHECK-S-OBJ: rev2 t0, t1
-rev2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
-# CHECK-S-OBJ: rev t0, t1
-rev x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1
-# CHECK-S-OBJ: zip.n t0, t1
-zip.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1
-# CHECK-S-OBJ: unzip.n t0, t1
-unzip.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2
-# CHECK-S-OBJ: zip2.b t0, t1
-zip2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2
-# CHECK-S-OBJ: unzip2.b t0, t1
-unzip2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3
-# CHECK-S-OBJ: zip.b t0, t1
-zip.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3
-# CHECK-S-OBJ: unzip.b t0, t1
-unzip.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
-# CHECK-S-OBJ: zip4.h t0, t1
-zip4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
-# CHECK-S-OBJ: unzip4.h t0, t1
-unzip4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6
-# CHECK-S-OBJ: zip2.h t0, t1
-zip2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6
-# CHECK-S-OBJ: unzip2.h t0, t1
-unzip2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7
-# CHECK-S-OBJ: zip.h t0, t1
-zip.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7
-# CHECK-S-OBJ: unzip.h t0, t1
-unzip.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8
-# CHECK-S-OBJ: zip8 t0, t1
-zip8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8
-# CHECK-S-OBJ: unzip8 t0, t1
-unzip8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12
-# CHECK-S-OBJ: zip4 t0, t1
-zip4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12
-# CHECK-S-OBJ: unzip4 t0, t1
-unzip4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14
-# CHECK-S-OBJ: zip2 t0, t1
-zip2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14
-# CHECK-S-OBJ: unzip2 t0, t1
-unzip2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
-# CHECK-S-OBJ: zip t0, t1
-zip x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
-# CHECK-S-OBJ: unzip t0, t1
-unzip x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
-# CHECK-S-OBJ: orc.p t0, t1
-orc.p x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2
-# CHECK-S-OBJ: orc2.n t0, t1
-orc2.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3
-# CHECK-S-OBJ: orc.n t0, t1
-orc.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
-# CHECK-S-OBJ: orc4.b t0, t1
-orc4.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6
-# CHECK-S-OBJ: orc2.b t0, t1
-orc2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
-# CHECK-S-OBJ: orc.b t0, t1
-orc.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8
-# CHECK-S-OBJ: orc8.h t0, t1
-orc8.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12
-# CHECK-S-OBJ: orc4.h t0, t1
-orc4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14
-# CHECK-S-OBJ: orc2.h t0, t1
-orc2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15
-# CHECK-S-OBJ: orc.h t0, t1
-orc.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16
-# CHECK-S-OBJ: orc16 t0, t1
-orc16 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24
-# CHECK-S-OBJ: orc8 t0, t1
-orc8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28
-# CHECK-S-OBJ: orc4 t0, t1
-orc4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30
-# CHECK-S-OBJ: orc2 t0, t1
-orc2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
-# CHECK-S-OBJ: orc t0, t1
-orc x5, x6
-
-# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
-# CHECK-S-OBJ: rori t0, t1, 8
-ror x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
-# CHECK-S-OBJ: bseti t0, t1, 8
-bset x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
-# CHECK-S-OBJ: bclri t0, t1, 8
-bclr x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
-# CHECK-S-OBJ: binvi t0, t1, 8
-binv x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
-# CHECK-S-OBJ: bexti t0, t1, 8
-bext x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
-# CHECK-S-OBJ: grevi t0, t1, 13
-grev x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
-# CHECK-S-OBJ: gorci t0, t1, 13
-gorc x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
-# CHECK-S-OBJ: shfli t0, t1, 13
-shfl x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
-# CHECK-S-OBJ: unshfli t0, t1, 13
-unshfl x5, x6, 13
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbb < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbb - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbb < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbb - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
+# CHECK-S-OBJ: zext.h t0, t1
+zext.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
+# CHECK-S-OBJ: orc.b t0, t1
+orc.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
+# CHECK-S-OBJ: rori t0, t1, 8
+ror x5, x6, 8
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip carry-less multiply extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip extract/deposit extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbe -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bit-Field extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbf -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbp < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbp - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbp < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbp - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
+# CHECK-S-OBJ: zext.h t0, t1
+zext.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
+# CHECK-S-OBJ: rev.p t0, t1
+rev.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
+# CHECK-S-OBJ: rev2.n t0, t1
+rev2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
+# CHECK-S-OBJ: rev.n t0, t1
+rev.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: rev4.b t0, t1
+rev4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
+# CHECK-S-OBJ: rev2.b t0, t1
+rev2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ: rev.b t0, t1
+rev.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
+# CHECK-S-OBJ: rev4.h t0, t1
+rev4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
+# CHECK-S-OBJ: rev2.h t0, t1
+rev2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
+# CHECK-S-OBJ: rev.h t0, t1
+rev.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
+# CHECK-S-OBJ: rev16 t0, t1
+rev16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
+# CHECK-S-OBJ: rev4 t0, t1
+rev4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
+# CHECK-S-OBJ: rev2 t0, t1
+rev2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1
+# CHECK-S-OBJ: zip.n t0, t1
+zip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1
+# CHECK-S-OBJ: unzip.n t0, t1
+unzip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2
+# CHECK-S-OBJ: zip2.b t0, t1
+zip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2
+# CHECK-S-OBJ: unzip2.b t0, t1
+unzip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3
+# CHECK-S-OBJ: zip.b t0, t1
+zip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3
+# CHECK-S-OBJ: unzip.b t0, t1
+unzip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: zip4.h t0, t1
+zip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unzip4.h t0, t1
+unzip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6
+# CHECK-S-OBJ: zip2.h t0, t1
+zip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6
+# CHECK-S-OBJ: unzip2.h t0, t1
+unzip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7
+# CHECK-S-OBJ: zip.h t0, t1
+zip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7
+# CHECK-S-OBJ: unzip.h t0, t1
+unzip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8
+# CHECK-S-OBJ: zip8 t0, t1
+zip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8
+# CHECK-S-OBJ: unzip8 t0, t1
+unzip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12
+# CHECK-S-OBJ: zip4 t0, t1
+zip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12
+# CHECK-S-OBJ: unzip4 t0, t1
+unzip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14
+# CHECK-S-OBJ: zip2 t0, t1
+zip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14
+# CHECK-S-OBJ: unzip2 t0, t1
+unzip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
+# CHECK-S-OBJ: zip t0, t1
+zip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
+# CHECK-S-OBJ: unzip t0, t1
+unzip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
+# CHECK-S-OBJ: orc.p t0, t1
+orc.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2
+# CHECK-S-OBJ: orc2.n t0, t1
+orc2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3
+# CHECK-S-OBJ: orc.n t0, t1
+orc.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: orc4.b t0, t1
+orc4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6
+# CHECK-S-OBJ: orc2.b t0, t1
+orc2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
+# CHECK-S-OBJ: orc.b t0, t1
+orc.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8
+# CHECK-S-OBJ: orc8.h t0, t1
+orc8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12
+# CHECK-S-OBJ: orc4.h t0, t1
+orc4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14
+# CHECK-S-OBJ: orc2.h t0, t1
+orc2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15
+# CHECK-S-OBJ: orc.h t0, t1
+orc.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16
+# CHECK-S-OBJ: orc16 t0, t1
+orc16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24
+# CHECK-S-OBJ: orc8 t0, t1
+orc8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28
+# CHECK-S-OBJ: orc4 t0, t1
+orc4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30
+# CHECK-S-OBJ: orc2 t0, t1
+orc2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
+# CHECK-S-OBJ: orc t0, t1
+orc x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
+# CHECK-S-OBJ: rori t0, t1, 8
+ror x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefix=CHECK-ASM %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-OBJ %s
-
# With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefix=CHECK-ASM %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
-
# With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip CRC extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbs < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbs - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zbs < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbs - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
+# CHECK-S-OBJ: bseti t0, t1, 8
+bset x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
+# CHECK-S-OBJ: bclri t0, t1, 8
+bclr x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
+# CHECK-S-OBJ: binvi t0, t1, 8
+binv x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
+# CHECK-S-OBJ: bexti t0, t1, 8
+bext x5, x6, 8
# Immediate operand out of range
bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
-bclrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-bsetw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-binvw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-bextw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-bclriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-bsetiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-binviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip single bit extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip ternary extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+++ /dev/null
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -riscv-no-aliases \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-b - \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \
-# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
-
-# The following check prefixes are used in this test:
-# CHECK-S-OBJ Match both the .s and objdumped object output with
-# aliases enabled
-# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
-# aliases disabled
-
-# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
-# CHECK-S-OBJ: andi t0, t1, 255
-zext.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
-# CHECK-S-OBJ: zext.h t0, t1
-zext.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: add.uw t0, t1, zero
-# CHECK-S-OBJ: zext.w t0, t1
-zext.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
-# CHECK-S-OBJ: rev.p t0, t1
-rev.p x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
-# CHECK-S-OBJ: rev2.n t0, t1
-rev2.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
-# CHECK-S-OBJ: rev.n t0, t1
-rev.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
-# CHECK-S-OBJ: rev4.b t0, t1
-rev4.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
-# CHECK-S-OBJ: rev2.b t0, t1
-rev2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
-# CHECK-S-OBJ: rev.b t0, t1
-rev.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
-# CHECK-S-OBJ: rev8.h t0, t1
-rev8.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
-# CHECK-S-OBJ: rev4.h t0, t1
-rev4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
-# CHECK-S-OBJ: rev2.h t0, t1
-rev2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
-# CHECK-S-OBJ: rev.h t0, t1
-rev.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
-# CHECK-S-OBJ: rev16.w t0, t1
-rev16.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24
-# CHECK-S-OBJ: rev8.w t0, t1
-rev8.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
-# CHECK-S-OBJ: rev4.w t0, t1
-rev4.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
-# CHECK-S-OBJ: rev2.w t0, t1
-rev2.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
-# CHECK-S-OBJ: rev.w t0, t1
-rev.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 32
-# CHECK-S-OBJ: rev32 t0, t1
-rev32 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 48
-# CHECK-S-OBJ: rev16 t0, t1
-rev16 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
-# CHECK-S-OBJ: rev8 t0, t1
-rev8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 60
-# CHECK-S-OBJ: rev4 t0, t1
-rev4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 62
-# CHECK-S-OBJ: rev2 t0, t1
-rev2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
-# CHECK-S-OBJ: rev t0, t1
-rev x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1
-# CHECK-S-OBJ: zip.n t0, t1
-zip.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1
-# CHECK-S-OBJ: unzip.n t0, t1
-unzip.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2
-# CHECK-S-OBJ: zip2.b t0, t1
-zip2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2
-# CHECK-S-OBJ: unzip2.b t0, t1
-unzip2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3
-# CHECK-S-OBJ: zip.b t0, t1
-zip.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3
-# CHECK-S-OBJ: unzip.b t0, t1
-unzip.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
-# CHECK-S-OBJ: zip4.h t0, t1
-zip4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
-# CHECK-S-OBJ: unzip4.h t0, t1
-unzip4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6
-# CHECK-S-OBJ: zip2.h t0, t1
-zip2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6
-# CHECK-S-OBJ: unzip2.h t0, t1
-unzip2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7
-# CHECK-S-OBJ: zip.h t0, t1
-zip.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7
-# CHECK-S-OBJ: unzip.h t0, t1
-unzip.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8
-# CHECK-S-OBJ: zip8.w t0, t1
-zip8.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8
-# CHECK-S-OBJ: unzip8.w t0, t1
-unzip8.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12
-# CHECK-S-OBJ: zip4.w t0, t1
-zip4.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12
-# CHECK-S-OBJ: unzip4.w t0, t1
-unzip4.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14
-# CHECK-S-OBJ: zip2.w t0, t1
-zip2.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14
-# CHECK-S-OBJ: unzip2.w t0, t1
-unzip2.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
-# CHECK-S-OBJ: zip.w t0, t1
-zip.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
-# CHECK-S-OBJ: unzip.w t0, t1
-unzip.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 16
-# CHECK-S-OBJ: zip16 t0, t1
-zip16 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 16
-# CHECK-S-OBJ: unzip16 t0, t1
-unzip16 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 24
-# CHECK-S-OBJ: zip8 t0, t1
-zip8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 24
-# CHECK-S-OBJ: unzip8 t0, t1
-unzip8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 28
-# CHECK-S-OBJ: zip4 t0, t1
-zip4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 28
-# CHECK-S-OBJ: unzip4 t0, t1
-unzip4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 30
-# CHECK-S-OBJ: zip2 t0, t1
-zip2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 30
-# CHECK-S-OBJ: unzip2 t0, t1
-unzip2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 31
-# CHECK-S-OBJ: zip t0, t1
-zip x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 31
-# CHECK-S-OBJ: unzip t0, t1
-unzip x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
-# CHECK-S-OBJ: orc.p t0, t1
-orc.p x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2
-# CHECK-S-OBJ: orc2.n t0, t1
-orc2.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3
-# CHECK-S-OBJ: orc.n t0, t1
-orc.n x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
-# CHECK-S-OBJ: orc4.b t0, t1
-orc4.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6
-# CHECK-S-OBJ: orc2.b t0, t1
-orc2.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
-# CHECK-S-OBJ: orc.b t0, t1
-orc.b x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8
-# CHECK-S-OBJ: orc8.h t0, t1
-orc8.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12
-# CHECK-S-OBJ: orc4.h t0, t1
-orc4.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14
-# CHECK-S-OBJ: orc2.h t0, t1
-orc2.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15
-# CHECK-S-OBJ: orc.h t0, t1
-orc.h x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16
-# CHECK-S-OBJ: orc16.w t0, t1
-orc16.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24
-# CHECK-S-OBJ: orc8.w t0, t1
-orc8.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28
-# CHECK-S-OBJ: orc4.w t0, t1
-orc4.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30
-# CHECK-S-OBJ: orc2.w t0, t1
-orc2.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
-# CHECK-S-OBJ: orc.w t0, t1
-orc.w x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 32
-# CHECK-S-OBJ: orc32 t0, t1
-orc32 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 48
-# CHECK-S-OBJ: orc16 t0, t1
-orc16 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 56
-# CHECK-S-OBJ: orc8 t0, t1
-orc8 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 60
-# CHECK-S-OBJ: orc4 t0, t1
-orc4 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 62
-# CHECK-S-OBJ: orc2 t0, t1
-orc2 x5, x6
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 63
-# CHECK-S-OBJ: orc t0, t1
-orc x5, x6
-
-# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
-# CHECK-S-OBJ: rori t0, t1, 8
-ror x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8
-# CHECK-S-OBJ: roriw t0, t1, 8
-rorw x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
-# CHECK-S-OBJ: bseti t0, t1, 8
-bset x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
-# CHECK-S-OBJ: bclri t0, t1, 8
-bclr x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
-# CHECK-S-OBJ: binvi t0, t1, 8
-binv x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
-# CHECK-S-OBJ: bexti t0, t1, 8
-bext x5, x6, 8
-
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
-# CHECK-S-OBJ: grevi t0, t1, 13
-grev x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
-# CHECK-S-OBJ: gorci t0, t1, 13
-gorc x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
-# CHECK-S-OBJ: shfli t0, t1, 13
-shfl x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
-# CHECK-S-OBJ: unshfli t0, t1, 13
-unshfl x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
-# CHECK-S-OBJ: greviw t0, t1, 13
-grevw x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
-# CHECK-S-OBJ: gorciw t0, t1, 13
-gorcw x5, x6, 13
-
-# CHECK-S-OBJ-NOALIAS: addi t1, zero, -2
-# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t1, t1, zero
-# CHECK-S-OBJ: addi t1, zero, -2
-# CHECK-S-OBJ-NEXT: zext.w t1, t1
-li x6, 0xfffffffe
-
-# CHECK-S-OBJ-NOALIAS: lui t2, 699051
-# CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366
-# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero
-# CHECK-S-OBJ: lui t2, 699051
-# CHECK-S-OBJ-NEXT: addiw t2, t2, -1366
-# CHECK-S-OBJ-NEXT: zext.w t2, t2
-li x7, 0xaaaaaaaa
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zba < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zba - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zba < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zba - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: add.uw t0, t1, zero
+# CHECK-S-OBJ: zext.w t0, t1
+zext.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: addi t1, zero, -2
+# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t1, t1, zero
+# CHECK-S-OBJ: addi t1, zero, -2
+# CHECK-S-OBJ-NEXT: zext.w t1, t1
+li x6, 0xfffffffe
+
+# CHECK-S-OBJ-NOALIAS: lui t2, 699051
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366
+# CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero
+# CHECK-S-OBJ: lui t2, 699051
+# CHECK-S-OBJ-NEXT: addiw t2, t2, -1366
+# CHECK-S-OBJ-NEXT: zext.w t2, t2
+li x7, 0xaaaaaaaa
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zba -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbb < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbb - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbb < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbb - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
+# CHECK-S-OBJ: zext.h t0, t1
+zext.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
+# CHECK-S-OBJ: orc.b t0, t1
+orc.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
+# CHECK-S-OBJ: rori t0, t1, 8
+ror x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8
+# CHECK-S-OBJ: roriw t0, t1, 8
+rorw x5, x6, 8
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip extract/deposit extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bit-Field extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbf -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip matix extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbm -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbp < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbp - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbp < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbp - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: zext.h t0, t1
+# CHECK-S-OBJ: zext.h t0, t1
+zext.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
+# CHECK-S-OBJ: rev.p t0, t1
+rev.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
+# CHECK-S-OBJ: rev2.n t0, t1
+rev2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
+# CHECK-S-OBJ: rev.n t0, t1
+rev.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: rev4.b t0, t1
+rev4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
+# CHECK-S-OBJ: rev2.b t0, t1
+rev2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ: rev.b t0, t1
+rev.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
+# CHECK-S-OBJ: rev4.h t0, t1
+rev4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
+# CHECK-S-OBJ: rev2.h t0, t1
+rev2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
+# CHECK-S-OBJ: rev.h t0, t1
+rev.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
+# CHECK-S-OBJ: rev16.w t0, t1
+rev16.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24
+# CHECK-S-OBJ: rev8.w t0, t1
+rev8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
+# CHECK-S-OBJ: rev4.w t0, t1
+rev4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
+# CHECK-S-OBJ: rev2.w t0, t1
+rev2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
+# CHECK-S-OBJ: rev.w t0, t1
+rev.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 32
+# CHECK-S-OBJ: rev32 t0, t1
+rev32 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 48
+# CHECK-S-OBJ: rev16 t0, t1
+rev16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rev8 t0, t1
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 60
+# CHECK-S-OBJ: rev4 t0, t1
+rev4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 62
+# CHECK-S-OBJ: rev2 t0, t1
+rev2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1
+# CHECK-S-OBJ: zip.n t0, t1
+zip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1
+# CHECK-S-OBJ: unzip.n t0, t1
+unzip.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2
+# CHECK-S-OBJ: zip2.b t0, t1
+zip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2
+# CHECK-S-OBJ: unzip2.b t0, t1
+unzip2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3
+# CHECK-S-OBJ: zip.b t0, t1
+zip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3
+# CHECK-S-OBJ: unzip.b t0, t1
+unzip.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4
+# CHECK-S-OBJ: zip4.h t0, t1
+zip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4
+# CHECK-S-OBJ: unzip4.h t0, t1
+unzip4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6
+# CHECK-S-OBJ: zip2.h t0, t1
+zip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6
+# CHECK-S-OBJ: unzip2.h t0, t1
+unzip2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7
+# CHECK-S-OBJ: zip.h t0, t1
+zip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7
+# CHECK-S-OBJ: unzip.h t0, t1
+unzip.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8
+# CHECK-S-OBJ: zip8.w t0, t1
+zip8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8
+# CHECK-S-OBJ: unzip8.w t0, t1
+unzip8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12
+# CHECK-S-OBJ: zip4.w t0, t1
+zip4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12
+# CHECK-S-OBJ: unzip4.w t0, t1
+unzip4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14
+# CHECK-S-OBJ: zip2.w t0, t1
+zip2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14
+# CHECK-S-OBJ: unzip2.w t0, t1
+unzip2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
+# CHECK-S-OBJ: zip.w t0, t1
+zip.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
+# CHECK-S-OBJ: unzip.w t0, t1
+unzip.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 16
+# CHECK-S-OBJ: zip16 t0, t1
+zip16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 16
+# CHECK-S-OBJ: unzip16 t0, t1
+unzip16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 24
+# CHECK-S-OBJ: zip8 t0, t1
+zip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 24
+# CHECK-S-OBJ: unzip8 t0, t1
+unzip8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 28
+# CHECK-S-OBJ: zip4 t0, t1
+zip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 28
+# CHECK-S-OBJ: unzip4 t0, t1
+unzip4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 30
+# CHECK-S-OBJ: zip2 t0, t1
+zip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 30
+# CHECK-S-OBJ: unzip2 t0, t1
+unzip2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 31
+# CHECK-S-OBJ: zip t0, t1
+zip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 31
+# CHECK-S-OBJ: unzip t0, t1
+unzip x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
+# CHECK-S-OBJ: orc.p t0, t1
+orc.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2
+# CHECK-S-OBJ: orc2.n t0, t1
+orc2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3
+# CHECK-S-OBJ: orc.n t0, t1
+orc.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4
+# CHECK-S-OBJ: orc4.b t0, t1
+orc4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6
+# CHECK-S-OBJ: orc2.b t0, t1
+orc2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: orc.b t0, t1
+# CHECK-S-OBJ: orc.b t0, t1
+orc.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8
+# CHECK-S-OBJ: orc8.h t0, t1
+orc8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12
+# CHECK-S-OBJ: orc4.h t0, t1
+orc4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14
+# CHECK-S-OBJ: orc2.h t0, t1
+orc2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15
+# CHECK-S-OBJ: orc.h t0, t1
+orc.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16
+# CHECK-S-OBJ: orc16.w t0, t1
+orc16.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24
+# CHECK-S-OBJ: orc8.w t0, t1
+orc8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28
+# CHECK-S-OBJ: orc4.w t0, t1
+orc4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30
+# CHECK-S-OBJ: orc2.w t0, t1
+orc2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31
+# CHECK-S-OBJ: orc.w t0, t1
+orc.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 32
+# CHECK-S-OBJ: orc32 t0, t1
+orc32 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 48
+# CHECK-S-OBJ: orc16 t0, t1
+orc16 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 56
+# CHECK-S-OBJ: orc8 t0, t1
+orc8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 60
+# CHECK-S-OBJ: orc4 t0, t1
+orc4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 62
+# CHECK-S-OBJ: orc2 t0, t1
+orc2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 63
+# CHECK-S-OBJ: orc t0, t1
+orc x5, x6
+
+# CHECK-S-OBJ-NOALIAS: rori t0, t1, 8
+# CHECK-S-OBJ: rori t0, t1, 8
+ror x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: roriw t0, t1, 8
+# CHECK-S-OBJ: roriw t0, t1, 8
+rorw x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 13
+# CHECK-S-OBJ: grevi t0, t1, 13
+grev x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 13
+# CHECK-S-OBJ: gorci t0, t1, 13
+gorc x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 13
+# CHECK-S-OBJ: shfli t0, t1, 13
+shfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 13
+# CHECK-S-OBJ: unshfli t0, t1, 13
+unshfl x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: greviw t0, t1, 13
+# CHECK-S-OBJ: greviw t0, t1, 13
+grevw x5, x6, 13
+
+# CHECK-S-OBJ-NOALIAS: gorciw t0, t1, 13
+# CHECK-S-OBJ: gorciw t0, t1, 13
+gorcw x5, x6, 13
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
-
# With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip CRC extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbs < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbs - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbs < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbs - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ Match both the .s and objdumped object output with
+# aliases enabled
+# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: bseti t0, t1, 8
+# CHECK-S-OBJ: bseti t0, t1, 8
+bset x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: bclri t0, t1, 8
+# CHECK-S-OBJ: bclri t0, t1, 8
+bclr x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: binvi t0, t1, 8
+# CHECK-S-OBJ: binvi t0, t1, 8
+binv x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
+# CHECK-S-OBJ: bexti t0, t1, 8
+bext x5, x6, 8
+++ /dev/null
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s
-
-# Too few operands
-bclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-bsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-binvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-bclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Immediate operand out of range
-bclriw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-bclriw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-# Too few operands
-bsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Immediate operand out of range
-bsetiw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-bsetiw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-# Too few operands
-binviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Immediate operand out of range
-binviw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-binviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+++ /dev/null
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# With Bitmanip single bit extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
-bclrw t0, t1, t2
-# CHECK-ASM-AND-OBJ: bsetw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28]
-bsetw t0, t1, t2
-# CHECK-ASM-AND-OBJ: binvw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68]
-binvw t0, t1, t2
-# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48]
-bextw t0, t1, t2
-# CHECK-ASM-AND-OBJ: bclriw t0, t1, 0
-# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48]
-bclriw t0, t1, 0
-# CHECK-ASM-AND-OBJ: bsetiw t0, t1, 0
-# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28]
-bsetiw t0, t1, 0
-# CHECK-ASM-AND-OBJ: binviw t0, t1, 0
-# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68]
-binviw t0, t1, 0
-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
# With Bitmanip ternary extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbt -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP
; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-zbb -S < %s | FileCheck %s --check-prefixes=CPOP
-; RUN: opt -loop-idiom -mtriple=riscv32 -mattr=+experimental-b -S < %s | FileCheck %s --check-prefixes=CPOP
-; RUN: opt -loop-idiom -mtriple=riscv64 -mattr=+experimental-b -S < %s | FileCheck %s --check-prefixes=CPOP
; RUN: opt -loop-idiom -mtriple=riscv32 -S < %s | FileCheck %s --check-prefixes=NOCPOP
; RUN: opt -loop-idiom -mtriple=riscv64 -S < %s | FileCheck %s --check-prefixes=NOCPOP
projects / platform / upstream / llvm.git / commitdiff