arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Sat, 15 Jun 2019 10:38:31 +0000 (12:38 +0200)
committerKevin Hilman <khilman@baylibre.com>
Thu, 20 Jun 2019 03:34:14 +0000 (20:34 -0700)
The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.

Replace snps,reset-gpio from the &ethmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.

snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.

Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet
  mentions: "For a complete PHY reset, this pin must be asserted low
  for at least 10ms") and a 30ms deassert delay (the datasheet
  mentions: "Wait for a further 30ms (for internal circuits settling
  time) before accessing the PHY register". This applies to the
  following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95
  variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox
  A1, GXM Q200, GXM RBox Pro boards.
- the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet
  mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms
  as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
  output ready after reset released | 10ms"). This applies to the GXBB
  Nexbox A95X board.
- the Micrel KSZ9031 seems to require a 100us delay but use the same
  (seemingly safe) values from RTL8211F due to lack of a board to verify
  this. This applies to the GXBB P200 board.

The GXBB P201 board is left out from this conversion because it doesn't
have a dedicated PHY node (because it's not clear which PHY is used on
that board).

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts

index 849c01650c4db559451abf830fac6142beba27bd..c34c1c90ccb6b91a387007f4b70e219ddb1ad59f 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        mdio {
                compatible = "snps,dwmac-mdio";
                #address-cells = <1>;
                eth_phy0: ethernet-phy@0 {
                        /* Realtek RTL8211F (0x001cc916) */
                        reg = <0>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <30000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                        interrupt-parent = <&gpio_intc>;
                        /* MAC_INTR on GPIOZ_15 */
                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
index 3c54f26eef15b061a2f03b9e96473f2f221ab309..b636912a271578f89a8836bb796f6d07b432737a 100644 (file)
        phy-handle = <&eth_phy0>;
        phy-mode = "rmii";
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        mdio {
                compatible = "snps,dwmac-mdio";
                #address-cells = <1>;
                eth_phy0: ethernet-phy@0 {
                        /* IC Plus IP101GR (0x02430c54) */
                        reg = <0>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <10000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
                };
        };
 };
index 5a139e7b1c60b853fd513a7119a3e2b6d97746d1..9972b1515da617993c7a872db083bd37ba10b32b 100644 (file)
        phy-handle = <&eth_phy0>;
        phy-mode = "rgmii";
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        amlogic,tx-delay-ns = <2>;
 
        mdio {
                eth_phy0: ethernet-phy@0 {
                        /* Realtek RTL8211F (0x001cc916) */
                        reg = <0>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <30000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                        interrupt-parent = <&gpio_intc>;
                        /* MAC_INTR on GPIOZ_15 */
                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
index 9d2406a7c4fadc21cd438cb75a5c3f30db224a8e..3c93d1898b4099bad289fa94bb8adb5284101e4a 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        mdio {
                compatible = "snps,dwmac-mdio";
                #address-cells = <1>;
                eth_phy0: ethernet-phy@3 {
                        /* Micrel KSZ9031 (0x00221620) */
                        reg = <3>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <30000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                        interrupt-parent = <&gpio_intc>;
                        /* MAC_INTR on GPIOZ_15 */
                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
index 18856f28fd60563d3ed14e52e15fbb001670ee3c..43b11e3dfe1194883f3520af00fcd3196091a477 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        mdio {
                compatible = "snps,dwmac-mdio";
                #address-cells = <1>;
                eth_phy0: ethernet-phy@0 {
                        /* Realtek RTL8211F (0x001cc916) */
                        reg = <0>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <30000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                        interrupt-parent = <&gpio_intc>;
                        /* MAC_INTR on GPIOZ_15 */
                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
index 9ef6858779c1b668269e1023685cf996a4fa01e7..4c539881fbb73f46fd2693a6a110161f718fe3a9 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        mdio {
                compatible = "snps,dwmac-mdio";
                #address-cells = <1>;
                eth_phy0: ethernet-phy@0 {
                        /* Realtek RTL8211F (0x001cc916) */
                        reg = <0>;
+
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <30000>;
+                       reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
                };
        };
 };
index 767b1763a6124c7681386d92cf97008c37ac1a8b..b08c4537f260dbfc556f6252ed0f00e66713da55 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       /* External PHY reset is shared with internal PHY Led signals */
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        /* External PHY is in RGMII */
        phy-mode = "rgmii";
 };
                /* Realtek RTL8211F (0x001cc916) */
                reg = <0>;
                max-speed = <1000>;
+
+               /* External PHY reset is shared with internal PHY Led signal */
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
+               reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                interrupt-parent = <&gpio_intc>;
                interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
                eee-broken-1000t;
index ff4f0780824d98b8687f1bbaf0471e4bdabe7fcb..989d33ac6eae80d69976ae15b4287784487b932d 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       /* External PHY reset is shared with internal PHY Led signals */
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        /* External PHY is in RGMII */
        phy-mode = "rgmii";
 
        external_phy: ethernet-phy@0 {
                /* Realtek RTL8211F (0x001cc916) */
                reg = <0>;
+
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
+               reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                interrupt-parent = <&gpio_intc>;
                /* MAC_INTR on GPIOZ_15 */
                interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
index 29715eae14a9aa6143307009952ca062827e7509..c2bd4dbbf38c5408a2fbe3b34de0c4e8224d81cb 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        /* External PHY is in RGMII */
        phy-mode = "rgmii";
 };
                /* Realtek RTL8211F (0x001cc916) */
                reg = <0>;
                max-speed = <1000>;
+
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
+               reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
        };
 };
 
index 8939c0fc5b6254f1092f33b10de90af7dfc77914..ea45ae0c71b7f16d00596453d13c628af25bd368 100644 (file)
 
        amlogic,tx-delay-ns = <2>;
 
-       /* External PHY reset is shared with internal PHY Led signals */
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        /* External PHY is in RGMII */
        phy-mode = "rgmii";
 };
                /* Realtek RTL8211F (0x001cc916) */
                reg = <0>;
                max-speed = <1000>;
+
+               /* External PHY reset is shared with internal PHY Led signal */
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
+               reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
                interrupt-parent = <&gpio_intc>;
                /* MAC_INTR on GPIOZ_15 */
                interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
index 13de1e8f58b5bae5f8e4a4c622e0781f91f78818..5cd4d35006d097951c045f00221e4a59a806774a 100644 (file)
        /* Select external PHY by default */
        phy-handle = <&external_phy>;
 
-       snps,reset-gpio = <&gpio GPIOZ_14 0>;
-       snps,reset-delays-us = <0 10000 1000000>;
-       snps,reset-active-low;
-
        amlogic,tx-delay-ns = <2>;
 
        /* External PHY is in RGMII */
                /* Realtek RTL8211F (0x001cc916) */
                reg = <0>;
                max-speed = <1000>;
+
+               reset-assert-us = <10000>;
+               reset-deassert-us = <30000>;
+               reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
        };
 };