MachineInstr *MI = SU->getInstr();
MachineOperand &MO = MI->getOperand(OperIdx);
unsigned Reg = MO.getReg();
+ // We do not need to track any dependencies for constant registers.
+ if (MRI.isConstantPhysReg(Reg))
+ return;
// Optionally add output and anti dependencies. For anti
// dependencies we use a latency of 0 because for a multi-issue
; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
-; CHECK: cmp x0, #0
-; CHECK-DAG: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
+; CHECK-DAG: cmp x0, #0
+; CHECK: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]
--- /dev/null
+# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=misched 2>&1 | FileCheck %s
+# REQUIRES: asserts
+--- |
+ define void @func() { ret void }
+...
+---
+# Check that the instructions are not dependent on each other, even though
+# they all read/write to the zero register.
+# CHECK-LABEL: MI Scheduling
+# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+# CHECK: SU(1): %W2<def> = COPY %WZR
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+# CHECK: SU(3): %W4<def> = COPY %WZR
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+name: func
+body: |
+ bb.0:
+ dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv
+ %w2 = COPY %wzr
+ dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv
+ %w4 = COPY %wzr
+...