#define STAT_TR_IDLE 22
#define STAT_TR_RDY 24
-struct etrax_serial_t
+struct etrax_serial
{
CPUState *env;
CharDriverState *chr;
uint32_t r_masked_intr;
};
-static void ser_update_irq(struct etrax_serial_t *s)
+static void ser_update_irq(struct etrax_serial *s)
{
s->r_intr &= ~(s->rw_ack_intr);
s->r_masked_intr = s->r_intr & s->rw_intr_mask;
static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
- struct etrax_serial_t *s = opaque;
+ struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
uint32_t r = 0;
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- struct etrax_serial_t *s = opaque;
+ struct etrax_serial *s = opaque;
unsigned char ch = value;
D(CPUState *env = s->env);
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
- struct etrax_serial_t *s = opaque;
+ struct etrax_serial *s = opaque;
s->r_intr |= 8;
s->rs_stat_din &= ~0xff;
static int serial_can_receive(void *opaque)
{
- struct etrax_serial_t *s = opaque;
+ struct etrax_serial *s = opaque;
int r;
/* Is the receiver enabled? */
void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
target_phys_addr_t base)
{
- struct etrax_serial_t *s;
+ struct etrax_serial *s;
int ser_regs;
s = qemu_mallocz(sizeof *s);