usb: dwc2: add optional usb ecc reset bit

The dwc2 USB controller in Stratix10 has an additional ECC reset bit that
needs to get de-asserted in order for the controller to work properly.

Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index f66c941..f22f2e9 100644 (file)
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -925,6 +925,7 @@ struct dwc2_hsotg {
        int     irq;
        struct clk *clk;
        struct reset_control *reset;
+       struct reset_control *reset_ecc;
 
        unsigned int queuing_high_bandwidth:1;
        unsigned int srp_success:1;

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 3e26550..4703478 100644 (file)
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -221,6 +221,15 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 
        reset_control_deassert(hsotg->reset);
 
+       hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
+       if (IS_ERR(hsotg->reset_ecc)) {
+               ret = PTR_ERR(hsotg->reset_ecc);
+               dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
+               return ret;
+       }
+
+       reset_control_deassert(hsotg->reset_ecc);
+
        /* Set default UTMI width */
        hsotg->phyif = GUSBCFG_PHYIF16;
 
@@ -319,6 +328,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
                dwc2_lowlevel_hw_disable(hsotg);
 
        reset_control_assert(hsotg->reset);
+       reset_control_assert(hsotg->reset_ecc);
 
        return 0;
 }